KR950013791B1 - Making method of gate electrode on the buried contact - Google Patents
Making method of gate electrode on the buried contact Download PDFInfo
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- KR950013791B1 KR950013791B1 KR1019920024504A KR920024504A KR950013791B1 KR 950013791 B1 KR950013791 B1 KR 950013791B1 KR 1019920024504 A KR1019920024504 A KR 1019920024504A KR 920024504 A KR920024504 A KR 920024504A KR 950013791 B1 KR950013791 B1 KR 950013791B1
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- 238000000034 method Methods 0.000 title claims abstract description 17
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 23
- 229920005591 polysilicon Polymers 0.000 claims abstract description 23
- 238000005530 etching Methods 0.000 claims abstract description 17
- 239000000758 substrate Substances 0.000 claims abstract description 16
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 13
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 13
- 239000004065 semiconductor Substances 0.000 claims abstract description 10
- 239000012535 impurity Substances 0.000 claims abstract description 9
- 238000001312 dry etching Methods 0.000 claims abstract description 7
- 238000000151 deposition Methods 0.000 claims abstract description 5
- 229910052723 transition metal Inorganic materials 0.000 claims description 14
- 150000003624 transition metals Chemical class 0.000 claims description 13
- 229910052721 tungsten Inorganic materials 0.000 claims description 4
- 239000010937 tungsten Substances 0.000 claims description 4
- 238000010438 heat treatment Methods 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 claims description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 3
- 238000000137 annealing Methods 0.000 claims description 2
- 239000005380 borophosphosilicate glass Substances 0.000 claims description 2
- 239000012299 nitrogen atmosphere Substances 0.000 claims description 2
- 229910052751 metal Inorganic materials 0.000 abstract description 5
- 239000002184 metal Substances 0.000 abstract description 5
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 230000002411 adverse Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- RLOWWWKZYUNIDI-UHFFFAOYSA-N phosphinic chloride Chemical compound ClP=O RLOWWWKZYUNIDI-UHFFFAOYSA-N 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
- -1 tungsten transition metal Chemical class 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
- H01L21/02129—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/32055—Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
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Abstract
Description
제 1 도는 매립 콘택 형성 후 게이트전극을 형성한 상태의 평면도.1 is a plan view of the gate electrode formed after the buried contact is formed.
제 2a도 내지 제2c도는 종래기술에 따른 게이트전극 형성 과정을 나타내는 제 1 도의 A-A'선을 따른 단면도.2A to 2C are cross-sectional views taken along line AA ′ of FIG. 1 showing a gate electrode forming process according to the prior art.
제 3a도 내지 제 3e도는 본 발명의 일실시예에 따른 게이트전극 형성과정을 나타내는 제 1 도의 A-A'선을 따른 단면도.3A to 3E are cross-sectional views taken along line AA ′ of FIG. 1 showing a process of forming a gate electrode according to an embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
30, 38 : 감광막패턴 31 : 실리콘 기판30, 38: photosensitive film pattern 31: silicon substrate
32 : 게이트산화막 33, 36 : 폴리실리콘막32: gate oxide film 33, 36: polysilicon film
34 : PSG막 35 : 실리사이드막34 PSG film 35 Silicide film
37 : 텡스텐(W) 전이금속막37: tungsten (W) transition metal film
본 발명은 반도체 소자 제조공정중 게이트전극 형성방법에 관한 것으로, 특히 매립(buried) 형태의 콘택위에 게이트전극 패턴 형성을 위한 식각시 상기 게이트전극 하부 측벽의 기판이 식각되어 트랜치가 형성되는 것을 방지하기 위한 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a gate electrode during a semiconductor device manufacturing process. In particular, when etching a gate electrode pattern on a buried contact, the substrate on the lower sidewall of the gate electrode is etched to prevent the formation of a trench. It is about a method.
제 1 도는 매립 콘택 형성 후 게이트전극을 형성한 상태의 평면도이고, 제2a도 내지 제2c도는 종래기술에 따른 게이트전극 형성과정을 나타내는 제 1 도의 A-A'선을 따른 단면도로서, 이를 통하여 종래기술을 살펴보면 다음과 같다.FIG. 1 is a plan view of a gate electrode formed after a buried contact is formed, and FIGS. 2a to 2c are cross-sectional views taken along line A-A 'of FIG. 1 showing a process of forming a gate electrode according to the prior art. The technology is as follows.
먼저, 제2a도는 반도체 기판(1)상에 150 내지 250Å 두께의 게이트산화막(2), 400 내지 600Å 두께의 폴리실리콘막(3)을 형성한 다음, 감광막패턴(4)을 형성하고, 상기 감광막패턴(4)을 식각마스크로 사용하여 하부의 상기 폴리실리콘막(3), 게이트산화막(2)을 차례로 식각하여 콘텍홀을 형성한 상태의 단면도이다.First, in FIG. 2A, a gate oxide film 2 having a thickness of 150 to 250 kPa and a polysilicon film 3 having a thickness of 400 to 600 kPa are formed on the semiconductor substrate 1, and then a photosensitive film pattern 4 is formed. A cross-sectional view of a state in which contact holes are formed by sequentially etching the polysilicon film 3 and the gate oxide film 2 at the lower side using the pattern 4 as an etching mask.
이어서, 제2b도는 상기 감광막패턴(4)을 제거한 다음, 전체 상부에 폴리실리콘막(5)을 1000 내지 2000Å 두께 증착하고 PCOl3를 도핑한 다음, 상기 도핑된 폴리실리콘막(5) 상부에 1500 내지 2500Å 두께의 실리사이드막(6)을 증착한 후 계속해서, 상기 실리사이드막(6) 상부에 게이트전극 패턴 형성용 감광막패턴(7)을 형성한 상태의 단면도이다.Subsequently, in FIG. 2B, after removing the photoresist pattern 4, the polysilicon film 5 is deposited to a thickness of 1000 to 2000 에 on the entire surface, and the doped PCO 3 is doped. After the deposition of the silicide film 6 having a thickness of 2,500 GHz or more, the cross-sectional view of the photoresist film pattern 7 for forming a gate electrode pattern is formed on the silicide film 6.
끝으로, 제2c도는 상기 감광막 패터(7)을 식각마스트로 사용하여 하부의 상기 실리사이드막(6), 폴리실리콘막(5)을 차례로 건식 식각하여 게이트전극을 형성한 상태의 단면도이다.Finally, FIG. 2C is a cross-sectional view of the gate electrode being formed by dry etching the lower silicide layer 6 and the polysilicon layer 5 sequentially using the photosensitive layer pattern 7 as an etching mask.
그러나, 상기 종래방법에 따라 게이트전극을 형성할 경우, 게이트전극 패턴형성을 위한 식각시 과도식각으로 인하여 게이트전극 하부 측벽의 기판이 식가되어 트랜치가 형성됨으로 인해 소자의 특성에 악영향을 끼치는 문제점이 따랐다.However, in the case of forming the gate electrode according to the conventional method, there is a problem in that the substrate on the lower sidewall of the gate electrode is etched due to the excessive etching during the etching for forming the gate electrode pattern, thereby adversely affecting the characteristics of the device. .
상기와 같은 종래기술의 문제점을 행결하기 위하여 안출된 본 발명은 매립(bruied) 형태의 콘택위에 게이트전극 패턴 형성을 위한 식각시 상기 게이트전극 하부 측벽의 기판이 식각되어 트랜치가 형성되는 것을 방지하기 위한 매립 형태의 콘택위에 게이트전극 형성 방법을 제공하는데 그 목적이 있다.The present invention has been made in order to solve the problems of the prior art as described above is to prevent the formation of the trench by etching the substrate of the lower sidewall of the gate electrode when etching to form a gate electrode pattern on the buried (contact) type It is an object of the present invention to provide a method for forming a gate electrode on a buried contact.
상기 목적을 달성하기 위하여 본 발명은 반도체 소자 제조공정 중 매립 콘택 형성 후 게이트전극을 형성하는 방법에 있어서, 반도체 기판에 게이트산화막, 제 1 폴리실리콘막, 불순물 도핑된 절연막을 적층하는 제 1 단계 ; 콘택영역의 상기 불순물 도핑된 절연막, 제 1 폴리실리콘막, 게이트산화막을 차례로 식각하여 상기 반도체 기판의 콘택영역을 노출시키는 제 2 단계 ; 열처리하여 상기 불순물도핑된 절연막을 플로우시키는 제 3 단계 ; 상기 제 1 단계 내지 제 3 단계에 의한 구조의 전체 상부에 제 1 전이금속막을 증착한 다음 열처리하여 상기 콘택영역 상부에 실리사이드막을 형성하는 제 4 단계 ; 상기 불순물 도핑된 절연막 위의 제 1 전이 금속막을 제거하는 제 5 단계 ; 제 1 단계 내지 제 5 단계에 의한 구조의 전체 상부에 제 2 폴리실리콘막, 제 2 전이금속막을 형성하는 제 6 단계 ; 및 콘택영역외의 상기 제 2 전이금속막 및 제 2 폴리실리콘막을 건식식각하여 상기 실리사이드막 상부에만 잔류하도록 하는 제 7 단계를 포함하여 이루어지는 것을 특징으로 한다.According to an aspect of the present invention, there is provided a method of forming a gate electrode after forming a buried contact in a semiconductor device manufacturing process, the method comprising: stacking a gate oxide film, a first polysilicon film, and an impurity doped insulating film on a semiconductor substrate; Etching the impurity-doped insulating film, the first polysilicon film, and the gate oxide film in the contact region in order to expose the contact region of the semiconductor substrate; A third step of heat treating the impurity doped insulating film; A fourth step of depositing a first transition metal film over the entire structure of the first to third steps and then performing heat treatment to form a silicide film on the contact region; A fifth step of removing the first transition metal film on the impurity doped insulating film; A sixth step of forming a second polysilicon film and a second transition metal film over the entire structure of the first to fifth steps; And a seventh step of dry etching the second transition metal film and the second polysilicon film outside the contact region so as to remain only on the silicide layer.
이하, 첨부된 도면 제3a도 내지 제3e도를 참조하여 본 발명의 실시예를 상술한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to FIGS. 3A to 3E.
제3a도 내지 제3e도는 본 발명의 일실시예에 따른 게이트전극 형성과정을 나타내는 제 1 도의 A-A'선을 따른 단면도로서, 먼저, 제3a도에 도시된 바와 같이 실리콘 기판(31)상에 150 내지 250Å 두께의 게이트산화막(32), 400 내지 600Å 두께의 폴리실리콘막(33), 500 내지 1000Å 정도의 PSG막(34)을 적충한 후, 감광막패턴(30)을 형성하고, 상기 감광막패턴(30)을 식각마스크로 사용하여 하부의 상기 PSG막(34), 폴리실리콘막(33), 게이트산화막(32)을 차례로 식각하여 콘택홀을 형성한다. 상기 PSG막은 불순물 도핑된 절연막으로 BPSG막도 가능한다.3A to 3E are cross-sectional views taken along line AA ′ of FIG. 1 illustrating a process of forming a gate electrode according to an embodiment of the present invention. First, as shown in FIG. 3A, a silicon substrate 31 is formed on the substrate 31. A gate oxide film 32 having a thickness of 150 to 250 kPa, a polysilicon film 33 having a thickness of 400 to 600 kPa, and a PSG film 34 having a thickness of about 500 to 1000 kPa are loaded thereon, and then a photosensitive film pattern 30 is formed. The PSG layer 34, the polysilicon layer 33, and the gate oxide layer 32 are sequentially etched using the pattern 30 as an etching mask to form a contact hole. The PSG film is an impurity doped insulating film and may also be a BPSG film.
이어서, 상기 감광막패턴(30)을 제거한 다음 제3b도에 도시된 바와 같이 800 내지 1000℃의 온도하에서 N2분위기로 어닐링하여 PSG막(34)을 플로우시킨다. 여기서, 상기 PSG막(34)의 플로우는 게이트전극과 게이트산화막간의 절연효과를 증대시키기 위함이다.Subsequently, the photoresist pattern 30 is removed and then the PSG film 34 is flowed by annealing in an N 2 atmosphere at a temperature of 800 to 1000 ° C. as shown in FIG. 3B. Here, the flow of the PSG film 34 is to increase the insulation effect between the gate electrode and the gate oxide film.
계속해서, 제3c도에서 상기 구조 전체 상부에 텅스텐(W) 전이금속막을 증착한 다음 열처리하여 상기 실리콘 기판과 접한 부위에 실리사이드막(35)을 형성한 후, 상기 PSG막(34) 위의 전이금속막을 모두 제거한다. 이때, 상기 실리사이드막(35)의 두께는 500내지 1000Å 정도이다.Subsequently, in FIG. 3C, a tungsten (W) transition metal film is deposited over the entire structure, and then heat-treated to form a silicide film 35 in contact with the silicon substrate, and then a transition on the PSG film 34. Remove all metal films. At this time, the thickness of the silicide film 35 is about 500 to 1000 GPa.
다음으로, 상기 PSG막934)을 HF로 모두 제거한 후 제3d도에 도시된 바와 같이 폴리실리콘막(36)을 1000 내지 2000Å 두께로 증착하고 POCl3를 도핑한 다음, HF로 자연 산화막을 제거하고, 상기 도핑된 폴리실리콘막(36) 상부에 다시 텅스텐 전이금속막(37)을 1500 내지 2500Å 두께로 증착하고 콘택영역의 상기 전이금속막(37) 상부에 감광막패턴(38)을 형성한다.Next, after removing all of the PSG film 934 with HF, as shown in FIG. 3d, the polysilicon film 36 was deposited to a thickness of 1000 to 2000 microns, doped with POCl 3 , and then the natural oxide film was removed with HF. In addition, a tungsten transition metal film 37 is deposited on the doped polysilicon film 36 to a thickness of 1500 to 2500 Å, and a photoresist pattern 38 is formed on the transition metal film 37 in the contact region.
끝으로, 제3e도에 도시된 바와 같이 상기 감광막패턴(28)을 식각마스크로 사용하여 하부의 상기 전이금속막(37), 폴리실리콘막(36)을 SF6및 Cl2가스로 차례로 건식식각한 후 상기 감광막패턴(38)을 제거하여 게이트전극 패턴을 형성한다. 여기서, 상기 건식식각시 도핑된 폴리실리콘(36)과 실리사이드막(35)의 높은 식각선택비를 이용함으로써 게이트전극 측면의 실리콘기판에 트렌치가 형성되는 것을 방지할 수 있다.Finally, as shown in FIG. 3e, dry etching of the lower transition metal layer 37 and the polysilicon layer 36 using SF 6 and Cl 2 gas is performed in sequence using the photoresist pattern 28 as an etching mask. Thereafter, the photoresist pattern 38 is removed to form a gate electrode pattern. Here, the trench may be prevented from being formed in the silicon substrate on the side of the gate electrode by using the high etching selectivity of the doped polysilicon 36 and the silicide layer 35 during the dry etching.
상기와 같이 이루어지는 본 발명은 매립 형태의 콘택위에 게이트전극 패턴 형성을 위한 식각시 과도식각으로 인해 게이트전극 하부측벽의 기판이 식가되어 트랜치가 형성되는 것을 방지할 수 있다.The present invention made as described above can prevent the formation of the trench by etching the substrate of the lower side wall of the gate electrode due to the excessive etching during the etching for forming the gate electrode pattern on the buried contact.
Claims (5)
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| KR1019920024504A KR950013791B1 (en) | 1992-12-16 | 1992-12-16 | Making method of gate electrode on the buried contact |
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| KR1019920024504A KR950013791B1 (en) | 1992-12-16 | 1992-12-16 | Making method of gate electrode on the buried contact |
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| KR950013791B1 true KR950013791B1 (en) | 1995-11-16 |
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