CA1131796A

CA1131796A - Method for fabricating mos device with self-aligned contacts

Info

Publication number: CA1131796A
Application number: CA339,798A
Authority: CA
Inventors: Tarsaim L. Batra
Original assignee: American Microsystems Holding Corp
Current assignee: American Microsystems Holding Corp
Priority date: 1979-01-08
Filing date: 1979-11-14
Publication date: 1982-09-14
Also published as: JPS5593271A; NL7908534A; FR2446011A1; GB2040564A; FR2446011B3; DE3000121A1; IT8019078A0

Abstract

Abstract of the Disclosure A method for fabricating an integrated circuit semiconduct-or device comprised of an array of MOSFET elements having self-aligned or self-registered connections with conductive interconnect lines. The method involves the formation on a substrate of a thick oxide insulation layer surrounding openings therein for the MOSFET
elements. A gate electrode within each opening is utilized to pro-vide self-registered source and drain regions and is covered on all sides and on its top surface with a dielectric layer. After source-drain diffusions a relatively thin dielectric protective layer is initially applied to the entire chip prior to the appli-cation of an upper insulative layer. When oversized windows are etched in the upper insulative layer the protective layer prevents overetching of the gate dielectric layer thus preventing shorts or leaks between conductive and active areas and providing self-aligned contacts with minimum spacing from adjacent conductive areas. With the present method the additional internal protection is provided for in MOS devices with source-drain regions formed either by diffusion or ion implantation.

Description

~ 1'796 S P E C I F I C A T I O N S

8ackground of ~he Invention 1 The present invention relates to integrated circuit semi-

2 conductor devices and more particularly to a method for fabricating

3 such devices with self-aligned contacts.

4 Large-scale integrated circuits,often having thousands of

5 MOSFET's on a single semiconductor chip, must have a ~Nl~plicitv of

6 contacts to provide the necessary interconnections between circuit

7 lines, source-drain regions and gate electrodes of individual

8 transistor elements. Using prior art procedures, it is necessary

9 to make oversized conductive areas and larger contact openings in

10 order to accommodate mask alignment tolerances. This generally

11 results in devices requiring a relatively large chip area. With

12 the rapid increase in large-scale integrated circuit devices having

13 even greater numbers of MOSFET elements, efforts have been made to

14 reduce not only the element size but also the size of the required

15 contacts~ With the trend toward reduced design tolexances and

16 narrower interconnect lines this became an increasingly severe

17 problem. One suggested solu~ion described in J. Electrochem. Soc.

18 Solid State Science and Technology, Vol. 125, No. 3, March 1978,

19 pp. 471-472, is to provide a gate material of polycrystalline

20 silicon which was coated on its sides and top with a thin silicon

21 dioxide (Si02) layer; However, t-his proved to be unsatisfactory

22 because it fails to eliminate the problem of shorts due to

23 occasional breakdowns or fractures of the SiO2 layer during subse-

24 quent process steps. The present invention overcomes these and 25other problems and provides several other advantages in addition i~to providing a means for making a large-scale integrated circuit ~7device with a substantially smaller area per MOS transistor element ~ i , ~, r ~ 1 1131796 1 than was heretofore possible. Moreover, the invention makes pos-21 sible the production of such reduced area devices wherein the 31 source~drain regions of the MOSFET elements can be formed either 41 by standard diffusion or ion implantation techniques.

61 Brief Summary of the Invention I .. __ 71 In accordance with the principles of the present invention 8l ~IOSFET elements with self-aligned contacts forming an integrated 9¦ circuit device may be fabricated in a semiconductor substrate having a first conductivity type by a method wherein a permanent 11 ¦ internal protective layer is formed. Preliminary steps of the 12 ¦ method utilize conventional fabrication techniques. After the 13 ¦ field oxide areas are formed with openings for transistor elements, 14 ¦ polysilicon gate areas are provided within the openings~ Poly-15 ¦ silicon conductive lines are also simultaneously formed on the 6¦ field oxide close or adjacent to such openings where necessary~
17 I Thereafter, contact areas with the minimum dimensions required are 8¦ formed on opposite sides of each gate area and also where required 19 ¦ on the conductive lines. In one version of the present method, all 20¦ of these poly gates and conductive lines are first provided with a ~1¦ top layer of silicon nitride and thereafter a thin oxide layer on 22¦ their sides. Source-drain regions then are formed by diffusion 231 techniques and thereafter the thin protective layer of silicon 241 nitride is provided over the entire chip, covering the field oxide areas, the poly silicon areas and the areas surrounding the poly 26 gate areas. Now, a standard layer of phosphorous impregnated glass 271 (PVX) is also applied to the entire chip covering the thin nitride 28¦ layer, and thereafter a contact mask on the PVX layer is used to 29¦ form the necessary contact openings by first etching away the PVX
30~ in the contact openi.ng regions but stopping at the protective ll -2--11;~1796 1 nitride layer. The thick field oxide and the thin oxide layer on 2 the sides of the poly gate areas are prevented from being attacked 3 during this PVX etch by the thin nitride protective layer. Follow-4 ing this, the thin protective nitride layer in the contact areas 5 is etched away by an etchant that will not attack the field oxide 6 and the protective poly oxide. The thin layer of gate oxide 7 exposed by the contact opening is then removed. Thereafter, a 8 poly contact mask is used to form contact openings in the PVX layer 9 and the top nitride layer on the poly lines for the contacts on the 10 poly interconnect lines. Both of these latter masks can utilize 11 the relatively large openings to assure registration or self-align-12 ment with the desired contact areas, because the previously applied 13 thin nitride layer provides protection for the field oxide and the 14 poly oxide on the gate areas and assures against circuit shorts 15 between gates, poly lines and N+ interconnect lines. With this 16 added internal protection the alignment tolerances heretofore 17 required between poly gates, poly lines and contact openings are 18 substantially reduced, yet without requiring unusually close 19 tolerances on the contact masks for forming the contact openings.
20 The invention thus greatly reduces the problems of producing 21 integrated circuit devices with more closely packed elements per 22 unit area and yet a higher yield.
23 In an alternative form of the present method, the poly 24 gates and conductive lines, after being formed, are provided with

25 a thin silicon dioxide layer on their sides and also on their top

26 surface instead of the initial nitride layer. The source-drain

27 regions are then formed by ion implantation techniques with the

28 poly silicon gate serving as a mask in the well-known manner.

29 Thereafter, the thin internal protective nitride layer is applied

30 over the entire chip surface before fabrication is completed. The

31 protective layer again performs its function of preventing internal

32 shorts and any ;~

1 overetching of the thin oxide layer on the conductive poly gates 2¦ or poly lines and during the formation of oversized holes in the 31 insulating PVX layer.
41 In summary, the objects of the invention are: to provide an 51 improved method for forming semiconductor devices with self-aligned 61 contacts; to provide a method that will allow a reduction in the 7 spacing between contacts and conductive interconnect lines and 8 ¦ thereby facilitate production of more closely packed devices; to 9¦ provide`a method that can be easily controlled with standard 10 ¦ semiconductor production ~acilities; and to provide a method that 11 ¦ will significantly increase the production yield of large-scale 12 ¦ semiconductor devices with self-aligned contacts.

14 I Brief Description of the Drawing 15 ¦ Fig. l is plan view of a typical MOS transistor structure 16 ¦ with contacts formed as in the prior art;
~7 ¦ Fig. 2 is a plan view of an MOS transistor structure formed 18 with self-aligned contacts;
19 I Figs. 3a-14a illustrate the steps for forming self-aligned 20 ¦ contacts for a semiconductor device according to the method of the 21 ¦ present invention; and 22 Figs. 3b-14b illustrate the steps for forming self-aligned 231 contacts for a semiconductor device using a somewhat modified 24 method according to the present invention.

26 ¦ Detailed Description of the Preferred Embodiments 271 With reference to the drawing, Fig. 1 illustrates in plan 2~1 view a conventional MOS transistor 10 of the prior art having non-2g self-~ligned source and drain contacts 12 and 14 and a gate contact 16. Generally accepted design rules for snch transistors 13~796 in a large-scale integrated circuit required each contact on a source and drain region 18 and on a gate electrode 20 extending over it to have a minimum area. Because of alignment tolerances in forming such contacts using conventional fabrication proce-dures, it was necessary for the underlying source-drain region 18 - to be considerably larger than the minimum contact area in order to assure proper registration of the contacts~ For example, in order to have a minimum required contact area, a uniform toler-ance around all sides of the contacts (shown at Ll and L2) and predetermined minimum spacing between contact edge and poly sili-con edge (L3) was required using conventional fabrication technology. The design requirements resulted in an MOS semi-conductor device as shown in Fig. 1 in order to prevent shorts and leakage problems in an integrated circuit comprised of many such MOS devices.
The reduction in chip area that can be accomplished for a single MOS transistor lOa with self-aligned contacts is illustrated in Fig. 2. ~ere, the source, drain and gate contacts 12a, 14a and 16a, all having the minimum area, are automatically registered with the borders of their Source-drain region 18a or the gate electrode 20a and the surrounding field gxide~ The tolerances Ll, L2 and L3 are reduced to zero, and each diffused region 18a can have minimum dimensions in width and in length using conventional design rules. Also, because each contact is self-aligned or completely contained on its respective contact area, the spacing from an adjacent conductive line can be mini-mized, thereby further decreasing the overall chip area required for a semiconductor device.
The more important method steps for making such a semiconductor device with self-aligned contacts according to the present invention will now be described relative to Figs. 3a-14a.

' l ` 11;~1796 As shown in Fig. 3a, the method commences with the provision 2 of a semiconductor substrate 22 (e.g. ~ 100~ plane silicon 3 material) that is doped in the suitable range to provide the desir-4 able characteristics. Tllis su~strate is covered with an initial oxidation layer 24 of 500-lOOOA on which is deposited a second 6 layer 26 of silicon nitride of approximately equal thickness.
7 Using a field oxide mask, the layers 24 and 26 are removed 8 by etching in the field areas as indicated in Fig. 4a, and these 9 areas are then field implanted as indicated ~y the dotted lines 28 10¦ to adjust field threshold levels in the conventional manner.
11 As shown in ~ig. 5a, a relatively thick field oxide 30 is 12 now grown in the field areas, also in the conventional manner.
13 This drives the field implanted areas 28 further into the substrate 14 22 under the oxide areas. In a typical semiconductor structure, the field oxide is configured to form holes or openings within 16 which each MOS transistor is to be formed.
17 After the field oxide is formed, the original nitride layer 18 26 and the gate oxide layer 24 are removed by etching. Thereafter, 19 a new gate oxide layer 32 is formed within the hole in the field oxide.
21 Now, over the entire device surface, including the new oxide 22 layer 32 and the field oxide 30 (as shown in Fig. 6a), a thin (e.g.
23 150-300A) nitride layer 34 is deposited using conventional vapor 24 deposition techniques. In order to insure stability of the pro-duct, the upper ~urface of this ni~ride layer is oxidized in steam 26 or dry oxygen ambien~ ~not shown~. The ~tep ~llustr~ted in Pig. 6a 27 provides a new nitride/oxide sand~ich that ha~n't undergone the 28 heat treatment which was applied during formation of the field 29 oxide adjusted ~o appropriate thicknesses. The original oxide/
3o nitride ~andwich 24,26, shown in ~ig. 3a, adiusted to appropriate . -6-'i, ': ' . , . - .

1 thicknesses, could be used as the gate dielectric.
21 In the next step of the method embodiment of Fig. 7a, a layer 3 36 of poly-crystalline silicon (poly) is deposited, by a standard 41 vapor deposition process, onto the entire surface of the chip being 51 fa~ricated to a typical thickness of around 3000-5000A.
6¦ A mask is then used to define gate electrodes 38 (as 71 shown in Figure 8a) within the active areas formed in the field 81 oxide and interconnect lines 40 situated on top of the field 91 oxide 30 and adjacent to one or more gate elements. At this 0 point, all portions of conductive poly within a field Gxide opening and on the field oxide are situated on a nitride/oxide 2¦ sandwich. Using known silicon gate procedures wherein the gate 13l serves as a mask, ion implantation techniques are employed, as 14 represented by the vertical arrows in Fig. 9a, to form source 5l and drain regions 42 and 44 just below the substrate surface 6¦ within the field oxide opening and on opposite sides of the poly-7¦ silicon gate 38.
8¦ In the next step, as shown in Fig. lOa, a layer 46 of sili-9 con-dioxide is grown on all sides and also on the top of all conductive poly areas including the gate poly areas 38 and the 21 adjacent poly interconnect lines 40. The thickness of this cover-22 ing layer on the poly is generally much greater than the gate oxide 23 32 (e.g. around 3000A), and its purpose is to provide a protective 24 layer on the poly for making the self-aligned contact structure.
In the next step, as also shown in Fig. lOa, a thin protec-26 tive nitride layer 48 is deposited over the entire structure at 27 this point, including the field areas 30, the source and drain 2~ areas 42 and 44 and the areas 38 and 40 of oxide covered poly.
29 This nitride layer will later serve to provide vital protection for field oxide and poly oxide during subsequent process steps.
Following this application of the thin nitride layer the entire ,: , ~:131~96 1 ~ chip, s shown in ~ig. lla, is covered with a relatively thick 2 ¦ layer 50 of phospho-silicate-glass (PVX) in the conventional 3 ¦ manner.
4 ¦ Now, as shown in Fig. 12a, a first mask (not shown) for 5 ¦ the N+ contacts is applied to the PVX and a suitable etchant (e.g.
6 ¦ buffered hydrofluoric acid) is used to etch away the PVX layer 50 7 in the contact area. As is well known, hydrofluoric acid does ¦ not affect nitride layers 34 and 46. A suitable etchant (e.g., 9 ¦ phosphoric acid) is then used to etch the nitride layers 34 and lOj 36 in the contact opening. Of importance, this nitride etch does 1¦ not attack field oxide 30, gate oxide 32 or oxide 46 which 12¦ protects poly 38. Gate oxide is then removed in the contact area 13 using a suitable etchant such a~ hydrofluoric acid. Of impor-14¦ tance, oxide layer 46 protecting poly 38 is significantly thicker lS than the gate oxide being removed, thus preventing appreciable 6¦ damage to protective oxide 46 during removal of the gate oxide.
7¦ With protective oxide 46 intact, contact metalization is later 18 deposited without forming electrical shorts to poly 38.
9¦ Thereafter, a second contact mask is applied to the chip 201 in the same manner as the first mask and etchants are used (again 21¦ in three steps) to etch away the PVX, nitride and the oxide on 22 the polysilicon lines. These latter two masks for the N+ and 23 polysilicon contacts may be applied in reverse order, if desired.
24 This leaves the chip, as shown in Fig. 13a, with the PVX layer 50 coincident with the thin nitride layer 48 having windows to 26¦ expose the drain contact area 42 and also an exposed contact 271 area 51 on the adjacent poly interconnect line 40 having no 28~ oxide coverino.
291 At this point, standard fabrication method steps can be used to deposit metal in the contact areas to define metal contacts 52 I! ;

`` ~13~796 1 and 54 as part of a desired metal interconnect pattern on the 2 semiconductor device. Generally, these metallization steps include 3 the evaporation of metal and definition thereof with an appropriate 4 metal mask and thereafter the application of a top protection di-S electric layer over the entire chip (not shown) for passivation.
6 In a modified version of method according to the present 7 invention, illustrated by Figs. 3b-14b, the initial steps of Figs.
8 3b-6b inclusive are identical to those of Figs. 3a-6a. However, 9 this modified version avoids the necessity for using ion implanta-tion equipment and procedures for forming the source and drain 11 regions.
12 Thus, as shown in Fig. 7b, a poly layer 36 having a typical - 8a -~, ~1~17~6 1 thickness in the range of 3000-5000A is formed on the chip over the 2 gate nitride layer 34 by ~onventional chemical vapor deposition 3 techniques. This poly layer is then doped by diffusing phosphorous 4 into it to make it more conductive. Thereafter, a nitride layer 56 5 having a thickness that is considerably greater than that of the 6 gate nitride layer 34 (e.g. l000-?OOOA) is deposited on the poly-7 silicon layer 36.
8 As shown in Fig. 8b, the polysilicon layer 36 is defined into 9 gate areas and interconnect lines by using a poly mask (not shown) 10 and standard etching techniques which removes the unwanted material 11 in the poly and nitride layers. This leaves the structure with a 12 doped polysilicon gate or electrode 38 within an area surrounded by 13 field oxide 30 and an adjacent poly interconnect line 40 situated 14 on the oxide, both o~ these poly elements having the nitride layer 15 56 on their top surfaces.
16 In the next step, shown in Fig. 9b, the poly gate elements 38 17 and the poly interconnect lines 40 are provided with an oxide layer 18 46 on their sides having a thickness of around 3000A. This is ac-19 complished by simple thermal oxidation in a chamber in accordance 20 with well-known procedures.
21 Now, as shown in Fig. lOb, the source and drain regions 22 ~2 and 44 are formed by diffusion techniques. First, using 23 suitable, well~known masking and etching techniques, the gate 24 nitride layer 34 is etched away from every surface except the tops 25 of poly layers 38 and 40. Then, the gate oxide layer 32 is etched 261 in all the areas surrounding the gate poly layer. Standard 27 diffusion procedures are now applied to form the source and drain 28 regions 42 and 44. Following this, a new thin gate oxide layer 29 58 is formed in the diffused regions, to a thickness of around 500A.
31 To the structure shown in Fig. lOb, a thin protective nitride 32 layer 60 (e.g. 150-300A) is applied. This layer 60 is thus much ~,,f~'` _g_ :

`~

thinner than the nitride layer 56, and as with the previous embodi-2 ment, layer 60 extends over the entire chip including the field 31 areas 30, the source and drain areas and the nitride covered gate 4 38 and line poly areas 40.

5 ¦ Now, the PVS layer 50 is applied (Fig. llb) and etched 6 (Figs. 12b and 13b), using contact masks in the same manner as 7 ¦previously described in respect to the first embodiment of the 8 method. Nitride layer 60 is then etched in the contact area in 9 ¦the same manner as in the previously described first embodiment, 10 without affecting gate oxide 58 and protective oxide 46. Thin 11 ¦oxide layer 58 is then removed from the contact area. Of impor-12 ¦tance, gate oxide 58 is significantly thinner than oxide layer 46 13 ¦protecting poly region 38. Thus, oxide layer 46 is not signifi-14 ¦cantly damaged during the removal of the gate oxide 58. With 15 oversized contact holes formed in the PVX layer as previously 16 ¦described, the metallization of the MOS elements on the chip is 17 ¦performed to form its metal contacts 52 and 54 with accompanying 18¦ interconnect lines in the standard manner as shown in Fig. 14b.

19¦ Because oxide 46 protecting poly 38 is not significantly damaged 201 during the formation of the contact, shorts between metallization 21¦ 52 and poly 38 are prevented.

22¦ By utilization of either embodiment of the method according 23¦ to the invention, it is possible to produce large-scale semiconduc-241 tor devices with a multiplicity of MOSFET elements having self-25 aligned contacts and therefore requiring a minimum of chip area in 26 a closely-packed array. For example, in a typical random access 271 memory (RAM) the area required for a single memory cell was 1344 28¦ square microns, whereas, with the self-aligned contacts made po-2g¦ sible using the present method, the same memory cell has an area of 301 only 950 square microns, reduction in area of approximately 30%.
31 Yet, with the method of the present invention, the yield of such ,, -10-li;~l796 1 closely-packed devices with self-aligned contacts can be even hi~her 2 than with prior conventional devices because the internal protective 3 nitride layers 48 and 60 maintain circuit integrity during critical 4 process steps by preventing shorts or failures heretofore caused 5 during the various process steps. While silicon nitride is a pre-6 ferred material for the protective layers, other materials could be 7 used such as silicon car~ide or aluminum oxide.
~ To those skilled in the art to which this invention relates, g many changes in construction and widely differing embodiments and - lOa -. ,, ~ .~, 11;~1~96 1~applications of the invention will suggest themselves without de-2 parting from the spirit and scope of the invention. The disclosures 3 and the description herein are purely illustrative and are not 6¦intended o be in any sense limiting.

lal 223 .

Claims

THE EMBODIMENTS OF THE INVENTION IN WHICH AN EXCLUSIVE
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:

1. A method for fabricating an integrated circuit semi-conductor device having a plurality of field effect transis-tor (FET) elements with self-registering electrical contacts on their source and drain regions and their gate electrodes connected to the device interconnection lines, said method comprising the steps of:
forming a patterned layer of field oxide on a semi-conductive substrate, of a first conductivity type to form active areas free from said field oxide on the substrate surface for the formation of said FET elements;
forming a relatively thin gate dielectric layer within said active areas;
forming a layer of conductive material over the surface of the substrate;
patterning said layer of conductive material into gate areas of a predetermined shape and thickness, over said gate dielectric layer within said open areas;
forming, within each said active area surrounded by said field oxide, doped silicon source and drain regions of a second conductivity type material opposite to said first conductivity type of said substrate, the boundaries of said source and drain regions being determined by the edge of said field oxide and by the edges of said gate areas whereby said source and drain regions are self-aligned with respect to the edges of said gate electrode;
forming a first layer of dielectric material on the sides and top of each said gate area of conductive material;
forming a relatively thin layer of protective material over the entire device including all areas of conduc-tive material in said active areas and said field oxide areas;
covering said thin layer of protective material on said device with a relatively thick layer of insulating material;
forming oversized contact openings through said insulating material over said gate electrode and over said source and drain regions where electrical contacts are to be formed to said source and drain regions;
removing said thin layer of protective material within said oversized contact openings;
removing said gate oxide from the surfaces of said source and drain regions within said oversized contact openings;
depositing a metallic-type, high-electrical conducti-vity interconnection line pattern on the surface of the wafer extending into said contact openings thereby forming elec-trical connections with said source and drain regions within said contact openings.

2. The method as described in Claim 1 wherein said layer of protective material is silicon nitride formed to a thickness in the range of 150.ANG. to 300.ANG..

3. The method as described in Claim 2 wherein the upper surface of said silicon nitride protective layer is oxidized before application of said insulating material.

4. The method as described in Claim 1 wherein said protective layer is silicon carbide.

5. The method as described in Claim 1 wherein said protective layer is aluminum oxide.

6. The method as described in Claim 1 wherein said gate dielectric layer is a sandwich of silicon nitride over silicon dioxide.

7. The method as described in Claim 1 wherein said conductive gate electrodes are polycrystalline silicon covered on all sides and on top with an outer layer of silicon dioxide

8. The method as described in Claim 7 wherein said source and drain regions are formed by ion implantation.

9. The method as described in Claim 1 wherein said first layer of silicon dioxide on said gate electrodes has a thickness of around 3000.ANG. to 5000.ANG..

10. The method as described in Claim 1 wherein conductive gate electrodes are polycrystalline silicon whose sides are covered with a layer of silicon dioxide and whose top is covered with a layer of silicon nitride.

11. The method as described in Claim 10 wherein the thickness of the silicon dioxide layer on the sides of said gate electrode is around 3000.ANG. to 5000.ANG. and wherein the thick-ness of said silicon nitride layer on the top thereof is around 1000.ANG. to 2000.ANG..

12. The method as described in Claim 10 wherein said source and drain regions for each said FET are formed by a diffusion process.

13. An integrated circuit semiconductor device having an array of field effect transistor (FET) elements each with self-aligned electrical contacts on their source and drain regions and their gate electrodes for connection with the device interconnection lines, said device comprising:
a doped semiconductive substrate of a first conduc-tive type;
field oxide regions above or recessed into said substrate surrounding active areas on the substrate surface for each of said FET elements;
a layer of conductive material of a predetermined shape and thickness forming said gate electrodes within said active areas;
a layer of protective material on the sides and top of each said gate electrode;
doped silicon source and drain regions of a second conductivity type material opposite to said first conductivity type of said substrate on opposite sides of said gate electrode, the boundaries of said source and drain regions being determined by the edges of said gate electrode and the edge of said field oxide;
a relatively thin layer of protective dielectric material covering substantially the entire top of each said integrated circuit device and having oversized contact openings located over said gate electrode and over said source and drain regions;
a relatively thick layer of insulating material covering said thin layer of protective material on said device and having oversized contact openings located over said gate electrode and over said source and drain regions;and a metallic-type, high-electrical conductivity inter-connection line pattern on said device extending into said contact openings to make electrical connections with said source and drain regions and with said gate electrode.

14. The semiconductor device as described in Claim 13, wherein said thin layer of protective dielectric material is silicon nitride having a thickness in the range of 150.ANG. to 300.ANG..