KR19980065726A - Self-aligned contact hole formation method - Google Patents

Abstract

A method of forming a self-aligned contact hole is disclosed. The method includes forming a gate pattern on a predetermined region of a semiconductor substrate, forming a spacer on the sidewall of the gate pattern, and a first heat treatment process for curing an etch damage applied to a surface of the resultant product on which the spacer is formed. And forming an interlayer insulating film on the first heat-treated resultant, and patterning the interlayer insulating film to expose a portion of the upper surface of the semiconductor substrate, the spacer, and the gate pattern between the gate patterns. And forming a dielectric film pattern, and performing a second heat treatment process to cure the etching damage applied to the surface of the resultant layer on which the interlayer dielectric film pattern is formed. Accordingly, the etching damage applied to the spacers formed on the sidewalls of the gate pattern and the upper surface of the gate pattern is cured, thereby preventing the etching of the upper surfaces of the spacers and the gate pattern exposed when the self-aligned contact holes are formed.

Description

Self-aligned contact hole formation method

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a contact hole for use in a semiconductor device, and more particularly to a method for forming a self-aligned contact hole.

Recently, as the degree of integration of semiconductor devices increases, research into a method of forming a fine pattern is becoming more active. Since the contact holes serve to connect different wires among the fine patterns, they are directly related to the electrical characteristics of the semiconductor device. Accordingly, a method of forming a fine contact hole suitable for a highly integrated semiconductor device has become very important. In particular, a method of increasing the misalignment margin for a photographic process when forming a contact hole for connecting a semiconductor substrate and an upper wiring between adjacent lower interconnections is indispensable in manufacturing a highly integrated semiconductor device. As a method of increasing the misalignment margin, a method of forming a self-aligned contact hole has been proposed.

1 is a process flowchart of forming a conventional self-aligned contact hole.

Referring to FIG. 1, the related art is a process of forming a gate pattern including a gate oxide layer pattern, a gate electrode, and a gate passivation layer pattern, which are sequentially stacked on a predetermined region of a semiconductor substrate, and a spacer on a sidewall of the gate pattern. And forming an interlayer insulating film on the entire surface of the resultant product on which the spacers are formed, and then patterning the self-aligned contact hole to expose the semiconductor substrate between the gate protective layer pattern, the spacer, and the gate pattern. And a step (7) of forming a conductive film covering the self-aligned contact hole and contacting the exposed semiconductor substrate.

2A to 2C are cross-sectional views illustrating a method of forming a conventional self-aligned contact hole according to the process flowchart of FIG. 1.

2A is a cross-sectional view for describing a step of forming the gate pattern 59. First, a gate oxide film, a gate electrode conductive film, and a gate protective film are sequentially formed on the semiconductor substrate 51. Here, a polysilicon film and a silicon nitride film doped with the conductive film for the gate electrode and the gate protective film, respectively, are widely used. Next, the gate protection film, the gate electrode conductive film, and the gate oxide film are successively patterned to sequentially stack the gate oxide film pattern 53, the gate electrode 55, and the gate on a predetermined region of the semiconductor substrate 51. A gate pattern 59 formed of the passivation layer pattern 57 is formed. Subsequently, source / drain regions 52 doped with impurities are formed on the surface of the semiconductor substrate 51 between the gate patterns.

2B is a cross-sectional view for explaining a step of forming the spacer 61. Specifically, a silicon nitride film is formed on the entire surface of the resultant source / drain region 52 and anisotropically etched to form the spacer 61 on the sidewall of the gate pattern 59. At this time, since the gate protection layer pattern 57 and the spacer 61 are subjected to an etch damage during anisotropic etching to have a porous film quality, the etching rate changes very rapidly during the subsequent etching process. In addition, since the etching damage is also caused to the source / drain regions 52 exposed between the gate patterns 59, crystal defects are generated, thereby reducing the junction leakage current characteristics between the semiconductor substrate 51 and the source / drain regions 52. Can be.

2C is a cross-sectional view for explaining a step of forming a self-aligned contact hole and a conductive film 65. In detail, an interlayer insulating film, for example, a BPSG film, is formed on the entire surface of the resultant product in which the spacer 61 is formed, and then patterned to form a self-aligned contact hole exposing the source / drain regions 52 between the gate patterns 59. At the same time, the interlayer insulating film pattern 63 is formed. At this time, as shown, a portion of the gate protective layer pattern 57 made of silicon nitride and the spacer 61 are exposed and etched, thereby deforming the gate pattern including the modified spacer 61a and the modified gate protective layer pattern 57a. 59a is formed. Since the spacer 61 and the gate passivation pattern 57 are etched as described in FIG. 2B, the spacer 61 and the gate passivation pattern 57 are easily etched during the etching process for patterning the interlayer insulating layer. Because it becomes. Accordingly, since the thicknesses of the modified spacer 61a and the modified gate passivation pattern 57a covering the gate electrode 55 become thin, the gate electrode 55 may be excessively etched when the self-aligned contact hole is formed. May be exposed. Next, a conductive film is formed on the entire surface of the resultant self-aligned contact hole and patterned to form a conductive film pattern 65 covering the self-aligned contact hole and contacting the source / drain region 52.

As described above, according to the conventional self-aligned contact hole forming method, the insulating property between the gate electrode and the conductive film pattern is lowered, and etching damage is applied to the source / drain regions exposed by the self-aligned contact hole, resulting in junction leakage. Deteriorates the current characteristic.

An object of the present invention is to provide a method of forming a self-aligned contact hole capable of improving the insulation characteristics of the gate electrode as well as the junction leakage current characteristics of the source / drain regions.

1 is a process flowchart of forming a conventional self-aligned contact hole.

2A to 2C are cross-sectional views illustrating a method of forming a conventional self-aligned contact hole.

3 is a process flowchart of forming a self-aligned contact hole according to the present invention.

4A to 4C are cross-sectional views illustrating a method of forming a self-aligned contact hole according to the present invention.

In order to achieve the above technical problem, a method of forming a self-aligned contact hole according to the present invention includes forming a gate pattern on a predetermined region of a semiconductor substrate, forming a spacer on the sidewall of the gate pattern, and forming the spacer. Performing a first heat treatment process for healing an etch damage applied to the surface of the semiconductor substrate, forming an interlayer insulating film on the first heat-treated resultant, patterning the interlayer insulating film, and forming a semiconductor substrate between the gate patterns; Forming an interlayer insulating film pattern exposing the spacer and a portion of an upper surface of the gate pattern; and performing a second heat treatment process to cure an etch damage applied to a surface of a resultant product on which the interlayer insulating film pattern is formed. Characterized in that.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3 is a process flowchart for forming a self-aligned contact hole according to the present invention.

Referring to FIG. 3, the present invention provides a process 101 of forming a gate pattern on a predetermined region of a semiconductor substrate, a process 103 of forming a spacer on a sidewall of the gate pattern, and a process of forming the spacer. A first step (105) of heat treating the resultant product formed with the spacer to heal etch damage, and forming an interlayer insulating film on the first heat-treated resultant, patterning the semiconductor substrate between the gate pattern, the spacer, and Forming a self-aligned contact hole exposing a portion of the upper surface of the gate pattern (107), and healing the etching damage applied to the spacer, the semiconductor substrate, and the upper surface of the gate pattern exposed by the self-aligned contact hole In order to cover the self-aligned contact hole by forming a conductive film on the entire surface of the second heat-treated product 109 and patterning the conductive film to form a conductive film. Challenge includes a process 111 for forming a pattern film.

4A to 4C are cross-sectional views illustrating in detail a method of forming a self-aligned contact hole according to the present invention.

4A is a cross-sectional view for describing a step of forming the gate pattern 159. First, a gate insulating film, a gate electrode conductive film, and a gate protective film are sequentially formed on the semiconductor substrate 151. Here, the gate insulating film, the conductive film for the gate electrode, and the gate protective film are preferably formed of a thermal oxide film, a doped polysilicon film, and a silicon nitride film, respectively. Next, the gate protective film, the gate electrode conductive film, and the gate insulating film are successively patterned to sequentially stack the gate insulating film pattern 153, the gate electrode 155, and the gate on a predetermined region of the semiconductor substrate 151. The protective film pattern 157 is formed. The gate insulating layer pattern 153, the gate electrode 155, and the gate protective layer pattern 157 stacked in this order constitute a gate pattern 159. Subsequently, an impurity is implanted into the surface of the semiconductor substrate between the gate patterns to form a source / drain region 152.

4B is a cross-sectional view for describing a step of forming the spacer 161. In detail, the spacer 161 is formed on the sidewall of the gate pattern 159 by anisotropic etching by forming a silicon nitride film on the entire surface of the resultant source / drain region 152. In this case, since a portion of the gate protection layer pattern 157 and the surface of the spacer 161 are etched, the bonding state of atoms is incomplete, thereby forming a porous film. In addition, etching damage is also applied to the surface of the semiconductor substrate between the spacers 161 to generate crystal defects near the junction of the source / drain regions 152. This crystal defect causes a decrease in the junction leakage current characteristic of the source / drain regions 152. The etch damaged spacer 161 and the gate protective layer pattern may lower the etch selectivity with respect to another material layer, for example, a silicon oxide layer. Therefore, in order to improve the etching selectivity, the resultant formed with the spacer 161 is first heat treated. Here, it is preferable that the first heat treatment step is performed by ammonia plasma treatment or sequentially performed by ammonia plasma treatment and rapid heat treatment. When the ammonia plasma treatment is performed, nitrogen can be sufficiently supplied to the surface of the spacer 161 and the gate protective layer pattern 157 formed of a silicon nitride film, thereby achieving complete atomic bonding. Subsequently, when rapid heat treatment is performed at a high temperature of 1000 ° C. to 1200 ° C., the film quality of the spacer 161 and the gate passivation layer pattern 157 may be more densely formed, thereby further increasing the etching selectivity of the oxide layer.

4C is a cross-sectional view for describing a step of forming the self-aligned contact hole and the conductive film pattern 165. In detail, an interlayer insulating layer, for example, a BPSG layer, is formed on the entire surface of the first heat-treated resultant, and patterned to form a source / drain region 152, a spacer 161, and a gate passivation layer pattern between the gate patterns 159. An interlayer insulating film pattern 163 having a self-aligned contact hole for exposing a portion of 157 is formed. In this case, the spacer 161 and the gate passivation pattern 157 maintain their initial shape during an etching process for patterning the interlayer insulating layer to form the self-aligned contact hole. This is because the film quality damaged by the first heat treatment process is cured and the etching selectivity is improved. However, the etching process for forming the self-aligned contact hole causes etch damage again to the exposed spacer 161, the gate passivation pattern 157, and the source / drain region 152. The second heat treatment step may be performed. It is preferable to perform the said 2nd heat processing process by the same method as a 1st heat processing process. Subsequently, a conductive film is formed on the entire surface of the resultant product subjected to the first heat treatment process, and patterned to form a conductive film pattern 165 in contact with the source / drain region 152 while covering the self-aligned contact hole. do.

The present invention is not limited to the above embodiments, and modifications and improvements are possible at the level of those skilled in the art.

As described above, according to the exemplary embodiment of the present invention, the spacer and the gate protective layer pattern covering the gate electrode may be prevented from being etched when the self-aligned contact hole is formed through the first heat treatment and the second heat treatment. Accordingly, the insulating property between the conductive layer pattern covering the self-aligned contact hole and the gate electrode can be improved, and the junction leakage current property of the source / drain regions can be improved.

Claims (7)

Forming a gate pattern on a predetermined region of the semiconductor substrate; Forming a spacer on sidewalls of the gate pattern; Performing a first heat treatment process for curing an etch damage applied to a surface of the resultant product on which the spacers are formed; Forming an interlayer insulating film on the first heat-treated resultant; Patterning the interlayer dielectric layer to form an interlayer dielectric layer pattern exposing the semiconductor substrate, the spacer, and a portion of an upper surface of the gate pattern between the gate patterns; And performing a second heat treatment process for curing an etch damage applied to a surface of the resultant layer on which the interlayer insulating film pattern is formed. The method of claim 1, wherein the forming of the gate pattern comprises: sequentially forming a gate insulating film, a conductive film for a gate electrode, and a gate protection film on a semiconductor substrate; And successively patterning the gate protective film, the gate electrode conductive film, and the gate insulating film to form a gate pattern including a gate insulating film pattern, a gate electrode, and a gate protective film pattern on a predetermined region of the semiconductor substrate. A method of forming a self-aligned contact hole, characterized in that. The method of claim 2, wherein the gate protective layer is formed of a silicon nitride layer. The method of claim 1, wherein the spacer is formed of a silicon nitride film. The method of claim 1, wherein the interlayer insulating film is formed of a BPSG film. The method of claim 1, wherein the first and second heat treatment processes use an ammonia plasma treatment process. The method of claim 6, further comprising a rapid thermal treatment at a high temperature of 1000 ℃ to 1200 ℃ after the ammonia plasma treatment process.