KR100559036B1 - Method for forming metalline in semiconductor device - Google Patents
Method for forming metalline in semiconductor device Download PDFInfo
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- KR100559036B1 KR100559036B1 KR1019990049480A KR19990049480A KR100559036B1 KR 100559036 B1 KR100559036 B1 KR 100559036B1 KR 1019990049480 A KR1019990049480 A KR 1019990049480A KR 19990049480 A KR19990049480 A KR 19990049480A KR 100559036 B1 KR100559036 B1 KR 100559036B1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 28
- 238000000034 method Methods 0.000 title claims abstract description 25
- 239000010410 layer Substances 0.000 claims abstract description 53
- 239000007772 electrode material Substances 0.000 claims abstract description 36
- 239000002184 metal Substances 0.000 claims abstract description 23
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 239000011229 interlayer Substances 0.000 claims abstract description 11
- 239000000463 material Substances 0.000 claims abstract description 9
- 238000005530 etching Methods 0.000 claims abstract description 7
- 239000012535 impurity Substances 0.000 claims abstract description 5
- 150000002500 ions Chemical class 0.000 claims abstract description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 10
- 229920005591 polysilicon Polymers 0.000 claims description 10
- 230000015572 biosynthetic process Effects 0.000 claims description 5
- 238000005137 deposition process Methods 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 3
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 2
- 230000000694 effects Effects 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76805—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
본 발명은 게이트 라인과 상층 금속 배선간의 접촉 저항을 줄일 수 있도록한 반도체 소자의 금속 배선 형성 방법에 관한 것으로, 반도체 기판상에 게이트 산화막,제 1 전극 물질층,제 2 전극 물질층을 차례로 적층 형성하는 단계;상기 제 1,2 전극 물질층을 선택적으로 식각하여 제 1,2 전극 물질 패턴층이 적층되는 게이트 전극을 형성하는 단계;상기 게이트 전극의 양측 반도체 기판의 표면내에 불순물 이온을 주입하여 소오스/드레인 영역을 형성하는 단계;전면에 층간 절연막을 형성하고 층간 절연막 및 상기 제 2 전극 물질 패턴층을 일정 깊이 식각하여 콘택홀을 형성하는 단계;상기 콘택홀을 포함하는 전면에 금속 배선 물질층을 형성하는 단계를 포함하여 이루어진다.The present invention relates to a method for forming a metal wiring of a semiconductor device to reduce the contact resistance between the gate line and the upper metal wiring, and sequentially forming a gate oxide film, a first electrode material layer, and a second electrode material layer on the semiconductor substrate. Selectively etching the first and second electrode material layers to form a gate electrode on which the first and second electrode material pattern layers are stacked; implanting impurity ions into surfaces of semiconductor substrates on both sides of the gate electrode Forming a contact hole by forming an interlayer insulating film on the front surface and etching the interlayer insulating film and the second electrode material pattern layer to a predetermined depth; forming a metal wiring material layer on the entire surface including the contact hole; It comprises the step of forming.
금속배선,콘택저항Metal wiring, contact resistance
Description
도 1은 종래 기술의 반도체 소자의 배선간의 콘택 구조를 나타낸 단면도1 is a cross-sectional view showing a contact structure between wirings of a semiconductor device of the prior art;
도 2a내지 도 2f는 본 발명에 따른 반도체 소자의 배선 콘택을 위한 공정 단면도2A to 2F are cross-sectional views of a process for wiring contacts of a semiconductor device according to the present invention.
도면의 주요 부분에 대한 부호의 설명Explanation of symbols for the main parts of the drawings
21. 반도체 기판 22. 게이트 산화막21.
23. 제 1 전극 물질층 24. 제 2 전극 물질층23. First electrode material layer 24. Second electrode material layer
25. 게이트 전극 26a.26b. 소오스/드레인25. Gate electrode 26a.26b. Source / Drain
27. 층간 절연막 28. 콘택홀27. Interlayer
29. 상부 배선 물질층29. Top Wiring Material Layer
본 발명은 반도체 소자에 관한 것으로, 특히 게이트 라인과 상층 금속 배선간의 접촉 저항을 줄일 수 있도록한 반도체 소자의 금속 배선 형성 방법에 관한 것이다.BACKGROUND OF THE
이하, 첨부된 도면을 참고하여 종래 기술의 반도체 소자의 금속 배선 및 콘택 공정에 관하여 설명하면 다음과 같다.Hereinafter, a metal wiring and a contact process of a semiconductor device of the prior art will be described with reference to the accompanying drawings.
도 1은 종래 기술의 반도체 소자의 배선간의 콘택 구조를 나타낸 단면도이다.1 is a cross-sectional view showing a contact structure between wirings of a semiconductor device of the prior art.
종래 기술에서 게이트 전극과 상부 배선간의 콘택 공정은 먼저, 반도체 기판(1)상에 게이트 산화막(2)을 형성하고 게이트 산화막(2)상에 게이트 형성용 물질층, 예를들면 폴리 실리콘을 증착하고 선택적으로 패터닝하여 게이트 전극(3)을 형성한다.In the prior art, the contact process between the gate electrode and the upper wiring firstly forms a
그리고 상기 게이트 전극(3)을 마스크로 반도체 기판(1)의 표면내에 불순물 이온을 주입하여 소오스/드레인(4a)(4b)을 형성한다.The impurity ions are implanted into the surface of the
이어, 전면에 층간 절연층으로 산화막(5)을 증착하고 선택적으로 패터닝하여 콘택홀을 형성한다.Subsequently, an oxide film 5 is deposited on the entire surface with an interlayer insulating layer and selectively patterned to form a contact hole.
여기서, 콘택홀 형성은 상기 게이트 전극(3)이 노출되도록 형성한다.In this case, the contact hole is formed to expose the
그리고 상기 콘택홀을 포함하는 전면에 스퍼터링 공정으로 금속층(6)을 증착 형성하여 상부 배선을 형성한다.In addition, the upper layer is formed by depositing the
이와 같은 종래 기술의 금속 배선 및 콘택 공정에서는 상부 금속 물질과 게이트 전극 물질간의 저항 및 콘택 면적에 따른 저항등이 소자의 특성에 영향을 준다.In the metal wiring and contact process of the prior art, the resistance between the upper metal material and the gate electrode material and the resistance according to the contact area affect the device characteristics.
이와 같은 종래 기술의 반도체 소자의 금속 배선 및 콘택 공정에 있어서는 다음과 같은 문제가 있다.In such a metal wiring and contact process of the semiconductor element of the prior art, there are the following problems.
첫째, 게이트 전극을 구성하는 폴리 실리콘과 상부 배선을 구성하는 금속간의 콘택 저항이 커 소자의 동작 신뢰성에 영향을 준다.First, the contact resistance between the polysilicon constituting the gate electrode and the metal constituting the upper wiring is large, which affects the operation reliability of the device.
둘째, 콘택홀 형성시에 단층으로 구성된 게이트 전극의 신호 전달 특성을 보호하기 위하여 식각 깊이를 크게 할 수 없으므로 콘택 저항이 크다.Second, in order to protect the signal transmission characteristics of the single-layered gate electrode when forming the contact hole, the etch depth cannot be increased so that the contact resistance is large.
본 발명은 이와 같은 종래 기술의 반도체 소자의 금속 배선 형성 및 콘택 공정의 문제를 해결하기 위한 것으로, 게이트 라인과 상층 금속 배선간의 접촉 저항을 줄일 수 있도록한 반도체 소자의 금속 배선 형성 방법을 제공하는데 그 목적이 있다.The present invention is to solve the problems of the metal wiring formation and contact process of the semiconductor device of the prior art, to provide a method for forming a metal wiring of the semiconductor device to reduce the contact resistance between the gate line and the upper metal wiring. There is a purpose.
이와 같은 목적을 달성하기 위한 본 발명에 따른 반도체 소자의 금속 배선 형성 방법은 반도체 기판상에 게이트 산화막,제 1 전극 물질층,제 2 전극 물질층을 차례로 적층 형성하는 단계;상기 제 1,2 전극 물질층을 선택적으로 식각하여 제 1,2 전극 물질 패턴층이 적층되는 게이트 전극을 형성하는 단계;상기 게이트 전극의 양측 반도체 기판의 표면내에 불순물 이온을 주입하여 소오스/드레인 영역을 형성하는 단계;전면에 층간 절연막을 형성하고 층간 절연막 및 상기 제 2 전극 물질 패턴층을 일정 깊이 식각하여 콘택홀을 형성하는 단계;상기 콘택홀을 포함하는 전면에 금속 배선 물질층을 형성하는 단계를 포함하여 이루어지는 것을 특징으로 한다.According to an aspect of the present invention, there is provided a method of forming a metal wiring of a semiconductor device, the method comprising: sequentially forming a gate oxide film, a first electrode material layer, and a second electrode material layer on a semiconductor substrate; Selectively etching the material layer to form a gate electrode on which the first and second electrode material pattern layers are stacked; implanting impurity ions into surfaces of semiconductor substrates on both sides of the gate electrode to form a source / drain region; Forming a contact hole by forming an interlayer insulating film on the substrate, and etching the interlayer insulating film and the second electrode material pattern layer to a predetermined depth; forming a metal wiring material layer on the entire surface including the contact hole; It is done.
이하, 첨부된 도면을 참고하여 본 발명에 따른 반도체 소자의 금속 배선 형 성 및 콘택 공정에 관하여 상세히 설명하면 다음과 같다.Hereinafter, metal wiring formation and a contact process of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.
도 2a내지 도 2f는 본 발명에 따른 반도체 소자의 배선 콘택을 위한 공정 단면도이다.2A to 2F are cross-sectional views of a process for wiring contacts of a semiconductor device according to the present invention.
본 발명은 게이트 전극을 다층으로 구성하고 식각 깊이를 충분히 갖도록하여 상부 배선과의 접촉 저항을 줄일 수 있도록한 것이다.The present invention is to reduce the contact resistance with the upper wiring by configuring the gate electrode in a multi-layer and having a sufficient etching depth.
먼저, 도 2a에서와 같이, 반도체 기판(21)상에 게이트 산화막(22),제 1 전극 물질층(23),제 2 전극 물질층(24)을 차례로 형성한다.First, as shown in FIG. 2A, a
여기서, 상기 제 1 전극 물질층(23)은 550℃ 이하의 저온 증착 공정으로 형성되는 저온 폴리 실리콘층이고, 제 2 전극 물질층(24)은 550℃ 이상의 고온 증착 공정으로 형성되는 고온 폴리 실리콘층이다.Here, the first electrode material layer 23 is a low temperature polysilicon layer formed by a low temperature deposition process of 550 ° C. or lower, and the second electrode material layer 24 is a high temperature polysilicon layer formed by a high temperature deposition process of 550 ° C. or higher. to be.
이때, 제 2 전극 물질층(24)을 고온 폴리 실리콘으로 형성하는 공정시에 비결정 폴리 실리콘이 동시에 증착된다.At this time, amorphous polysilicon is simultaneously deposited in the process of forming the second electrode material layer 24 from high temperature polysilicon.
그리고 제 2 전극 물질층(24)은 제 1,2 전극 물질층(23)(24)의 전체 두께의 50%가 넘는 두께로 형성한다.The second electrode material layer 24 is formed to a thickness of more than 50% of the total thickness of the first and second electrode material layers 23 and 24.
이어, 도 2b에서와 같이, 상기 제 1,2 전극 물질층(23)(24)을 선택적으로 식각하여 제 1 전극 물질 패턴층(23a),제 2 전극 물질 패턴층(24a)이 적층되는 게이트 전극(25)을 형성한다.Subsequently, as shown in FIG. 2B, the first and second electrode material layers 23 and 24 are selectively etched to stack the first electrode
그리고 도 2c에서와 같이, 상기 게이트 전극(25)을 마스크로하여 반도체 기판(21)의 표면내에 불순물 이온을 주입하여 소오스/드레인 영역(26a)(26b)을 형성한다.As shown in FIG. 2C, source /
이어, 도 2d에서와 같이, 상기 셀 트랜지스터가 형성된 전면에 층간 절연막(27)을 형성한다.Next, as shown in FIG. 2D, an
상기 층간 절연막(27)은 산화막을 사용한다.The
그리고 도 2e에서와 같이, 상기 층간 절연막(27)을 선택적으로 식각하여 콘택홀(28)을 형성한다.As shown in FIG. 2E, the
여기서, 상기 콘택홀(28)은 제 2 전극 물질 패턴층(24a)의 두께의 20% ~ 80%의 두께가 제거되도록 형성한다.In this case, the
이어, 도 2f에서와 같이, 상기 콘택홀(28)을 포함하는 전면에 스퍼터링 공정으로 상부 배선 물질층(29)을 형성한다.Subsequently, as shown in FIG. 2F, the upper
이와 같은 본 발명에 따른 반도체 소자의 금속 배선 형성 및 콘택 공정은 게이트 전극을 다중층으로 형성하여 게이트 주배선으로 사용되는 하부의 전극 물질층은 콘택홀 형성시에 식각되지 않도록하고 상부의 전극 물질층을 식각하여 콘택 면적을 충분히 확보한다.The metal wiring formation and contact process of the semiconductor device according to the present invention is to form a gate electrode in multiple layers so that the lower electrode material layer used as the gate main wiring is not etched when forming the contact hole and the upper electrode material layer Etch to secure a sufficient contact area.
게이트 전극으로의 특성에 적합한 물질로 하부층을 구성하고 콘택저항이 작은 물질로 상부층을 구성하여 콘택 저항을 줄일 수 있다.The contact resistance may be reduced by forming a lower layer with a material suitable for the gate electrode characteristics and an upper layer with a material having a small contact resistance.
이와 같은 본 발명에 따른 반도체 소자의 금속 배선 형성 방법은 다음과 같은 효과가 있다.Such a metal wiring formation method of a semiconductor device according to the present invention has the following effects.
게이트 전극과 상부의 금속 배선과의 접촉 면적을 충분히 확보할 수 있고, 상부 게이트층을 형성하기 위한 저온 폴리 실리콘 증착시에 비결정 실리콘이 증착 되어 금속과의 콘택 저항을 줄일 수 있다.The contact area between the gate electrode and the upper metal wiring can be sufficiently secured, and amorphous silicon is deposited during low temperature polysilicon deposition for forming the upper gate layer, thereby reducing contact resistance with the metal.
이는 소자의 동작 특성 및 신뢰성을 향상시키는 효과가 있다.This has the effect of improving the operating characteristics and reliability of the device.
Claims (5)
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| Application Number | Priority Date | Filing Date | Title |
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| KR1019990049480A KR100559036B1 (en) | 1999-11-09 | 1999-11-09 | Method for forming metalline in semiconductor device |
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| Application Number | Priority Date | Filing Date | Title |
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| KR1019990049480A KR100559036B1 (en) | 1999-11-09 | 1999-11-09 | Method for forming metalline in semiconductor device |
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| Publication Number | Publication Date |
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| KR20010045946A KR20010045946A (en) | 2001-06-05 |
| KR100559036B1 true KR100559036B1 (en) | 2006-03-10 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019990049480A KR100559036B1 (en) | 1999-11-09 | 1999-11-09 | Method for forming metalline in semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR100559036B1 (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR920020763A (en) * | 1991-04-19 | 1992-11-21 | 김광호 | Semiconductor device and manufacturing method |
| JPH05226333A (en) * | 1992-02-12 | 1993-09-03 | Sharp Corp | Manufacture of semiconductor device |
| KR19990057882A (en) * | 1997-12-30 | 1999-07-15 | 김영환 | Semiconductor device manufacturing method |
| KR19990080170A (en) * | 1998-04-14 | 1999-11-05 | 김규현 | Polysilicon Electrode Formation Method |
-
1999
- 1999-11-09 KR KR1019990049480A patent/KR100559036B1/en not_active IP Right Cessation
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR920020763A (en) * | 1991-04-19 | 1992-11-21 | 김광호 | Semiconductor device and manufacturing method |
| JPH05226333A (en) * | 1992-02-12 | 1993-09-03 | Sharp Corp | Manufacture of semiconductor device |
| KR19990057882A (en) * | 1997-12-30 | 1999-07-15 | 김영환 | Semiconductor device manufacturing method |
| KR19990080170A (en) * | 1998-04-14 | 1999-11-05 | 김규현 | Polysilicon Electrode Formation Method |
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| Publication number | Publication date |
|---|---|
| KR20010045946A (en) | 2001-06-05 |
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