KR910010223B1 - Multi-layer wiring method of semiconductor elements - Google Patents

Abstract

The method comprises forming a lower metallic film (12) on a substrate (1) having elements to form a Si film (11) thereon; patterning metallic wirings (11') thereon; forming an insulating film (12) on the Si film (11); performing a photoresist process and removing the insulating film; forming a via-contact hole for connecting between the lower metallic film (10) and upper metallic film; removing the photoresist film and the remaining Si film (11) from the via-contact hole opening; forming wirings and insulating film to connect to the lower metallic wirings; and forming an upper metallic wirings thereon. The method obtains a stable ohmic contact between the metallic wirings.

Description

Multi-layer metallization process method of semiconductor device

1 is a cross-sectional view of a metal film constituting a lower layer metal wiring after the basic process for the cell configuration before the multi-layer metal wiring process in the silicon substrate.

2 is a cross-sectional view of a silicon thin film formed on a metal film.

3 is a cross-sectional view of a state in which a photoresist is removed after forming a metal wiring pattern by dry etching a silicon thin film and a metal film by forming a photoresist pattern for metal wiring.

4 is a cross-sectional view of a silicon oxide film planarized by a planarization process after deposition of a silicon oxide film for insulation between metal wiring layers.

5 is a cross-sectional view of a state in which a photoresist is formed and a via contact hole is formed.

FIG. 6 is a cross-sectional view after removing a photoresist and removing the silicon thin film on the surface of the metallization of the opening by dry etching.

FIG. 7 is a cross-sectional view of the formation of the upper metal film, the upper metal wiring etching by the photoresist pattern, and the upper metal wiring after removing the photoresist.

* Explanation of symbols for the main parts of the drawings

1 silicon substrate 2 diffusion layer

3: field oxide film 4: gate oxide film

5: polysilicon gate electrode or polyside gate electrode

6: silicon oxide film 7: polysilicon or polyside lead

8: silicon oxide film

9: silicon oxide film doped with B or P (BPSG or PSG)

10 and 10 ': lower layer metal film and lower layer metal wiring 11: silicon thin film

12: planarized silicon oxide film 13: upper metal wiring

14 photoresist

The present invention relates to a multi-layer metallization process method of a highly integrated semiconductor device, in particular, the etching end point of the insulating layer by dry etching when forming a contact hole in the planarized insulating layer after the planarization process of the insulating film between the lower metal layer and the upper layer metal wiring On the surface of the lower layer metal layer to prevent damage to the lower layer metal line due to the over etching of the etching end point and to suppress the formation of the aluminum oxide layer (Al ₂ O ₃ ) on the surface when the lower layer layer is aluminum. The present invention relates to a multilayer metallization process method for forming a silicon thin film to stabilize contact resistance between metallization lines.

In the development of semiconductor integrated circuits, the main development point of view has been to increase the operation speed, minimize the power consumption, increase the degree of integration due to the high functionality and unit cell area. The adoption of multilayer metallization process enables to increase the operation speed of semiconductor devices and increase the degree of integration. Therefore, the multilayer metallization process is not only applied to the manufacture of general-purpose semiconductor memory devices such as DRAM and SRAM, but also for custom semiconductor devices and logic gate arrays. It is widely used in the field of semiconductor device manufacturing, such as acting on device manufacturing.

In particular, the via contact process for the contact between the lower metal wiring and the upper metal wiring in the multilayer metal wiring process has a close relationship with the yield and reliability of the semiconductor device to which the multilayer metal wiring process is applied. Increasing the defective rate of the device, not only weakening the characteristics of the device but also reduce the reliability of the device. This is due to incomplete removal of the metal oxide film from the surface of the metal contact film in the via contact hole opening and plasma damage due to the exposure of the surface of the metal wire during dry etching of the via contact hole in the semiconductor small glass manufacturing process using the multilayer metal wiring process. The main cause is change or injection of impurities into the metal.

In a conventional multilayer metallization process, for example, in a two-layer metallization process, a silicon oxide film is deposited for insulation between the metallization layers after the formation of the first metal film and the pattern etching, and the silicon oxide film is planarized. Subsequently, a via contact pattern is formed by a photoresist for contact between the primary metal wire and the secondary metal wire, and then a via contact hole is formed in the silicon oxide layer by dry etching or a combination of wet and dry etching. Contact the metal wiring and the secondary metal wiring.

However, if the primary metal wiring is, for example, aluminum wiring, in the photoresist removal process in which an etching pattern is formed after metal etching by a pattern process, photoresist removal by oxygen plasma or wet photoresist removal or the above two methods are performed. The aluminum oxide film produced by the surface oxidation reaction according to the exposure of aluminum by the complex photoresist removal method sequentially proceeds to remove the aluminum oxide film on the aluminum wiring layer due to the high binding energy between molecules and the difficulty of removal. If is incomplete, it exists as an insulating film between the primary aluminum wiring and the secondary aluminum wiring layer, resulting in an increase in contact resistance between the aluminum wiring layers or a partially unstable resistance.

In addition, due to the difference in dry etching time due to the difference in thickness of the silicon oxide film of the via contact hole forming part, plasma damage of the surface of the metal wiring in the via contact hole of the thin silicon oxide film part is caused by the formation of the via contact hole in the thick silicon oxide film part. As it becomes relatively deeper than plasma damage on the surface of the metal wiring, the contact resistance between the metal wiring layers in each part of the semiconductor device cell is uneven, resulting in a bad effect on the reliability of the semiconductor device.

Accordingly, the present invention provides a multi-layered metallization process method that obtains stable contact resistance between metallizations by inhibiting the growth of the metal oxide film on the surface of the metallized lines during the multilayered metallization process and preventing damage to the metallized film by dry etching. The purpose is.

That is, a multi-layer metal wiring process method of forming a thin film, for example, a thin silicon film, which can easily bring a low etch ratio with the silicon oxide film at the same time as the lower metal layer is formed.

According to the present invention, first, by inhibiting the growth of the metal oxide film due to the exposure of the atmosphere of the lower metal film formed from the vacuum reactor, and by etching the via contact hole for the contact between the metal wiring and the thin film formed simultaneously with the lower metal film, by controlling the etching selectivity Plasma damage due to dry etching does not directly affect the metal wiring by leaving it on the metal wiring surface of the via contact hole opening. Also, in the photoresist removal process, the thin film is maintained on the lower metal wiring surface until the upper metal wiring layer is formed. By preventing the direct exposure of the metal film by the use of oxygen plasma or wet etching method, it is possible to exclude the possibility of changing the characteristics of the metal wiring film.

Hereinafter, with reference to the accompanying drawings, the present invention will be described in detail.

FIG. 1 shows the formation of the field oxide film 3 for isolation between devices on the silicon substrate 1, the growth of the gate oxide film 4 by oxidation, and the formation of the polysilicon gate electrode 5, followed by ion implantation. The diffusion layer 2 is formed. After depositing a silicon oxide film 6 to protect the polysilicon gate electrode 4 and to insulate the upper polysilicon or polyside lead to be formed later, a contact hole is formed, and the polysilicon or polyside 7 is formed thereon. E) and dry etching to form a lead, then a silicon oxide film 8 is deposited on the polysilicon or polyside lead 7 and a silicon oxide film 9 containing B or P is also deposited and then flow To relieve surface curvature. Next, a cross-sectional view of a metal layer 10 deposited after contact hole etching for connecting the metal layer to the polysilicon gate electrode 5, the polysilicon or polyside lead 7, and the diffusion layer 2.

FIG. 2 is a cross-sectional view of the metal film 10 formed in the metal film forming reactor in FIG. 1 and the silicon thin film 11 formed in the same reactor at the same time, and the metal film 10 of FIG. The silicon thin film 11 of FIG. 2 shows a state formed sequentially in the same reactor. As a method of forming an aluminum (Al) film for metal wiring, a method of forming an aluminum (Al) film, which is a metal wiring layer, in addition to accelerated evaporation, chemical vapor deposition (CVD) and argon ions (Ar ⁺ ) of aluminum metal atoms A method of forming an aluminum target by sputtering and the like is used, and the general method may include the latter sputtering method. The sputter chamber (Chamber) for forming an aluminum film has a considerable degree of vacuum (5 × 10 ^-7 torr), and several targets such as an aluminum target and a silicon (Si) target can be simultaneously mounted in the chamber. In the formation of the silicon thin film of the first in the sputter chamber, aluminum is first formed by sputtering, followed by silicon target sputtering by argon to form a silicon thin film.

3 is a cross-sectional view of a state in which a pattern of a lower layer metal line 10 'is formed by dry etching and a photoresist is removed by dry or wet after forming a photoresist pattern for the lower layer metal line 10' in FIG. to be.

4 is a cross-sectional view of a silicon oxide film 12 in which a planarization process is performed by depositing a silicon oxide film 12 to insulate the metal wiring layers.

FIG. 5 is a cross-sectional view of a via contact hole forming process for connecting the lower metal wiring 10 'and the upper metal wiring, in which a via contact hole is formed by a via contact pattern after the photoresist 14 is formed. The silicon thin film 11 formed in FIG. 2 on the surface of the metal wiring 10 ′ at the via contact hole opening by the etching rate of the silicon oxide film 12 is preserved as it is.

FIG. 6 is a process of removing the silicon thin film 11 remaining on the surface of the metal wiring 10 'of the via contact hole opening after the photoresist 14 in FIG. 5 is removed by oxygen plasma or wet process. , A cross-sectional view of the silicon thin film 11 on the surface of the metal wiring 10 ′ completely removed without being damaged or contaminated by etching by-products during etching by dry etching with an etching gas such as NF ₃ or SF ₆ . .

FIG. 7 is a cross-sectional view of the upper metal film 13 formed immediately after the process of FIG. 6 and the upper metal wiring 13 formed by the etching process.

According to the present invention, the formation of the lower layer metal layer and the formation of the silicon thin film on the surface of the lower layer metal layer are sequentially inhibited to form the metal oxide layer due to the exposure of the lower layer metal layer. Since the contact resistance between the metallization layers can be obtained by eliminating the plasma damage on the lower metallization surface, there is a great effect of increasing the reliability of the semiconductor device adopting the multilayer metallization process.

Claims (1)

MOSFETs, device isolation oxides and capacitors are formed on the silicon substrate, and an insulating film is formed on top of the silicon substrate. Then, a lower metal film and an insulating film are sequentially formed on the silicon device, and a portion of the insulating film is etched to form a via contact hole. In the multi-layer metal wiring process of forming an upper metal film to form an upper metal film and then connecting the lower metal film, damage to the lower metal film generated when etching a portion of the insulating film to form a via contact, and an oxide film is formed on the lower metal film. In order to prevent the unstable shape of the contact resistance according to the generation, the silicon thin film is formed on the surface of the lower metal film in the same reactor when forming the lower metal film, and then metal wiring is formed by a pattern process and an insulating film is formed on the silicon thin film. Forming a photoresist on a portion of the insulating film on the metal wiring; Removing the insulating layer of the portion where the photoresist has been removed to form a via contact hole, and then removing all of the photoresist and selectively removing the silicon thin film of the exposed portion of the via contact hole; A multi-layered metal of a semiconductor device comprising a step of forming an upper metal layer on the exposed lower metal wiring and an insulating film immediately after the thin film is removed and connecting to the lower metal wiring, and then forming an upper metal wiring by a pattern process. Wiring process method.

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