KR920008842B1 - Application method for metal layer of semiconductor - Google Patents

Application method for metal layer of semiconductor Download PDF

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KR920008842B1
KR920008842B1 KR1019880008602A KR880008602A KR920008842B1 KR 920008842 B1 KR920008842 B1 KR 920008842B1 KR 1019880008602 A KR1019880008602 A KR 1019880008602A KR 880008602 A KR880008602 A KR 880008602A KR 920008842 B1 KR920008842 B1 KR 920008842B1
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film
contact hole
forming
metal
region
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KR1019880008602A
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KR900002448A (en
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이철진
류지효
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삼성전자 주식회사
강진구
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Priority to JP1171322A priority patent/JPH0266940A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268

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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
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Abstract

The method for forming a metallic wiring film on a contact hole without increasing the contact resistance and leakage current comprises the steps of forming an impurity implantation region (2) into a substrate (1) to form an insulation film (3) on the substrate, removing a given region of the film (3) to form a contact hole (20) on the region (2), forming a titanium film (14) in the contact hole and on the film (3), forming a titanium silicide film (15) into the contact hole by using a self-aligning process, selectively applying a tungsten film (16) on the film (15) by chemical deposition method and forming a metallic film (17) on the films (3,16). The method improves the step coverage of metallic wirings.

Description

반도체장치의 금속배선막 도포방법Metal wiring film coating method of semiconductor device

제1도는 종래의 일반적인 방법에 의해 콘택트홀에 금속배선막을 도포시킨 방법.1 is a method in which a metal wiring film is applied to a contact hole by a conventional method.

제2도는 종래의 콘택트홀에 선택적 도포방법으로 금속배선막을 도포시킨 방법.2 is a method in which a metal wiring film is applied to a conventional contact hole by a selective coating method.

제3도는 이 발명에 의한 콘택트홀에서 금속배선막 형성상태를 나타낸 단면도.3 is a cross-sectional view showing a metal wiring film forming state in a contact hole according to the present invention.

제4a도에서 4h도는 이 발명에 의한 콘택트홀에서의 선택적 도포방법 및 금속배선막 형성방법을 공정단계별로 나타낸 상태도이다.4A to 4H are state diagrams showing the selective coating method and the metal wiring film forming method in the contact hole according to the present invention for each process step.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings

1 : 실리콘기판 2 : 불순물주입영역1: silicon substrate 2: impurity injection region

3 : 절연막 4 : 텅스텐막3: insulating film 4: tungsten film

5 : 금속막 6 : 실리콘석출물5: metal film 6: silicon precipitate

7 : 스파이크 8 : 잠식현상영역7: spike 8: erosion area

9 : 턴널링영역 14 : 티타늄막9: tunneling area 14: titanium film

15 : 티타늄 실리사이드막 16 : 텅스텐막15 titanium silicide film 16 tungsten film

17 : 금속막 20 : 콘택트홀17 metal film 20 contact hole

이 발명은 반도체장치의 제조공정중에서 단차가 심한 콘택트홀(Contact Hole)에 금속배선막을 형성시킬 때 콘택트저항을 크게 낮추고 누설전류를 방지할 수 있는 금속배선막의 제조방밥에 관한 것이다. 반도체소자가 집적화되어감에 따라 콘택트홀의 크기가 감소되고 단차가 깊어지게 되어 미세가공이 요구되는 것이었다. 그러나 종래의 방법으로 금속배선막을 형성시킬 경우에는, 제1도에 도시한 바와 같이 콘택트홀 내부에 실리콘 석출물(6)이 생기고, 또한 금속막(5)에 의한 스파이크(7)가 발생되기 때문에 콘택트 저항이 증가될 뿐만이 아니라, 누설전류가 증가되는 원인이 되는 것이었다.The present invention relates to a manufacturing method of a metal wiring film that can greatly reduce contact resistance and prevent leakage current when forming a metal wiring film in a contact hole having a high level of difference in the manufacturing process of a semiconductor device. As semiconductor devices are integrated, the size of contact holes is reduced and the steps are deepened, so that fine processing is required. However, in the case of forming the metal wiring film by the conventional method, as shown in FIG. 1, the silicon precipitate 6 is formed inside the contact hole, and since the spike 7 is generated by the metal film 5, the contact is made. Not only did the resistance increase, but it also caused the leakage current to increase.

한편, 콘택트홀에서 실리콘 석출방지 및 스파이크 방지를 위해 메탈제(Barrier Metal)을 사용하는 방법과, 콘택트홀에서 스텝커버리지를 증가시키기 위해 콘택트홀을 채우는 공정이 시도 되어 왔다.On the other hand, a method of using a metal (barrier metal) to prevent silicon precipitation and spike prevention in the contact hole, and the process of filling the contact hole to increase the step coverage in the contact hole has been attempted.

그러나, 전자의 경우 실리콘 석출방지 및 스파이크 방지효과를 얻을 수가 있으나, 금속배선막의 스템커버리지를 개선시킬 수가 없었고, 후자의 경우 다결정 실리콘 또는 텅스텐막을 이용하여 콘택트홀을 채우는 방법은 금속배선막의 스텝커버리지는 개선시킬 수가 있으나 콘택트 저항증가 및 콘택트 누설전류의 증가로 인하여 실제 반도체 장치에 적용시 문제점이 되고 있다.However, in the former case, the silicon deposition prevention and spike prevention effect can be obtained, but the stem coverage of the metal interconnection film cannot be improved. In the latter case, the step coverage of the metal interconnection film is filled by using a polycrystalline silicon or tungsten film. However, due to the increase in contact resistance and the increase of contact leakage current, there is a problem when applied to actual semiconductor devices.

즉, 제2도에 도시된 바와 같이 콘택트홀에 선택적 도포방식에 의해 텅스텐막(4)를 도포시키는 경우, 콘택트 경계면에서 실리콘과 텡스텐의 상호작용에 의하여 잠식현상영역(8)이 나타나고, 또한 콘택트홀 아랫부분의 불순물 주입영역(2)으로 텡스텐 원자의 턴널링영역(9)이 나타나게 되어 누설전류가 급격히 증가하게 된다.That is, when the tungsten film 4 is applied to the contact hole by the selective coating method as shown in FIG. 2, the erosion area 8 appears due to the interaction of silicon and tungsten at the contact interface. As the impurity implantation region 2 in the lower portion of the contact hole appears, the tunneling region 9 of the tungsten atom appears and the leakage current rapidly increases.

이 발명의 목적은 반도체장치의 제조공정에서 콘택트홀에 금속배선막을 도포시킬 때 콘택트저항 및 콘택트홀에서의 누설전류를 크게 감소시키기 위하여 콘택트홀에 실리사이드막을 형성시킨후 금속막이 도포될 수 있는 반도체 장치의 금속배선막 도포방법을 제공하고자 하는 것이다.SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device in which a metal film may be applied after forming a silicide film in a contact hole to greatly reduce contact resistance and leakage current in the contact hole when the metal wiring film is applied to the contact hole in a semiconductor device manufacturing process. It is to provide a metal wiring film coating method.

이 발명의 특징은, 기판의 소정영역에 불순물 주입영역을 형성한 후 상기 기판의 전면에 절연막을 형성하는 공정과, 상기 절연막의 소정영역을 제거하여 콘택트홀을 상기 불순물 주입영역상에 형성시키는 공정과, 상기 콘택트홀에 금속막을 형성시키는 공정으로 이루어지는 반도체 장치의 금속배선막 도포방법에 있어서, 티타늄막을 상기 콘택트홀내와 상기 절연막상에 형성하는 공정과, 셀프 얼라인(Self-align) 방식으로 상기 콘택트홀내에 티타늄 실리사이드막을 형성시키는 공정과, 화학 증착법에 의하여 텅스텐막을 상기 티타늄 실리사이드막위에 선택적으로 도포시키는 공정과, 상기 텅스텐막 및 상기 절연막의 상부에 금속막을 형성시키는 공정을 포함하는 반도체 장치의 금속배선막 도포방법을 제공하는데 있다.The present invention is characterized by forming an impurity implantation region in a predetermined region of a substrate, and then forming an insulating film over the entire surface of the substrate, and forming a contact hole on the impurity implantation region by removing a predetermined region of the insulation layer. And forming a metal film in the contact hole, comprising: forming a titanium film in the contact hole and on the insulating film; and in a self-align method. Forming a titanium silicide film in a contact hole; selectively applying a tungsten film on the titanium silicide film by chemical vapor deposition; and forming a metal film on top of the tungsten film and the insulating film. A wiring film coating method is provided.

이 발명의 실시예를 첨부도면에 따라서 상세하게 설명하면 다음과 같다.An embodiment of the present invention will be described in detail with reference to the accompanying drawings.

제3도는 이 발명에 의한 콘택트홀에서 금속배선막 형성상태를 나타낸 도면도로서, 실리콘기판(1)위에 불순물 주입영역(2)을 형성시키고 셀프-얼라인 방식에 의하여 단차가 심한 콘택트홀의 저면에 티타늄 실리사이드막(15)을 형성시키고 텅스텐막(16)을 상기 콘택트홀내의 티타늄 실라사이드막(15)상에 선택적으로 도포 실시한 후 그위에 금속막(17)이 도포된 것을 나타내고 있다.3 is a view showing a metal wiring film forming state in a contact hole according to the present invention, in which an impurity implantation region 2 is formed on a silicon substrate 1 and formed on a bottom surface of a contact hole having a high level of difference by a self-aligned method. The titanium silicide film 15 is formed and the tungsten film 16 is selectively applied on the titanium silicide film 15 in the contact hole, and then the metal film 17 is applied thereon.

이를 공정순서별로 설명하면, 먼저 절연막 도포를 위하여 제4a도와 같이 실리콘기판(1)에 이온 주입을 실시하여 불순물 주입영역(2)을 형성시킨 후 절연막(3)을 도포시킨다. 이때 절연막(3)은 화학증착법을 이용한 산화막 또는 불순물이 도핑된 산화막으로서 두께는 1㎛로 한다.To explain this step by step, first, the impurity implantation region 2 is formed by ion implantation into the silicon substrate 1 as shown in FIG. 4A to apply the insulation film, and then the insulation film 3 is coated. At this time, the insulating film 3 is an oxide film using a chemical vapor deposition method or an oxide film doped with impurities and has a thickness of 1 μm.

다음 콘택트홀을 형성하기 위하여 일반적인 사진식각 공정을 사용하여 4b도와 같이 절연막(3)을 RIE(반응성 이온에칭)으로 건식식각한다. 콘택트홀(20)을 형성한 후 100 : 1의 HF용액에 1분간 담아 세정공정을 하고서 스퍼터(Sputter)장비를 사용하여 티타늄막(14)을 콘택트홀(20)내와 절연막(3)상에 600Å+정도 도포하여 4c도와 같이 형성되게 한다.Next, in order to form a contact hole, the insulating film 3 is dry-etched by RIE (reactive ion etching) as shown in FIG. 4B using a general photolithography process. After the contact hole 20 was formed, it was immersed in 100: 1 HF solution for 1 minute, and the titanium film 14 was deposited in the contact hole 20 and on the insulating film 3 using a sputtering device. Apply 600Å + to form 4c.

그리고나서 열처리장치로 900℃ 10초간 아르곤 분위기내에서 열처리를 실시하여 콘택트홀(20)의 아랫부분만 4d도와 같이 티타늄 실리사이드막(15)이 형성되게 한다.Then, heat treatment is performed in an argon atmosphere at 900 ° C. for 10 seconds using a heat treatment apparatus so that only the lower portion of the contact hole 20 is formed as shown in 4d as the titanium silicide film 15.

열처리 실시후 습식식각 방법으로 티타늄막(14)을 식각하고, 티타늄 실리사이드막(15)을 콘택트홀(20)의 아래부분에 남겨두는 선택적 식각공정을 진행하여 4e도와 같이 형성되게 한다. 이때 사용되는 습식식각 용액으로는 NH4OH : H2O2: H2O=1 : 1 : 5인 비율의 용액을 70℃에서 사용한다.After the heat treatment is performed, the titanium film 14 is etched by a wet etching method, and the selective etching process of leaving the titanium silicide film 15 at the lower portion of the contact hole 20 is performed to form the 4e degree. At this time, the wet etching solution used is NH 4 OH: H 2 O 2 : H 2 O = 1: 1: The ratio of the solution is used at 70 ℃.

그리고나서 4f도와 같이 산소플라즈마 분위기에서 콘택트홀(20)내의 티타늄 실리사이드막(15) 및 절연막(3)을 건식세정한다. 건식세정후 화학증착도포법으로 텅스텐막(16)을 4g도와 같이 선택적으로 도포시킨다. 이때 절연막(3)위에는 텅스텐막(16)이 도포되지 않고 콘택트홀의 실리사이드막(15)위에만 텅스텐막(16)이 도포되는 것으로 도포온도는 550℃이고, 사용가스는 WF5/H2=200/6000 SCCM압력은 400m Torr이다.Then, the titanium silicide film 15 and the insulating film 3 in the contact hole 20 are dry-cleaned in an oxygen plasma atmosphere as shown in FIG. 4f. After dry cleaning, the tungsten film 16 is selectively applied by chemical vapor deposition as shown in Fig. 4g. At this time, the tungsten film 16 is not coated on the insulating film 3, and the tungsten film 16 is coated only on the silicide film 15 of the contact hole. The coating temperature is 550 ° C. and the working gas is WF 5 / H 2 = 200. / 6000 SCCM pressure is 400m Torr.

그리고 마지막 공정으로 스퍼터장비를 사용하여 금속막(17)을 텅스텐막(16) 및 절연막(3)의 상부에 도포시키면 (H)도와 같이 완성되는 것을 불순물이 주입된 영역의 콘택트홀에서 실리콘 석출물 및 스파이크현상이 생기는 것을 방지할 수 있다.Finally, when the metal film 17 is applied on the tungsten film 16 and the insulating film 3 by using a sputtering equipment, the silicon precipitate and the silicon oxide in the contact hole in the region where the impurity is implanted are completed as shown in (H). Spikes can be prevented from occurring.

이상에서와 같이 이 발명은 콘택트홀에 선택적으로 텅스텐막을 도포시키는 경우 발생되는 잠식현상 및 턴널링현상들을 티타늄 실리사이드막이 형성된 후 선택적으로 텅스텐막이 도포되도록 함으로써 방지할 수 있는 것으로 다음과 같은 효과를 기대할 수가 있다.As described above, the present invention can prevent the erosion and tunneling phenomena generated when the tungsten film is selectively applied to the contact hole by selectively applying the tungsten film after the titanium silicide film is formed, and the following effects can be expected. have.

(1)반도체장치의 제조공정에서 단차가 심한 콘택트홀을 매립시킴으로써 금속배선막의 스텝커버리지를 향상시킬 수 있다.(1) The step coverage of the metal wiring film can be improved by filling the contact hole with a high level of difference in the manufacturing process of the semiconductor device.

(2)불순물 주입영역에 형성된 콘택트홀에서 금속배선막의 콘택트저항을 낮출 수 있는 동시에 누설전류를 현저하게 감소시킬수가 있다.(2) In the contact hole formed in the impurity injection region, the contact resistance of the metal wiring film can be lowered and the leakage current can be significantly reduced.

(3)다층배선공정으로 금속막을 도포시키는 경우 뛰어난 평탄화 효과를 얻을 수가 있다.(3) When the metal film is applied by the multi-layer wiring process, excellent planarization effect can be obtained.

Claims (1)

기판의 소정영역에 불순물 주입영역을 형성한후 상기 기판의 전면에 절연막을 형성하는 공정과, 상기 절연막의 소정영역을 제거하여 콘택트홀을 상기 불순물 주입영역상에 형성시키는 공정과, 상기 콘택트홀에 금속막을 형성시키는 공정으로 이루어지는 반도체 장치의 금속배선막 도포방법에 있어서, 상기 티타늄막으로 상기 콘택트홀내와 상기 절연막상에 형성하는 공정과, 셀프-얼라인(Self-align) 방식으로 상기 콘택트홀내에 티타늄 실리사이드막을 형성시키는 공정과, 화학 증착법에 의하여 텅스텐막을 상기 티타늄 실리사이드막위에 선택적으로 도포시키는 공정과, 상기 텅스텐막 및 상기 절연막의 상부에 금속막을 형성시키는 공정을 포함하는 반도체 장치의 금속배선막 도포방법.Forming an insulating film on the entire surface of the substrate after forming an impurity implantation region in a predetermined region of the substrate; forming a contact hole on the impurity implantation region by removing a predetermined region of the insulating layer; A metal wiring film coating method for a semiconductor device comprising a step of forming a metal film, the method comprising: forming in the contact hole and the insulating film with the titanium film, and in the contact hole in a self-aligned manner. Forming a titanium silicide film; selectively applying a tungsten film on the titanium silicide film by chemical vapor deposition; and forming a metal film on top of the tungsten film and the insulating film. Way.
KR1019880008602A 1988-07-11 1988-07-11 Application method for metal layer of semiconductor KR920008842B1 (en)

Priority Applications (2)

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KR1019880008602A KR920008842B1 (en) 1988-07-11 1988-07-11 Application method for metal layer of semiconductor
JP1171322A JPH0266940A (en) 1988-07-11 1989-07-04 Application method for metallic wiring film of semiconductor device

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Application Number Priority Date Filing Date Title
KR1019880008602A KR920008842B1 (en) 1988-07-11 1988-07-11 Application method for metal layer of semiconductor

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KR920008842B1 true KR920008842B1 (en) 1992-10-09

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100844459B1 (en) * 2006-07-24 2008-07-08 정연일 Apparatus for Supplying Power for Ellectrically Driven Reel for Fishing Rod

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61216433A (en) * 1985-03-22 1986-09-26 Mitsubishi Electric Corp Manufacture of semiconductor device
JPS6254470A (en) * 1985-09-03 1987-03-10 Seiko Epson Corp Manufacture of semiconductor device
JPS62145774A (en) * 1985-12-20 1987-06-29 Agency Of Ind Science & Technol Semiconductor device
JPS63160328A (en) * 1986-12-24 1988-07-04 Mitsubishi Electric Corp Manufacture of semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100844459B1 (en) * 2006-07-24 2008-07-08 정연일 Apparatus for Supplying Power for Ellectrically Driven Reel for Fishing Rod

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KR900002448A (en) 1990-02-28
JPH0266940A (en) 1990-03-07

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