JPS63160328A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS63160328A
JPS63160328A JP61309838A JP30983886A JPS63160328A JP S63160328 A JPS63160328 A JP S63160328A JP 61309838 A JP61309838 A JP 61309838A JP 30983886 A JP30983886 A JP 30983886A JP S63160328 A JPS63160328 A JP S63160328A
Authority
JP
Japan
Prior art keywords
layer
titanium
titanium nitride
nitride layer
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP61309838A
Other languages
Japanese (ja)
Inventor
Hajime Arai
新井　肇
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP61309838A priority Critical patent/JPS63160328A/en
Priority to KR1019870009827A priority patent/KR910002452B1/en
Priority to DE19873743591 priority patent/DE3743591A1/en
Publication of JPS63160328A publication Critical patent/JPS63160328A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76855—After-treatment introducing at least one additional element into the layer
    • H01L21/76856—After-treatment introducing at least one additional element into the layer by treatment in plasmas or gaseous environments, e.g. nitriding a refractory metal liner
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
    • H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System the conductive layers comprising silicides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76855—After-treatment introducing at least one additional element into the layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53214—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being aluminium
    • H01L23/53223—Additional layers associated with aluminium layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

PURPOSE:To prevent a semiconductor layer from being eroded due to a reaction of titanium with the semiconductor layer by a method wherein a first titanium nitride layer is formed on the surface of the semiconductor layer exposed inside a contact hole and a second titanium nitride layer is formed on the layer. CONSTITUTION:A contact hole 3 is made at a prescribed part at an insulating film 2 formed on a silicon substrate 1. After titanium has been deposited on the surface, a first titanium layer 4a is formed. Then, after nitrification in an atmosphere of nitrogen by means of RTP, the layer is transformed into a first titanium nitride layer 4. During this process, due to a reaction of titanium with silicon, a titanium silicide layer 6 is formed at the interface between the silicon substrate 1 and the titanium nitride layer 4. In addition, after titanium has been deposited again on the layer, a second titanium layer 7a is formed. Then, if the layer is transformed into a second titanium nitride layer 7 after the nitrification in the atmosphere of nitrogen by means of RTP, a thick titanium nitride layer 8 which acts as a barrier metal layer in combination with the titanium nitride layer 4 at the under layer is formed.

Description

【発明の詳細な説明】 ［産業上の利用分野コ この発明は、半導体装置の製造方法に関し、特にバリツ
メタル層の製造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for manufacturing a burr metal layer.

ｒ従来の技術〕 第２Ａ図〜ｉ２ｃ図は、Ｒ＋　Ｐ　（Ｒａｐｉｄ　　Ｔ
ｈｅｒｌｌｌａｌ　　ｐｒｏｃｅｓｓ）技術、すなわち
強力なランプニよる急速加熱の技術を用いて形成された
窒化チタニウムによる従来のバリアメタル層の製造方法
を示す工程断面図である。rPrior art] Figures 2A to 2c show R+P (Rapid T
1 is a cross-sectional view illustrating a conventional method for manufacturing a barrier metal layer made of titanium nitride formed using a rapid heating technique using a powerful lamp.

まず、第２Ａ図に示すように、シリコン基板１上に形成
されたＰ！縁膜２の所定箇所に、シリコン基板１と電気
的コンタク！−を得るためのコンタクトホール３を設け
る。そして、表面にチタニウムをスパッタ法、蒸着法笠
により堆積することによってチタニウムＥ１４０ａを形
成する。なお、この場合、第２Ａ図に示すように、コン
タクトホール３下部におけるシリコン基板１の領域に、
不純物を注入して活性化することにより不純物拡散層５
が形成されていることもある。First, as shown in FIG. 2A, P! is formed on a silicon substrate 1. Electrical contact with the silicon substrate 1 is made at a predetermined location on the membrane 2! A contact hole 3 is provided to obtain -. Then, titanium E140a is formed by depositing titanium on the surface by sputtering or vapor deposition. In this case, as shown in FIG. 2A, in the area of the silicon substrate 1 below the contact hole 3,
The impurity diffusion layer 5 is formed by implanting and activating impurities.
is sometimes formed.

次に、第２Ｂ図に示すように、窒素雰囲気中でＲＴＰを
行なうことによりこのチタニウムｇ４０８を窒化して窒
化チタニウム層４ｏとする。この際、チタニウムとシリ
コンとが反応して窒化チタニウム層４０とシリコン基板
１との界面にチタニウムシリサイド層６が形成される。Next, as shown in FIG. 2B, this titanium g408 is nitrided to form a titanium nitride layer 4o by performing RTP in a nitrogen atmosphere. At this time, titanium and silicon react to form a titanium silicide layer 6 at the interface between the titanium nitride layer 40 and the silicon substrate 1.

最後に、第２Ｃ図に示すように、この窒化チタニウム層
４０の上にアルミニウム合金層９をスパッタ法、蒸着法
等により形成し、バターニングして配線を形成°ｆる。Finally, as shown in FIG. 2C, an aluminum alloy layer 9 is formed on the titanium nitride layer 40 by sputtering, vapor deposition, etc., and patterned to form wiring.

このようにして形成された窒化チタニウム層４０は緻密
であるので、上囮のアルミニウム合１ｆ１９のアルミニ
ウムとシリコン長板１とが反応してアルミニウムによる
接合の突抜けが発生することを防止する。アルミニウム
の突抜けに対するバリア作用は、コンタクトホール３の
底部にＪ５ける窒化チタニウム４０のｍｓが１５０ＸＤ
上であれば発揮されるが、よりバリア作用を高めるため
には、膜厚が厚いほど良い。Since the titanium nitride layer 40 formed in this manner is dense, it prevents the aluminum of the upper decoy aluminum alloy 1f19 from reacting with the long silicon plate 1, thereby preventing the bond from breaking through due to the aluminum. The barrier effect against aluminum punch-through is that the ms of titanium nitride 40 at J5 at the bottom of contact hole 3 is 150XD.
However, in order to further enhance the barrier effect, the thicker the film, the better.

たとえば、チタニウムの堆積によって形成されたチタニ
ウム層４０ａの膜厚が１００ＯＡのとき、ＲＴＰによっ
てコンタクトホール３の底部に形成される窒化チタニウ
ム層４０の膜厚は約３００Ａであり、チタニウムシリサ
イド６の膜厚は約１５００人である。このとき、チタニ
ウムＷ！Ｉ４０ａとシリコン基板１との反応によってシ
リコン基板′１が約８００λ浸食され、コンタクトホー
ル３の部分での接合深さ×ト　　が浅くなる。For example, when the thickness of the titanium layer 40a formed by titanium deposition is 100 OA, the thickness of the titanium nitride layer 40 formed at the bottom of the contact hole 3 by RTP is about 300 Å, and the thickness of the titanium silicide 6 is There are approximately 1,500 people. At this time, Titanium W! Due to the reaction between I40a and the silicon substrate 1, the silicon substrate '1 is eroded by about 800λ, and the junction depth x t at the contact hole 3 becomes shallow.

［発明が解決しようとする問題点〕 上記のように、チタニウムを１０００Ａ堆積させた場合
、シリサイド化により失われるシリコン基板１の深さは
約８００Ａ程度であるが、部分的にはさらに深い領域ま
で浸食されており、実際には接合深さｘＪ　　が３００
０Ａの場合にもジ１！ンクションリークが発生していた
。[Problems to be Solved by the Invention] As mentioned above, when titanium is deposited at 1000A, the depth of the silicon substrate 1 lost due to silicidation is about 800A, but in some parts even deeper regions are lost. It has been eroded, and the actual joint depth xJ is 300
Ji1 even in case of 0A! A leak was occurring.

微細化が進み、さらに接合深さ×よ　が浅（なった場合
には、チタニウムシリサイド層６を薄クシてシリサイド
化によって失われるシリコン基板１の深さを浅くする必
要がある。しかしながら、従来の製造方法によれば、チ
タニウムシリサイド層６の厚さを薄くするためには、堆
積させるチタニウムの膜厚を薄くする必要があり、これ
は、コンタクトホール底部の窒化チタニウム層４０の膜
厚を薄くすることになり、バリアメタルとしての性能は
低下する。As miniaturization progresses and the junction depth x y becomes shallower, it is necessary to thin the titanium silicide layer 6 to reduce the depth of the silicon substrate 1 that is lost due to silicide. According to the manufacturing method, in order to reduce the thickness of the titanium silicide layer 6, it is necessary to reduce the thickness of the titanium to be deposited, and this reduces the thickness of the titanium nitride layer 40 at the bottom of the contact hole. As a result, its performance as a barrier metal deteriorates.

この発明は上記のような問題点を解消するためになされ
たもので、バリアメタルとしての性能を高く保ちながら
、チタニウムと半導体層との反応による半導体心の浸食
を抑えることのできる半導体装置の製造方法を得ること
を目的とする。This invention was made to solve the above-mentioned problems, and aims to manufacture a semiconductor device that can suppress corrosion of the semiconductor core due to the reaction between titanium and the semiconductor layer while maintaining high performance as a barrier metal. The purpose is to obtain a method.

Ｅ問題点を解決するための手段］ この発明に係る半導体装置の製造方法は、まず、コンタ
クトホール内に露出した半導体層の表面上にｇｉＸｌの
チタニウム層を形成し、この第１のチタニウム層を窒素
雰囲気中での熱処理により窒化することによって第１の
窒化チタニウム層を形成する。さらに、この第１の窒化
チタニウム病上に第２のブ・クニウム日を形成し、この
第２のチタニウム日を窒素雰囲気中での熱処理により窒
化することによって第２の窒化チタニウム層を形成する
。Means for Solving Problem E] In the method for manufacturing a semiconductor device according to the present invention, first, a titanium layer of giXl is formed on the surface of the semiconductor layer exposed in the contact hole, and this first titanium layer is A first titanium nitride layer is formed by nitriding by heat treatment in a nitrogen atmosphere. Further, a second titanium layer is formed on the first titanium nitride layer, and the second titanium layer is nitrided by heat treatment in a nitrogen atmosphere to form a second titanium nitride layer.

［作用］ この発明に係る半導体装置の製造方法においてＧｊ　Ｍ
　第１のチタニウム層の窒化により得られた第１の窒化
チタニウム史によって、第２のチタニウム層と半導体層
とが接触しないため、第２のチタニウム層と半導体層と
は反応せず、この第２のチタニウム層は窒化によって全
体が窒化チタニウム層となる。[Function] In the method for manufacturing a semiconductor device according to the present invention, Gj M
Due to the first titanium nitride history obtained by nitriding the first titanium layer, the second titanium layer and the semiconductor layer do not come into contact with each other, so the second titanium layer and the semiconductor layer do not react, and this second The entire titanium layer becomes a titanium nitride layer by nitriding.

デクニウムシリサイド層は、第１のチタニウム層の窒化
の際に形成されるだけであるので、チタニウム層との反
応により浸食される半導体口の厚さは、第１のチタニウ
ム層のｍ厚を薄くすることで抑えられる。Since the decnium silicide layer is only formed during the nitridation of the first titanium layer, the thickness of the semiconductor hole that is eroded by the reaction with the titanium layer is smaller than the m thickness of the first titanium layer. It can be suppressed by doing.

このようにして、チタニウム層と半導体層との界面にお
ける両者の反応により浸食される半導体層のｇさを抑え
ながら、」−分な厚さの窒化チタニウム層をコンタクト
ホール底部において得ることが可能となる。In this way, it is possible to obtain a titanium nitride layer with a thickness of 100-300 mm at the bottom of the contact hole while suppressing the stiffness of the semiconductor layer that is eroded by the reaction between the titanium layer and the semiconductor layer at the interface between the two. Become.

［実施例］ 以下、この発明の一実施例を図面を用いて説明する。[Example] An embodiment of the present invention will be described below with reference to the drawings.

第１Ａ図〜第１Ｄ図は、この発明によるバリアメタル層
の製造方法の一実施例を示す工程断面図である。FIGS. 1A to 1D are process cross-sectional views showing an embodiment of a method for manufacturing a barrier metal layer according to the present invention.

まず、第１Ａ図に示すように、シリコン基板１上に形成
された絶縁膜２の所定箇所にコンタクトホール３を設け
る。そして表面にチタニウムをスパッタ法、蒸着法等に
より従来より薄く堆積することによって第１のチタニウ
ム層４ａを形成する。First, as shown in FIG. 1A, contact holes 3 are provided at predetermined locations in an insulating film 2 formed on a silicon substrate 1. As shown in FIG. Then, a first titanium layer 4a is formed by depositing titanium on the surface thinner than conventionally by sputtering, vapor deposition, or the like.

なお、この場合、第１Ａ図のように、コンタクトホール
３下部におけるシリコン基板１の領域に不純物拡散層５
が形成されていることもある。In this case, as shown in FIG. 1A, an impurity diffusion layer 5 is formed in the region of the silicon substrate 1 below the contact hole 3.
is sometimes formed.

次に、第１Ｂ図に示すように、この第１のチタニウムｆ
ｆ１４ａを窒素雰囲気中でのＲＴＰにより窒化すること
によって第１の窒化チタニウム層４とする。この際、チ
タニウムとシリコンとの反応によってシリコン基板１と
窒化チタニウム層４との界面にチタニウムシリサイド１
１６が形成される。Next, as shown in FIG. 1B, this first titanium f
The first titanium nitride layer 4 is formed by nitriding f14a by RTP in a nitrogen atmosphere. At this time, due to the reaction between titanium and silicon, titanium silicide 1 is formed at the interface between the silicon substrate 1 and the titanium nitride layer 4.
16 is formed.

さらに、第１Ｃ図に示すように、前記窒化チタニウム磨
４上に再度チタニウムを堆積することによって第２のチ
タニウム層７ａを形成する。Furthermore, as shown in FIG. 1C, titanium is deposited again on the titanium nitride polishing 4 to form a second titanium layer 7a.

次いで、第１Ｄ図に示すように、この第２のチタニウム
層７ａを窒素雰囲気中でのＲＴＰにより窒化することに
よって第２の窒化チタニウム層７とすると、下層の窒化
チタニウム層４と合わせてバリアメタル層となる厚い窒
化チタニウム層８が形成される。Next, as shown in FIG. 1D, when this second titanium layer 7a is nitrided by RTP in a nitrogen atmosphere to form a second titanium nitride layer 7, a barrier metal layer is formed together with the lower titanium nitride layer 4. A thick titanium nitride layer 8 is formed.

以上のような製造方法によると、最初に薄く形成された
第１の窒化チタニウム［４によって、２回目に形成され
た第２のチタニウムＲ７ａがシリコン基板１またはデク
ニウムシリサイド層６と接していないので、ＲＴＰによ
り窒化を行なう際に第２のチタニウムｆｆ１７ａがシリ
サイド化されることはない。したがって、高いバリア性
能を得るのに十分な窒化チタニウム層８を、従来よりも
薄いチタニウム層でｊｗ３成４゛ることができる。According to the manufacturing method described above, the first titanium nitride [4 formed thinly at first causes the second titanium R7a formed second time not to be in contact with the silicon substrate 1 or the decnium silicide layer 6. , the second titanium ff17a is not silicided when nitriding is performed by RTP. Therefore, the titanium nitride layer 8 sufficient to obtain high barrier performance can be formed using a titanium layer that is thinner than before.

たとえば、Ｍ２Ａ図・〜第２Ｃ図に示した従来の製造方
法では、３００Ａの窒化チタニウム層４０を得るために
は、チタニウムＭ４０ａを約１０００Ａ堆積する必要が
ある。この際、デクニウムシリサイド層６が約１５００
Ａ形成され、シリコン基板１はコンタクトホール３の部
分で約８００Ａ浸食される。For example, in the conventional manufacturing method shown in Figures M2A to 2C, in order to obtain the titanium nitride layer 40 of 300A, it is necessary to deposit about 1000A of titanium M40a. At this time, the thickness of the decnium silicide layer 6 is about 1500
A is formed, and the silicon substrate 1 is eroded by about 800 A at the contact hole 3 portion.

これに対して、この発明による上記の製造方法によれば
、まず、第１のチタニウム１Ｉ４ａを５０ＯＡ堆積し、
ＲＴＰにより窒化すると、第１の窒化チタニウム層４が
約＋５ｏＡとチタニウムシソサイドｒｆｔ　６が約７５
ＯＡ形成され、シリコン基板１は約４００Ａ浸食される
。次に、第２のチタニウム１７ａを１５ＯＡ堆積し、Ｒ
ＴＰにより窒化すると、１５０人の第２の窒化チタニウ
ム層７が形成され、合計３００Ａの窒化チタニウム層８
が形成されることになる。On the other hand, according to the above manufacturing method according to the present invention, first, 50OA of the first titanium 1I4a is deposited,
When nitrided by RTP, the first titanium nitride layer 4 is about +5oA and the titanium sisoside rft 6 is about 75
OA is formed and the silicon substrate 1 is eroded by about 400A. Next, 15OA of second titanium 17a is deposited, and R
When nitrided by TP, a second titanium nitride layer 7 of 150 is formed, with a total of 300 A of titanium nitride layer 8
will be formed.

したがって、上記の製造方法によると、３００Ａの窒化
チタニウム層８を得る場合、シリコン基板１は約４００
Ａ浸食されるだけである。Therefore, according to the above manufacturing method, when obtaining the titanium nitride layer 8 of 300A, the silicon substrate 1 has a thickness of about 400A.
A: It will only be eroded.

なお、上記実施例においては、チタニウムの堆積を２回
に分割して行なっているが、３回以上に分割して行なっ
てもよく、上記実施例と同様の効果が得られる。Incidentally, in the above embodiment, the titanium deposition is carried out in two divided steps, but it may be carried out in three or more divided steps, and the same effect as in the above embodiment can be obtained.

また、この窒化チタニウムｍ８に接する部分は、シリコ
ン基板１に限られず、下層に形成されているポリシリコ
ン配線層であってもよく、この場合にはポリシリコンの
浸食を押えることができる。Further, the portion in contact with the titanium nitride m8 is not limited to the silicon substrate 1, but may be a polysilicon wiring layer formed below, and in this case, erosion of the polysilicon can be suppressed.

［発明の効果］ 以上のようにこの発明によれば、チタニウム層の形成お
よびそのチタニウム層の窒化を少なくとも２回に分けて
行なうことにより、コンタクトホール底部におけるチタ
ニウム層と半導体層との反応を薄く抑えながら、十分に
厚い窒化チタニウム層を得ることができるので、バリア
メタルとして高い性能を得ることができ、かつ、下層の
半導体層におけるジャンクションリーク等の不良の発生
を防止することができる。[Effects of the Invention] As described above, according to the present invention, by performing the formation of the titanium layer and the nitridation of the titanium layer in at least two steps, the reaction between the titanium layer and the semiconductor layer at the bottom of the contact hole can be thinned. Since it is possible to obtain a sufficiently thick titanium nitride layer while suppressing the thickness of the titanium nitride layer, it is possible to obtain high performance as a barrier metal and to prevent defects such as junction leak in the underlying semiconductor layer.

また、この発明によれば、チタニウム層と半導体層との
反応が１く抑えられるので、同じ厚さの窒化チタニウム
層を得るために必要なチタニウムの膜厚も薄くなり、チ
タニウムの消費量、および、チタニウムの堆積のために
必要な時間を削減できる。Further, according to the present invention, since the reaction between the titanium layer and the semiconductor layer is suppressed to one level, the thickness of the titanium film required to obtain a titanium nitride layer of the same thickness is also reduced, reducing the amount of titanium consumed and , the time required for titanium deposition can be reduced.

【図面の簡単な説明】[Brief explanation of the drawing]

第１Ａ図〜第１Ｄ図はこの発明に係る半導体装置の製造
方法の一実施例を示す工程断面図、第２Ａ図〜第２Ｃ図
は従来の半導体装置の製造方法を示す工程断面口である
。 図において、１はシリコン基板、２は絶縁膜、３はコン
タクトホール、４ａは第１のチタニウム層、４は第１の
窒化チタニウム層、７ａは第２のチタニウム層、７は第
２の窒化チタニウム層である。 なお、各図中同一符号は同一または相当部分を示す。 代理人　　　大　　岩　　増　　雄 第１Ａ図 ；ｉｙ　ｌ　８回 第１Ｃ回 ｙ、１０回 第２Ａ回 第２日回 第２０回1A to 1D are process cross-sectional views showing one embodiment of the method for manufacturing a semiconductor device according to the present invention, and FIGS. 2A to 2C are process cross-sectional views showing a conventional method for manufacturing a semiconductor device. In the figure, 1 is a silicon substrate, 2 is an insulating film, 3 is a contact hole, 4a is a first titanium layer, 4 is a first titanium nitride layer, 7a is a second titanium layer, and 7 is a second titanium nitride layer. It is a layer. Note that the same reference numerals in each figure indicate the same or corresponding parts. Agent Masuo Oiwa Figure 1A; iy l 8th 1C y, 10th 2A 2nd day 20th

Claims (5)

【特許請求の範囲】[Claims] （１）半導体層上に絶縁膜を形成し、前記絶縁膜の所定
箇所にコンタクトホールを開孔して前記半導体層の表面
を露出させ、前記半導体層の表面上に第１のチタニウム
層を形成し、この第１のチタニウム層を窒素雰囲気中で
の熱処理により窒化することによつて第１の窒化チタニ
ウム層を形成し、さらに、前記第１の窒化チタニウム層
上に第２のチタニウム層を形成し、この第２のチタニウ
ム層を窒素雰囲気中での熱処理により窒化することによ
つて第２の窒化チタニウム層を形成する半導体装置の製
造方法。(1) An insulating film is formed on the semiconductor layer, a contact hole is opened at a predetermined location in the insulating film to expose the surface of the semiconductor layer, and a first titanium layer is formed on the surface of the semiconductor layer. Then, a first titanium nitride layer is formed by nitriding this first titanium layer by heat treatment in a nitrogen atmosphere, and a second titanium layer is further formed on the first titanium nitride layer. A method for manufacturing a semiconductor device in which a second titanium nitride layer is formed by nitriding the second titanium layer by heat treatment in a nitrogen atmosphere. （２）前記半導体層は、シリコン基板またはポリシリコ
ン配線層であることを特徴とする特許請求の範囲第１項
記載の半導体装置の製造方法。(2) The method for manufacturing a semiconductor device according to claim 1, wherein the semiconductor layer is a silicon substrate or a polysilicon wiring layer. （３）前記半導体層は、シリコン基板内にリン、ボロン
、ヒ素等の不純物がイオン注入、熱拡散等により注入さ
れた不純物拡散層であることを特徴とする特許請求の範
囲第１項または第２項記載の半導体装置の製造方法。(3) The semiconductor layer is an impurity diffusion layer in which impurities such as phosphorus, boron, arsenic, etc. are implanted into a silicon substrate by ion implantation, thermal diffusion, etc. 2. A method for manufacturing a semiconductor device according to item 2. （４）前記チタニウム層の熱処理は、ＲＴＰ（Ｒａｐｉ
ｄＴｈｅｒｍａｌＰｒｏｃｅｓｓ）技術を用いたもので
あることを特徴とする特許請求の範囲第１項ないし第３
項のいずれかに記載の半導体装置の製造方法。(4) The heat treatment of the titanium layer is performed using RTP (Rapi).
Claims 1 to 3 are characterized in that the invention uses dThermalProcess) technology.
A method for manufacturing a semiconductor device according to any one of paragraphs. （５）前記第２の窒化チタニウム層の形成後、さらにチ
タニウム層の形成およびそのチタニウム層の窒化による
窒化チタニウム層の形成を少なくとも１回以上行なうこ
とを特徴とする特許請求の範囲第１項ないし第４項のい
ずれかに記載の半導体装置の製造方法。(5) After forming the second titanium nitride layer, forming a titanium layer and forming a titanium nitride layer by nitriding the titanium layer are performed at least once or more. 4. A method for manufacturing a semiconductor device according to any one of Item 4.
JP61309838A 1986-12-24 1986-12-24 Manufacture of semiconductor device Pending JPS63160328A (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP61309838A JPS63160328A (en) 1986-12-24 1986-12-24 Manufacture of semiconductor device
KR1019870009827A KR910002452B1 (en) 1986-12-24 1987-09-05 Manufacture of semiconductor device
DE19873743591 DE3743591A1 (en) 1986-12-24 1987-12-22 Method for fabricating a semiconductor arrangement

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61309838A JPS63160328A (en) 1986-12-24 1986-12-24 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS63160328A true JPS63160328A (en) 1988-07-04

Family

ID=17997879

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61309838A Pending JPS63160328A (en) 1986-12-24 1986-12-24 Manufacture of semiconductor device

Country Status (3)

Country Link
JP (1) JPS63160328A (en)
KR (1) KR910002452B1 (en)
DE (1) DE3743591A1 (en)

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JPH03280424A (en) * 1990-03-28 1991-12-11 Sony Corp Wiring formation process
JPH04226062A (en) * 1990-04-06 1992-08-14 Philips Gloeilampenfab:Nv Semiconductor device

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DE3930655A1 (en) * 1988-09-13 1990-03-22 Mitsubishi Electric Corp Semiconductor module with laminated coupling layer - has coupling section, extending over insulating film on semiconductor substrate main surface
NL8900010A (en) * 1989-01-04 1990-08-01 Philips Nv SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE.
US5236868A (en) * 1990-04-20 1993-08-17 Applied Materials, Inc. Formation of titanium nitride on semiconductor wafer by reaction of titanium with nitrogen-bearing gas in an integrated processing system
US5250467A (en) * 1991-03-29 1993-10-05 Applied Materials, Inc. Method for forming low resistance and low defect density tungsten contacts to silicon semiconductor wafer
JP3280803B2 (en) * 1994-08-18 2002-05-13 沖電気工業株式会社 Semiconductor device and manufacturing method thereof
US5877087A (en) * 1995-11-21 1999-03-02 Applied Materials, Inc. Low temperature integrated metallization process and apparatus
US6066358A (en) * 1995-11-21 2000-05-23 Applied Materials, Inc. Blanket-selective chemical vapor deposition using an ultra-thin nucleation layer
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US6001420A (en) 1996-09-23 1999-12-14 Applied Materials, Inc. Semi-selective chemical vapor deposition
US6537905B1 (en) 1996-12-30 2003-03-25 Applied Materials, Inc. Fully planarized dual damascene metallization using copper line interconnect and selective CVD aluminum plug
US6110828A (en) * 1996-12-30 2000-08-29 Applied Materials, Inc. In-situ capped aluminum plug (CAP) process using selective CVD AL for integrated plug/interconnect metallization
US6139905A (en) * 1997-04-11 2000-10-31 Applied Materials, Inc. Integrated CVD/PVD Al planarization using ultra-thin nucleation layers
US6605531B1 (en) 1997-11-26 2003-08-12 Applied Materials, Inc. Hole-filling technique using CVD aluminum and PVD aluminum integration
KR100510465B1 (en) * 1998-05-12 2005-10-24 삼성전자주식회사 Method for forming barrier metal layer in semiconductor device
US6797620B2 (en) 2002-04-16 2004-09-28 Applied Materials, Inc. Method and apparatus for improved electroplating fill of an aperture

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DE3140669A1 (en) * 1981-10-13 1983-04-28 Siemens AG, 1000 Berlin und 8000 München METHOD FOR PRODUCING SEMICONDUCTOR DEVICES

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0266940A (en) * 1988-07-11 1990-03-07 Samsung Electron Co Ltd Application method for metallic wiring film of semiconductor device
JPH03280424A (en) * 1990-03-28 1991-12-11 Sony Corp Wiring formation process
JPH04226062A (en) * 1990-04-06 1992-08-14 Philips Gloeilampenfab:Nv Semiconductor device

Also Published As

Publication number Publication date
DE3743591A1 (en) 1988-07-07
KR910002452B1 (en) 1991-04-22
DE3743591C2 (en) 1992-12-17
KR880008418A (en) 1988-08-31

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