JPH08316476A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE: To provide a semiconductor device of a structure, wherein a spike phenomenon in the formation of the contact of an aluminium wiring with a diffused layer is prevented from being generated without depending upon a barrier metal method and at the same time, a stable salicide process is possible, and a method of manufacturing the semiconductor device. CONSTITUTION: A silicon nitride later (an Si3 N4 layer) 31 for protecting the junction surface between a silicon base body 21 and an N<+> impurity diffused region 23 is formed in the interior of the region 23 along this junction surface by an ion-implantation. By the existence of this layer 31, the local abnormal reaction of silicon to a high-melting point metal is inhibited at the time of a heat treatment for forming silicide layers 26 and 28 and a breaking of the junction between the base body 21 and the region 23 is prevented from being caused. Moreover, the generation of a spike phenomenon in the vertical direction due to a sintering heat treatment for forming the stable contact of the region 23 with an aluminium wiring is also prevented.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a PN junction with an impurity diffusion layer on the surface of a semiconductor substrate and a method for manufacturing the same.

[0002]

2. Description of the Related Art Conventionally, in the impurity diffusion layer of this type of semiconductor device, a contact is formed with a metal wiring such as aluminum. FIG. 6 shows a cross section of an essential part of an NMOS semiconductor device as such a semiconductor device. As shown in this figure, a so-called LOCOS (Local Oxidation of Silicon) is formed on the P-type silicon substrate 11.
The element isolation film 12 made of a silicon oxide film is partially formed by the method. The element active region on the silicon substrate 11 partitioned by the element isolation film 12 has N
A gate electrode (not shown) of the MOS transistor is formed, and an N ⁺ impurity diffusion region 13 as a source or drain region is formed adjacent to the gate electrode. The N ⁺ impurity diffusion region 13 and the element isolation film 12 are covered with an interlayer insulating film 14 made of a silicon oxide film. In the upper region of the N ⁺ impurity diffusion region 13 of the interlayer insulating film 14, N ⁺
An opening 15 reaching the impurity diffusion region 13 is provided, thereby forming a contact with the aluminum wiring layer 16.

In the semiconductor device having such a structure, in order to form a good ohmic contact between the N ⁺ impurity diffusion region 13 and the aluminum wiring layer 16 and to improve the adhesion between them, the temperature is, for example, about 400 ° C. Heat treatment (sintering) at temperature is required. However, due to this heat treatment, the aluminum wiring layer 16 and the silicon substrate 11
Mutual heat diffusion occurs between and, so-called vertical spike phenomenon often occurs. In this case, as shown in FIG. 6, the spike 17 as an aluminum-silicon alloy is used.
May penetrate through the joint surface between the silicon substrate 11 and the N ⁺ impurity diffusion region 13 to cause so-called junction leak. This problem becomes particularly noticeable under the tendency to form the N ⁺ impurity diffusion region 13 shallowly as the degree of integration increases.

As a method for solving such a problem, there is a so-called barrier metal process. This method is shown in FIG.
, The N ⁺ impurity diffusion region 1 of the interlayer insulating film 14
3 is a method in which an opening 15 is provided in the upper region of 3, and a barrier metal layer 18 is deposited by a sputtering method, and then an aluminum wiring layer 16 is formed. In addition, in FIG.
The same components as those of the above are denoted by the same reference numerals. According to this method, the spike phenomenon during the heat treatment for sintering can be prevented.

On the other hand, in recent years, in order to meet the demands for device miniaturization and high speed, a silicide process technology for siliciding an impurity diffusion layer and a salicide (self-aligned silicide) for siliciding both a diffusion layer and a gate electrode have been proposed. )
Many process technologies are being used. The salicide process technology will be briefly described below.

FIG. 8 shows a cross section of a main part of an NMOS semiconductor device. As shown in this figure, an element isolation film 22 made of a silicon oxide film is partially formed on a P-type silicon substrate 21 by the LOCOS method.
A gate oxide film 24 of an NMOS transistor is selectively formed in an element active region on the silicon substrate 21 divided by the element isolation film 22, and an N ⁺ impurity diffusion region as a source or drain region is adjacent to the gate oxide film 24. 23
Are formed. A polysilicon (polycrystalline silicon) layer 25 as a gate electrode is formed on the gate oxide film 24. Side walls 27 made of a silicon oxide film are formed on both sides of the polysilicon layer 25, and the so-called LDD (Lightly-Doped-Drain) NM structure is formed.
It constitutes an OS transistor. Furthermore, silicide layers 26 and 28 are formed on the polysilicon layer 25 and the N ⁺ impurity diffusion region 23. The silicide layers 26 and 28 are formed by depositing a refractory metal such as titanium (Ti) by a sputtering method, and then RTA (Rapid-Thermal-Annel).
It is formed by reacting with silicon by heat treatment such as, and further removing unreacted refractory metal with an etchant such as hydrogen peroxide (H ₂ O ₂ ). Although not shown, each of these portions is covered with an interlayer insulating film made of a silicon oxide film, and an opening provided in the interlayer insulating film causes a gap between the silicide layers 26 and 28 and an aluminum wiring layer (not shown). A contact is formed on.

[0007]

However, in the contact forming method by the barrier metal method shown in FIG. 7, a step for forming the barrier metal layer 18 is additionally required, and there is a drawback that the manufacturing process becomes complicated. Along with
There is a problem in that the yield is reduced by dust generated during the sputtering process for forming the barrier metal layer.

In the salicide process technique shown in FIG. 8, abnormal silicidation may occur due to local non-uniform reaction during heat treatment such as RTA for reacting refractory metal with silicon. is there. In this case, as shown in FIG. 8, the alloy layer 29 formed by the abnormal reaction between silicon and the refractory metal causes the silicon substrate 21 and the N ⁺
There is a problem that the junction (junction) with the impurity diffusion region 23 is destroyed.

The present invention has been made in view of the above problems, and an object thereof is to prevent a spike phenomenon at the time of forming a contact with a diffusion layer without using a barrier metal method, and also to prevent diffusion with a gate electrode. It is an object of the present invention to provide a semiconductor device capable of stably performing a salicide process of simultaneously siliciding a layer and a method for manufacturing the semiconductor device.

[0010]

A semiconductor device according to the present invention is a semiconductor substrate of a first conductivity type, an impurity diffusion layer of a second conductivity type formed in the vicinity of the surface of the semiconductor substrate, and this impurity diffusion layer. And a nitride layer provided along the boundary surface between the semiconductor substrate and the impurity diffusion layer. The nitride layer preferably extends at least from the metal wiring layer for connecting to the outside to below the contact region for the impurity diffusion layer.

A method of manufacturing a semiconductor device according to the present invention comprises a step of forming an impurity diffusion layer of a second conductivity type in the vicinity of the surface of a semiconductor substrate of a first conductivity type and implanting nitrogen ions into the impurity diffusion layer. , A step of forming a nitride layer along the boundary surface between the semiconductor substrate and the impurity diffusion layer, and a heat treatment step for correcting disorder of the crystal structure caused by implantation of nitrogen ions. The heat treatment step is preferably performed by RTA (short time annealing).

[0012]

In the semiconductor device or the method for manufacturing the same according to the present invention, the presence of the nitride layer provided inside the impurity diffusion layer causes the formation of the metal wiring contact to the impurity diffusion layer or the formation of the silicide layer on the impurity diffusion layer. Leakage or destruction of the junction between the semiconductor substrate and the impurity diffusion layer during formation is prevented.

[0013]

Embodiments of the present invention will now be described in detail with reference to the drawings.

FIG. 1 shows a cross-sectional structure of a main part of a semiconductor device according to an embodiment of the present invention. Here, NMO
An S semiconductor device will be described as an example. The same components as those in FIG. 8 are designated by the same reference numerals. As shown in this figure, an element isolation film 22 made of a silicon oxide film is partially formed on a P-type silicon substrate 21 by the LOCOS method. An NMOS is formed in the element active region on the silicon substrate 21 partitioned by the element isolation film 22.
The gate oxide film 24 of the transistor is selectively formed,
Adjacent to this is N ⁺ as a source or drain region.
An impurity diffusion region 23 is formed. Gate oxide film 2
A polysilicon layer 25 as a gate electrode is formed on the gate electrode 4. Side walls 27 made of a silicon oxide film are formed on both sides of the polysilicon layer 25, and the NM of the LDD structure is formed.
It constitutes an OS transistor. Further, on the polysilicon layer 25 and the N ⁺ impurity diffusion region 23, a silicide layer 26 using a refractory metal such as titanium (Ti),
28 are formed. The silicide layers 26 and 28
As described later, after depositing a refractory metal such as titanium (Ti) by a sputtering method, RTA (Rapid-Thermal-An
nel; heat treatment such as annealing for a short time) to react with silicon, and unreacted refractory metal is converted to hydrogen peroxide (H
It is formed by removing it with an etchant such as ₂ O ₂ ).

Further, in this NMOS semiconductor device, N
⁺ Inside the impurity diffusion region 23, the silicon substrate 21 and the N
A silicon nitride layer (Si ₃ N ₄ ) 31 is formed along the joint surface with the ⁺ impurity diffusion region 23 to protect the joint surface.

Although not shown, each of the above element portions is covered with an interlayer insulating film made of a silicon oxide film, and the silicide layers 26, 2 are formed by openings provided in the interlayer insulating film.
8 is formed between the aluminum wiring layer 8 and an aluminum wiring layer (not shown).

In such a semiconductor device, the presence of the silicon nitride layer 31 suppresses a local abnormal reaction between silicon and the refractory metal during the heat treatment for forming the silicide layers 26 and 28, and the silicon substrate The destruction of the junction between 21 and the N ⁺ impurity diffusion region 23 is prevented. The presence of the silicon nitride layer 31 also prevents the vertical spike phenomenon from occurring during the sintering heat treatment for forming a stable contact between the N ⁺ impurity diffusion region 23 and the aluminum wiring.

Next, with reference to FIGS. 2 to 5, a method of manufacturing the semiconductor device having the above configuration will be described.

First, as shown in FIG. 2, an element isolation film 22 made of a silicon oxide film having a film thickness of about 400 nm is selectively formed on the surface of a P-type silicon substrate 21 by the LOCOS method. As a result, a partition is formed between the element isolation region in which the element isolation film 22 is formed and the element active region surrounded by the element isolation film 22.

Next, a gate insulating film 24 made of a silicon oxide film is formed on the surface of the element active region, and then CVD is performed.
A polysilicon layer 25 is deposited by a (Chemical Vapor Deposition) method, a sputtering method, or the like, and is further doped with phosphorus (P) and then patterned to form N.
The gate electrode of the MOS transistor is formed. Although phosphorus is doped by a thermal diffusion method using POCl ₃ , it may be replaced by ion implantation instead. After that, phosphorus, for example, is ion-implanted in a self-aligned manner with the gate electrode. The conditions at that time are, for example, energy 35 KeV, dose amount 3E13.
(3 × e ¹³ ) / cm ² .

Next, as shown in FIG. 3, sidewalls 27 are formed on both sides of the polysilicon layer 25 as a gate electrode.
Specifically, a silicon oxide film (SiO 2
₂ ) is deposited and then anisotropically etched by RIE (reactive ion etching) or the like to form a side wall 27 on the side surface of the polysilicon layer 25. Next, for example, arsenic (A _S ) is implanted by ion implantation in a self-alignment manner with the gate electrode (polysilicon layer 25) to form the N ⁺ impurity diffusion region 23. Ion implantation in this case is performed under the conditions of, for example, an implantation energy of 50 KeV and a dose amount of 5E15 (5 × e ¹⁵ ) / cm ² .

Next, as shown in FIG. 4, the silicon nitride layer (Si _x N _y ) which is a feature of the present invention is provided inside the N ⁺ impurity diffusion region 23 to form the silicon substrate 21 and the N ⁺ impurity diffusion region 23. It is formed along the joint surface of. Specifically, nitrogen (N) is ion-implanted, for example, with an implantation energy of 30 KeV and a dose amount of 1E14 (1 × e).
Implantation is performed from the surface of the N ⁺ impurity diffusion region 23 under the condition of ¹⁴ ) / cm ² , and then activation annealing is performed by, for example, RTA in order to strengthen the bond between Si and N. This activation annealing is performed, for example, at an atmospheric temperature of 1000.
Perform for 10 seconds at ° C.

Next, the N ⁺ impurity diffusion region 23 and the polysilicon layer 25 are silicidized. Specifically, as shown in FIG. 5, a titanium (Ti) layer 32 as a refractory metal, for example, is deposited on the entire surface by a sputtering method or the like, and thereafter,
Activation annealing for silicidation is performed. This activation annealing is performed, for example, at an ambient temperature of 1000 ° C.
Although the RTA is performed for about 0 seconds, the RTA may be performed by a thermal diffusion method using a diffusion furnace.
Furthermore, RTA and the thermal diffusion method may be used together. As a result, the polysilicon layer 25 and the N ⁺ impurity diffusion region 2
The titanium layer 32 in contact with 3 is silicidized and becomes a silicide layer. At this time, the presence of the silicon nitride layer 31 suppresses a local abnormal reaction between the silicon and the refractory metal in the activation annealing, and the silicon substrate 2
The destruction of the junction between 1 and the N ⁺ impurity diffusion region 23 is prevented.

Next, the unreacted titanium layer 32 (that is, the portion not mainly in contact with the N ⁺ impurity diffusion region 23 or the polysilicon layer 25) is treated with hydrogen peroxide solution (H ₂ O).
₂ ) and sulfuric acid (H ₂ SO ₄ ) mixed solution is used for removal.
As a result, as shown in FIG.
And the silicide layer 2 on the N ⁺ impurity diffusion region 23.
6, 28 are formed.

After that, usual MOS process steps are performed. That is, an interlayer insulating film such as a silicon oxide film is formed on the entire surface, an opening reaching the N ⁺ impurity diffusion region 23 is provided in this interlayer insulating film, and this is filled with aluminum to form a contact with an aluminum wiring layer (not shown). Further, sintering heat treatment for stabilizing the contact is performed. At this time, the presence of the silicon nitride layer 31 prevents the vertical spike phenomenon from occurring due to the heat treatment.

[0026]

As described above, according to the semiconductor device and the method of manufacturing the same according to the present invention, the second conductivity type impurity diffusion layer is formed in the vicinity of the surface of the first conductivity type semiconductor substrate. Since the nitride layer is provided along the boundary surface between the semiconductor substrate and the impurity diffusion layer, the presence of this nitride layer protects the junction between the semiconductor substrate and the impurity diffusion layer. That is, without using the conventional barrier metal method, the spike phenomenon at the contact portion between the impurity diffusion layer and the metal wiring such as aluminum is prevented, and the leak or the destruction of the junction between the semiconductor substrate and the impurity diffusion layer is avoided. can do. Therefore, it is possible to eliminate the complicated process of depositing the barrier metal and simplify the manufacturing process, and it is possible to prevent a decrease in yield due to dust generation during deposition of the barrier metal. Further, when the process of siliciding the upper layer portion of the impurity diffusion layer is involved, a local abnormal reaction between silicon and the refractory metal due to activation annealing is suppressed, so that the junction between the semiconductor substrate and the impurity diffusion layer is suppressed. Be protected. Therefore, a stable silicide process becomes possible. Of course, it can also be applied to a salicide process in which the gate electrode and the impurity diffusion layer are simultaneously silicidized.

In particular, according to the method of manufacturing a semiconductor device of the present invention, the barrier layer of the nitride layer can be formed only by the simple steps of nitrogen ion implantation and heat treatment. Therefore, there is an effect that the cost is not increased.

[Brief description of drawings]

FIG. 1 is a sectional view showing a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view showing a method of manufacturing this semiconductor device.

FIG. 3 is a cross-sectional view showing a step that follows the step of FIG.

FIG. 4 is a cross-sectional view showing a step that follows the step of FIG.

FIG. 5 is a side sectional view for explaining a step following FIG.

FIG. 6 is a cross-sectional view showing a contact portion between an impurity diffusion layer and an aluminum wiring in a conventional semiconductor device.

FIG. 7 is a cross-sectional view showing a contact portion between an impurity diffusion layer and an aluminum wiring in another conventional semiconductor device.

FIG. 8 is a cross-sectional view showing a silicidation process of an impurity diffusion layer in another conventional semiconductor device.

[Explanation of symbols]

21 silicon substrate 22 element isolation film 23 N ⁺ impurity diffusion region 24 gate oxide film 25 polysilicon layer 26, 28 silicide layer 27 side wall (silicon oxide layer) 31 silicon nitride layer 32 titanium layer

Claims (5)

[Claims] 1. A semiconductor substrate of a first conductivity type, an impurity diffusion layer of a second conductivity type formed near the surface of the semiconductor substrate, and the semiconductor substrate and the impurity diffusion layer inside the impurity diffusion layer. And a nitride layer provided along a boundary surface between the semiconductor device and the semiconductor device. 2. The semiconductor device according to claim 1, wherein the nitride layer extends at least from a metal wiring layer for connecting to the outside to below a contact region for the impurity diffusion layer. 3. A semiconductor device comprising a refractory metal silicide layer on the impurity diffusion layer. 4. A step of forming an impurity diffusion layer of a second conductivity type in the vicinity of the surface of a semiconductor substrate of a first conductivity type, and implanting nitrogen ions into the inside of the impurity diffusion layer to form the semiconductor substrate and the impurity diffusion layer. A method of manufacturing a semiconductor device, comprising: a step of forming a nitride layer along the boundary surface of the semiconductor layer and a heat treatment step for correcting the disorder of the crystal structure caused by implantation of nitrogen ions. 5. The method for manufacturing a semiconductor device according to claim 4, wherein the heat treatment step is performed by RTA (short time annealing).