DE3930655A1 - Semiconductor module with laminated coupling layer - has coupling section, extending over insulating film on semiconductor substrate main surface - Google Patents

Abstract

The coupling layer has a coupling section in an insulating layer (3) on the main surface of a semiconductor substrate (22). A contact section is coupled to a preset, conductive silicon layer contained in the semiconductor module. The connecting section comprises a metal barrier layer (6), a metal layer (7) with aluminium, and an anti-reflection coating, in this order starting from the surface of the insualting layer. The contact section contains a silicide layer (20), a barrier metal layer, an aluminium layer, and an anti-reflection coating in this order, starting from the surface of the conductive silicon layer. Pref. the anti-reflection coating is made of amorphous silicon. USE/ADVANTAGE - For semiconductor circuits e.g. dynamic RAM, connecting transistorse and diodes to resistors and capacitors in a chip, with increased coupling reliability.

Description

The present invention relates to a semiconductor device with multilayered stacked connection layer claims 1 and 4, and a method for the manufacture thereof position according to the preamble of claim 6.

In particular, the invention relates to a verb structure in which the connection reliability in a multi-layer interconnect semiconductor device structure is increased.

In a semiconductor device or semiconductor circuit a connection layer is needed, the active elements, such as for example transistors and diodes with passive elements such as resistors and capacitors a chip that combines the following characteristics  stika has:

• (1) The layer is said to have a low connection resistance to have.
• (2) The layer should have a low contact resistance compared to materials to be connected, and one Allow formation of an ohmic contact on it.
• (3) The layer should be easy to manufacture and the out formation of a very fine or small connection pattern enable on it.
• (4) The layer should relate to electro-migration as opposed to an electrical particle migration, against be resistant to corrosion and the like, and high Have reliability.

No materials are specified in the prior art that meet all of the above requirements. Instead For example, aluminum (Al), Polysilicon, refractory metals, silicide, polycide and Similar materials as connecting materials depending used by the application. Among the remaining Ma aluminum compound is most common due to their low connection resistance and good Manufacturing properties used. As a result of that in the recently achieved high integration of semiconductor scarf However, their connecting structures were also developed miniaturized so that various problems in the prior art Technology have occurred.

One problem is the phenomenon of electrical migration or electric particle migration, which partially with the increasing current density, which is caused by the miniatu rized line width caused in the connection layer becomes and to an increased connection resistance or an interruption or similar malfunction.  

Another problem is that the depth of the in one Silicon substrate formed pn junction became low which is what makes the aluminum component in the connection layer can penetrate into the transition and a connecting Peak phenomenon can cause the pn junction shortly closed and destroyed. Furthermore, since the contact richly reduced with the listing area, if the pn junction is made flatter, the Abla accumulation of silicon nodules between the connection layer that is contacted with the doping layer, and the silicon substrate may occur as a result of the epi tactical growth from the solid phase a larger Influence, which increases the contact resistance.

Yet another problem is caused by the fact gently that the connection layer on a top layer with protruding surface irregularities is because, due to the high level of integration, a structure is required is in three-dimensionally stacked form is building. For this reason, the layer causes Pattern Generation Process for the Link Layer Using a lithography process a scattering of the exposure rays that ver the resolution of the connection pattern deteriorates what is in an uneven line width the link layer or in breaks or the like errors.

To cope with the above problems, all of them one the connection reliability of the connection The following improvements have been made struck:

First, the compound of structure 7 is shown in FIG. Proposed in layers about the contact between the aluminum compound and to improve a silicon substrate. The specific matic representation of FIG. 7 shows a connection structure with a two-layered structure of a bar centering metal layer 6 and an aluminum alloy layer 7. Furthermore, FIG. 7 typically shows a structure in which an interlayer insulation film 3 is formed on the surface of a silicon substrate 2 with a doping region, whereupon a connection layer 5 is formed on a surface of the interlayer insulation field 3 and inside a contact hole 4 .

The barrier metal layer 6 is formed below the aluminum compound layer 7 as an underlying layer and covers the surface of the silicon substrate 2 in the contact hole 4th

The aluminum alloy layer 7 is formed over the barrier metal layer 6 , whereby direct contact with the silicon substrate 2 can be prevented. Such a two-layer structure enables the barrier metal layer 6 to prevent the penetration of aluminum into the silicon substrate, and also prevents epitaxial silicon growth from the solid phase at the boundary between the substrate and the connecting layer, so that problems such as that Connection tip phenomenon and the deposit of silicon nodules can be solved. Meanwhile, a very small amount of copper (Cu) in the aluminum of the aluminum layer 7 increases the resistance to electro-migration or electric particle migration, so that the problems associated therewith are also solved.

Second, a connection structure according to FIG. 8 was proposed to improve the formation of the connection layer on a level with protruding surface irregularities, as is the case with multilayer connections. The structure shown in FIG. 8 shows a typical contact connection, as can also be seen in FIG. 7.

This second exemplary connection structure includes a two-layer structure composed of an aluminum connection layer 7 and an antireflection coating 8 (hereinafter referred to as "ARC" = antireflection coating). The aluminum compound layer 7 contains a small amount of copper in the aluminum, thereby increasing the resistance to migration or particle migration. The ARC film has a largely low refractive index for the exposure beams used in a photolithographic process. By preventing the reflection of exposure rays in the photolithographic process, the ARC film prevents deterioration of the resolution by refraction of the exposure rays, and thus prevents the width of the connecting lines in the connecting layer from being reduced, the occurrence of interruptions, and the like.

For this reason, the above two improvements have been made games suggested that each solve different problems sen that occur in connection layers, these improved embodiments the characteristics of Improve connection when these embodiments on such connection layers are applied to these Problems. In particular, the first was example for a connection area proposed, which is contacted with a silicon surface. The second Embodiment has been made for a connection area struck that on a less flat surface part in a multilayer connection structure is formed. However, as described above, it has high integration from semiconductor devices to multilayer structures of the connecting layers, which gives rise to the tendency has shown that a connection between the senior Layers of these are formed on a substrate surface Elements is three-dimensional. Therefore there is a Be need for a connection structure with high reliability speed that the above problems for the entire connection can solve layer.

Japanese Patent Laid-Open No. 21 871/1988 discloses another embodiment of a connection  structure. In this embodiment, one is stacked Connection structure shown that a silicide layer, a Metal layer and an anti-reflective aluminum silicide layer includes.

The present is in relation to this prior art Invention, the object of a semiconductor device as well as a process for their production of the ge named kind so that the connection verver casualness is further increased.

This object is achieved in a semiconductor device according to the Preamble of claims 1 and 4 by the in the kenn drawing part of claims 1 and 4 specified Features and in a method according to the preamble of Claim 6 by the in the characterizing part of Features specified 6 solved.

A significant advantage of the present invention lies in the creation of a fine or very fine conductor structure the connection layer in a semiconductor device. Another advantage of the invention is improvement the contact characteristics of the intermediate layer in one Semiconductor device.

Yet another advantage of the invention is that Creation of a manufacturing process with which a very fei Nes conductor pattern of the connection layer in a semiconductor device is achievable.

According to a first aspect of the invention, the connection layer in a semiconductor device stacked structure. With a connecting section that is via an insulation layer on the semiconductor device extends beyond, includes the multilayered stacked structure ture a barrier metal layer, an aluminum metal layer and an anti-reflective coating in this series are arranged from bottom to top.  

According to the second aspect of the invention, the verb comprises layer with the multi-layer stacked structure Barrier metal layer, an aluminum metal layer and a amorphous silicon layer in this order from bottom to bottom above.

The layers mentioned each have their own functions. To next, the aluminum alloy layer in the High conductivity in the middle of the three-layer structure, which is important for a connection layer due to low is resistance characteristics. Second, there it is underlying barrier metal layer between a sili zium layer and the aluminum alloy layer in a Kon clock area with one under the barrier metal layer formed connection layer or with a conductive Area of a doping area and prevents one direct contact between the aluminum and the silicon, causing any reaction between these materials is closed. Therefore, the alloy tip phenomenon or the epitaxial growth from the solid phase of sili nodules can be prevented. Third, the anti improves reflective coating the accuracy of the connection Patterns in photolithography. If an amorphous silicon layer can be used as an anti-reflective coating prevents the deposition of silicon in the aluminum layer be changed.

According to the third aspect of the invention is the connection layer of the semiconductor device with the multilayered ge stacked structure structured such that a predetermined Configuration after sequential creation of a barrier en metal layer, an aluminum alloy layer and one Anti-reflective coating is achieved. After generation the pattern or the structuring of the conductive The upper layer of the anti-reflection area layering removed by etching.

Below are with reference to the accompanying  Drawings preferred embodiments of the present Invention explained in more detail. Show it:

Fig. 1 is a cross sectional view of a memory cell of a DRAM according to a Ausführungsbei game of the present invention;

FIG. 2 shows a top view of the memory cells according to FIG. 1;

Fig. 3 is a typical cross-sectional view of a dummy word line in the memory cells of FIG. 1;

FIGS. 4A-4E are cross sectional views of a connecting structure according to another execution example of the present invention, wherein in order, the manufacturing steps are shown for this ge;

Fig. 5 is a cross sectional view of a connection structure in a manufacturing process that follows that of Fig. 4E;

Fig. 6 is a graph showing the relationship between the reflectivity and the thickness of the amorphous silicon film used as an anti-reflection coating;

Fig. 7 is a cross-sectional view of a connecting layer in a semiconductor device according to an earlier proposal;

Fig. 8 is a cross sectional view of another example guidance from a link layer of an accelerator as earlier proposal.

A DRAM (dynamic random access memory) with stacked capacitor cells is explained below as an exemplary embodiment of the invention. As shown in FIGS. 1 and 2, a DRAM has a structure of a memory cell array. The memory cell array comprises a plurality of word lines 10 a , 10 b , 10 c , 10 d , which extend in the direction of the rows, and a plurality of bit lines 11 a , 11 b , which extend in the direction of the columns and cut vertically with them. Furthermore, second word lines (hereinafter referred to as auxiliary word lines) 12 a , 12 b , 12 c , 12 d are formed in upper sections of the word lines 10 a - 10 d , which overlap with these. In the vicinity of the respective intersection of the word lines 10 a - 10 d and the bit lines 11 a and 11 b , a memory cell 13 is formed. Each memory cell 13 comprises a single trans fergate transistor 14 and a single capacitor 15 . The transfer gate transistor 14 includes a gate electrode disposed on the surface of a p-type semiconductor substrate 2 , with a gate oxide film 16 disposed between these layers. The gate electrodes form part of the word lines 10 a - 10 d . Furthermore, the gate electrodes are covered with an insulating film 17 . N-doping regions 18 a and 18 b are formed in a surface region of the p-type semiconductor substrate 2 in a self-aligning positional relationship with the gate electrodes. The n-doping regions 18 a and 18 b comprise a so-called LDD structure (Lightly Dopgd Drain = lightly doped drain), are formed within the doping regions of low concentration on the channel sides of the doping regions, and which a couple of source / drain regions of the transistor 14 form. The capacitor 15 is composed of a stacked structure of a lower electrode 19 , a dielectric film 20 and an upper electrode 21 . The lower Elektro de 19 consists of polycrystalline silicon (hereinafter referred to as polysilicon), in which impurities or dopants are introduced, and it extends over the gate electrode 10 b ( 10 c ) of the transistor gate 14 to the word line 10 a ( 10 d ) which runs over a field oxide film 22 , wherein an isolating film 17 lies between these layers. Furthermore, a portion of the lower electrodes 19 is connected to the doping region 18 b . The dielectric film 20 is formed on the lower electrode 19 and includes a two-layer structure of a silicon nitride film and an oxide film formed thereon. Furthermore, the upper electrode 21 consists of polysilicon, in which impurities or dopants are introduced. A so-called ge stacked capacitor 15 according to the above description, it extends over the gate electrode of the transfer gate transistor 14 and the field oxide film 22 , which contributes to the reduction of the required planar area of the substrate surface and thus to a higher integration. A first interlayer insulation film 23 is arranged on a surface as a capacitor 15 or the like. Furthermore, the bit lines 11 a and 11 b are formed on a surface of the first interlayer insulation film 23 . The bit lines 11 a and 11 b are connected to an n-doping region 18 a of the transfer gate transistor 14 through a contact hole 24 in the first interlayer insulation film 23 . A second interlayer insulation film 25 also lies over the bit lines 11 a and 11 b , auxiliary word lines 12 a , 12 b , 12 c and 12 d being formed on the surface thereof. This auxiliary word lines 12 a to 12 d are formed in such a mutual positional relationship that they overlap with the underlying word lines 10 a to 10 d in the same direction and are contacted with them in several areas of their longitudinal extent. The auxiliary word lines 12 a to 12 d supply voltages to the word lines 10 a to 10 d through these contact sections without delay and thus improve the voltage rise on the word lines.

Therefore, it is necessary that the auxiliary word lines 12 a to 12 d consist of materials of good conductivity and low resistance. For this reason, a connection structure with a three-layer structure according to the present invention is applied to these auxiliary word lines.

Referring to FIG. 3, a structure of the auxiliary is word line 12 a described. The auxiliary word line 12 a is contacted with the underlying word line 10 a on a pre-determined field oxide film 22 . The auxiliary word line 12 a comprises a three-layer stacked structure of a barrier metal layer 6 , an aluminum compound layer 7 and an anti-reflective coating 8 in this sequence from bottom to top. Meanwhile, the auxiliary word line 12 a in a contact portion with the word line 10 a has a four-layer stacked structure of a silicide layer 20 , a barrier metal layer 6 , an aluminum alloy layer 7 and an anti-reflection coating 8 in this order from bottom to top.

The silicide layer 20 is made of a high-melting metal silicide, such as titanium silicide (TiSi index 2). Titanium nitride (TiN) or tungsten silicide is used as the barrier metal layer 6 .

As the aluminum alloy layer 7 , any Al-Si alloy with approximately 0.5% silicon (Si) can be added to the aluminum, the Al-Si-Cu alloy also having a small amount of copper (Cu) added to this alloy. Similar substances can also be added.

Furthermore, any amorphous silicon, an Al-Si alloy with about 40 to 45% silicon added to aluminum, a high-melting metal, a high-melting metal silicide or the like can be used as the anti-reflection coating 8 .

The aluminum alloy layer 7 is formed with a thickness of 5000A to 10,000A and serves as a main connection with high conductivity due to the low resistance characteristics of the aluminum. Furthermore, the copper added to the aluminum has the effect of improving the resistance of the alloy to electrical migration or electrical particle migration. At the contact section with the connection layer, the silicon layer 20 brings about good ohmic contact with a conductive layer in the silicon substrate.

The barrier metal layer 6 is formed with a thickness of about 700A and prevents direct contact between the aluminum alloy layer 7 and the silicon layer at the contact portion to prevent the occurrence of an alloy peak phenomenon or the deposition of silicon nodules, thereby Contact resistance value would be reduced.

Furthermore, the anti-reflective coating 8 is formed to a thickness of approximately 300 A and prevents refraction of the exposure beams in the pattern structuring during photolithography to improve the resist pattern accuracy. Fig. 6 shows the reflectivity of the amorphous silicon. The data show the relative reflectivity of amorphous silicon when the reflectivity of Al-Si (1%, 10,000A thick) is assumed to be 100. It can be seen from this data that the reflectivity or reflectivity of amorphous silicon is low. The scattering of the exposure rays in the pattern production can be prevented by using amorphous silicon with low reflectivity. This improves the accuracy in the pattern structuring of the connecting layer 12 b , which is formed on a surface with protruding irregularities, in order to prevent thinning or interruption of the conductor of the connecting layer. As a result, a stable and miniaturized connection pattern is obtained. The combined functions of each layer contained in the three-layer structure enable the creation of an extremely reliable connection layer, which as a whole has a high conductivity, a low contact resistance and a stable connection pattern. Such a connection shows significant effects particularly when applied to such a connection layer with the above-mentioned auxiliary word lines 12 a , 12 b , which lie above the multilayered stacked connection layer, in order to achieve a fast switching behavior. Therefore, the application of such a connection layer to a DRAM creates an improvement in the memory cells, the response behavior or switching behavior and a reduced rejection rate during production due to the stabilized production process of the connection layer.

Although in the above embodiment, the connection layer according to the present invention on an auxiliary word line that is applied in a memory array of a DRAM is used, the invention is not limited to this limits, but can for example to one below lying bit line can be used. Likewise, it is possible to use the connection layers in a wide range application field of the semiconductor devices.

The following description relates to a method of manufacturing a connection layer in a semiconductor device according to the invention with reference to FIGS . 4A-4E.

As shown in Fig. 4 A, a contact hole 40 is formed in an insulating film 3 on the surface of a silicon substrate 2 to reach a doping region 1 which is formed in a surface region of the silicon substrate 2 . A titanium layer 30 a is then deposited within the contact hole 40 and deposited on a surface of the insulating film 3 by sputtering.

Second, as shown in Fig. 4B, a titanium nitride layer 30 b by nitriding the titanium layer 30 a in a nitrogen atmosphere by means of an RTP process (RTP = Rapid Thermal Process = rapid thermal process), in which a nitride reaction by rapid On heating with a powerful heating lamp. During this nitriding, a titanium silicide layer 20 is generated in a contact section between the titanium layer 30 a and the silicon substrate 2 (doping region 1 ) by reaction between the titanium and the silicon.

Furthermore, as shown in FIG. 4C, a titanium layer 30 a is again deposited on a surface of the titanium nitride layer 30 .

As shown next in Fig. 4D, the titanium layer 30 a is nitrided in nitrogen using the RTP. The titanium layer 30 a is converted into a titanium nitride layer by nitriding and forms a titanium nitride layer 30 of a predetermined thickness, which is combined with the underlying titanium nitride layer. This titanium nitride layer 30 forms a barrier metal layer.

As further shown in FIG. 4E, an Al-Si-Cu layer 31 having a thickness of 5000A-10,000A is formed on a surface of the titanium nitride layer 30 . An amorphous silicon layer 32 is in turn deposited on the upper surface of the Al-Si-Cu layer 31 by sputtering. Then, the amorphous silicon layer 32 , the Al-Si-Cu layer 31 and the titanium nitride layer 30 are patterned and etched by photolithography to produce a predetermined connection configuration. The amorphous silicon layer 32 is etched using a fluoride-based etching gas (eg CF index 4 + 0 index 2). The Al-Si-Cu layer 31 is etched using a chlorine-based etching gas (eg BCl Index 3 + Cl Index 2).

A connection layer is formed by the above process formed a three-layer structure from a titanium nitride layer, an Al-Si-Cu layer and an amorphous Identifies silicon layer in the connecting section, and a four-layer structure of one layer of titanium silicide, one  Titanium nitride layer, an Al-Si-Cu layer and one has amorphous silicon layer in the contact area.

As shown in Fig. 5, the top anti-reflective coating (amorphous silicon layer) 32 can be removed after patterning the connection layer. Although in this case the amorphous silicon layer 32 is removed using a fluorine-based etching gas, etching of the underlying Al-Si-Cu layer 31 is prevented because the etch selectivity of this layer is greater for the etching gas than that of the amorphous silicon layer . Therefore, the underlying Al-Si-Cu layer 31 cannot be damaged when the amorphous silicon layer 32 is removed by etching.

Further, if Al-Si (45%) is used as the anti-reflective coating, it cannot be removed by etching without damaging the underlying Al-Si-Cu layer 31 because the Al-Si (45%) layer and the Al-Si-Cu layer 31 are both etched, for example, by a chlorine-based etching gas. When the intermediate layer heats up during operation of the semiconductor device, a significant amount of the Al-Si (45%) layer above it penetrates into the Al-Si-Cu layer 31 and is deposited therein. As a result, the resistance of the Al-Si-Cu layer 31 to electro-migration or electric particle migration is reduced. On the other hand, if amorphous silicon is used as the anti-reflection coating, it is possible to remove the amorphous silicon only by etching without damaging the Al-Si-Cu layer 31 in any form, so that there is no decrease in the resistance to electro-migration due to the characteristics of the anti-reflective coating.

Therefore, the connection structure includes a semiconductor device according to the present invention a three layered stacked structure in the connection section, the top layer being an anti-reflective coating  is. The anti-reflective coating prevents one Refraction of exposure rays in the pattern structure generation in the connection layer by photolithography. As a result, a miniaturized connection pattern be preserved. The connection structure further includes one four-layer structure in the contact area, two there underlying layers one silicide layer and one Barrier metal layer are from bottom to top. The sili Zidschicht allows a good ohmic contact between a conductive silicon layer and the connection layer. The barrier metal layer prevents discharge formation of silicon nodules between these layers as well the creation of an alloy tip phenomenon so that the Contact characteristics of the connection structure improved becomes. Therefore, the compound layer shows a semiconductor device with the connection structure according to the present the invention improved reliability.

Claims (8)

1. A semiconductor device with a multilayer stacked connection layer, characterized in that the connection layer has the following features:
A connection portion extending over an insulating layer ( 3 ) formed on a main surface of a semiconductor substrate ( 22 ); and
a contact portion connected to a predetermined conductive silicon layer ( 102 ) included in the semiconductor device;
wherein the connection portion of the connection layer has a barrier metal layer ( 6 ), a metal layer ( 7 ) with aluminum and an anti-reflective coating ( 8 ) in this order starting from the surface side of the insulating layer, and
wherein the contact portion of the connection layers comprises a silicide layer ( 20 ), a barrier metal layer ( 6 ),
has a metal layer ( 7 ) with aluminum and an anti-reflection coating ( 8 ) in this order from the surface side of the conductive silicon layer. 2. Semiconductor device according to claim 1, characterized in that the anti-reflection coating ( 8 ) consists of amorphous silicon. 3. Semiconductor device according to claim 1 or 2, characterized in that the barrier metal layer ( 6 ) consists of titanium nitride. 4. Semiconductor device with a multilayer stacked connection layer, characterized in that the connection layer has the following features:
a barrier metal layer ( 30 ) formed on a surface of an insulating film ( 3 ) formed on a main surface of a semiconductor substrate ( 2 );
a metal layer ( 31 ) containing aluminum and formed on a surface of the barrier metal layer ( 30 );
an amorphous silicon layer ( 32 ) formed on the upper surface of the metal layer. 5. Semiconductor device according to claim 4, characterized in that the barrier metal layer ( 30 ) consists of Ti tannitrid. 6. A method of manufacturing a semiconductor device having a multilayer stacked interconnection layer which extends over an insulating layer formed on a surface of a conductive silicon layer and which is connected to a surface of the conductive silicon layer through a contact hole which is in the insulating Layer is formed to reach the surface of the conductive silicon layer, characterized by the following process steps:
Creating a barrier metal layer ( 30 ) on the upper surface of the conductive silicon layer ( 1 ), which is open in the contact hole ( 40 ), and on a surface of the insulating layer ( 3 );
Creating a metal layer ( 31 ) containing aluminum on a surface of the barrier metal layer;
Creating an anti-reflective coating ( 32 ) on the surface of the metal layer;
Creating a mask with a predetermined connection pattern on the anti-reflective coating by the photolithography;
Patterning the anti-reflective coating, the metal layer and the barrier metal layer to create a predetermined configuration using the mask;
Remove the structured anti-reflective coating. 7. A method for producing a semiconductor device according to claim 6, characterized in that the procedural step for producing the anti-reflection coating device ( 32 ) has a process step of depositing amorphous silicon ( 32 ) on a surface of the metal layer by means of sputtering. 8. A method for producing a semiconductor device according to claim 6 or 7, characterized in that the step of producing the barrier metal layer ( 30 ), which consists of high-melting metal nitride, comprises the following steps:
Generating a first high-melting metal layer ( 30 a ) on the surface of the conductive silicon layer ( 1 ), which is open in the contact hole ( 40 ), and on the surface of the insulating layer ( 3 );
Creating a first refractory metal nitride layer ( 30 ) by nitriding the first refractory metal layer using high temperature, and simultaneously forming a refractory metal silicide layer ( 20 ) by silicide treatment of the first refractory metal layer in contact with the surface of the conductive silicon layer;
Generating a second refractory metal layer ( 30 a ) on the surface of the refractory metal nitride layer;
Generate a second high-melting metal nitride layer ( 30 ) by nitriding the second high-melting metal layer.