JP3280803B2 - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereofInfo
- Publication number
- JP3280803B2 JP3280803B2 JP19401694A JP19401694A JP3280803B2 JP 3280803 B2 JP3280803 B2 JP 3280803B2 JP 19401694 A JP19401694 A JP 19401694A JP 19401694 A JP19401694 A JP 19401694A JP 3280803 B2 JP3280803 B2 JP 3280803B2
- Authority
- JP
- Japan
- Prior art keywords
- titanium nitride
- film
- titanium
- layer
- tin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53214—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being aluminium
- H01L23/53223—Additional layers associated with aluminium layers, e.g. adhesion, barrier, cladding layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
- H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
- Y10S257/915—Active solid-state devices, e.g. transistors, solid-state diodes with titanium nitride portion or region
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
Description
【0001】[0001]
【産業上の利用分野】本発明は半導体装置及びその製造
方法に関し、特にバリアメタルを介してシリコン基板に
金属配線を形成する方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a method of forming a metal wiring on a silicon substrate via a barrier metal.
【0002】[0002]
【従来の技術】コンタクト部におけるシリコン(Si)
基板に形成された不純物拡散層と、シリコン(Si)基
板上に形成する金属配線とのオーミック接続する際、金
属配線とシリコン(Si)との反応を防止するためにバ
リアメタルの中間層が用いられる。バリアメタルとして
はチタン(Ti)と窒化チタン(TiN)が一般的に良
く用いられる。2. Description of the Related Art Silicon (Si) in a contact portion
When forming an ohmic connection between the impurity diffusion layer formed on the substrate and the metal wiring formed on the silicon (Si) substrate, an intermediate layer of a barrier metal is used to prevent a reaction between the metal wiring and silicon (Si). Can be As the barrier metal, titanium (Ti) and titanium nitride (TiN) are commonly used.
【0003】層間絶縁膜に開口したコンタクト孔でのシ
リコン(Si)基板とタングステン(W)配線との接続
方法では、シリコン(Si)基板に形成された不純物拡
散層上に層間絶縁膜を形成し、その層間絶縁膜にコンタ
クト孔を開口し、基板表面にチタン(Ti)膜と窒化チ
タン(TiN)膜をバリアメタルとして順次形成し、窒
化チタン(TiN)膜をアニールするための熱処理をお
こなう。そしてタングステン(W)膜を堆積形成し、次
いで、第2の層間絶縁膜を形成し、ガラスフロー等の熱
処理をおこない、第2の層間絶縁膜に第2のコンタクト
孔を開口し、最後にアルミニウム(Al)膜を堆積しコ
ンタクト部の金属配線接続が完成する。従来、バリアメ
タルとして用いられている窒化チタン(TiN)膜は、
一般にチタン(Ti)をターゲット電極としたAr+N
2 雰囲気中での反応性スパッタ法により形成され、また
チタン(Ti)膜のN2あるいはNH3 雰囲気中でのラ
ンプアニール(RTN)によっても形成されていた。そ
して、その後のアニールを経て窒化チタン(TiN)膜
の結晶完全化がおこなわれる。In a method of connecting a silicon (Si) substrate and a tungsten (W) wiring through a contact hole opened in an interlayer insulating film, an interlayer insulating film is formed on an impurity diffusion layer formed on a silicon (Si) substrate. Then, a contact hole is opened in the interlayer insulating film, a titanium (Ti) film and a titanium nitride (TiN) film are sequentially formed on the substrate surface as barrier metals, and heat treatment for annealing the titanium nitride (TiN) film is performed. Then, a tungsten (W) film is deposited and formed, then a second interlayer insulating film is formed, a heat treatment such as a glass flow is performed, a second contact hole is opened in the second interlayer insulating film, and finally aluminum is formed. An (Al) film is deposited to complete the metal wiring connection at the contact portion. Conventionally, a titanium nitride (TiN) film used as a barrier metal is:
Generally, Ar + N using titanium (Ti) as a target electrode
It was formed by a reactive sputtering method in a 2 atmosphere and also by lamp annealing (RTN) of a titanium (Ti) film in an N2 or NH3 atmosphere. After the subsequent annealing, the crystal perfection of the titanium nitride (TiN) film is performed.
【0004】[0004]
【発明が解決しようとする課題】しかしながら、上述し
た半導体装置及びその製造装置では、窒化チタン(Ti
N)膜形成後の熱処理による結晶完全化の際、窒化チタ
ン(TiN)膜の収縮が起こり窒化チタン(TiN)膜
に微細なクラックが発生する。このため窒化チタン(T
iN)膜のバリア性が低下しコンタクト部でのリーク電
流が多くなる。また、タングステン(W)膜堆積後にガ
ラスフロー等の高温アニールが加わると、シリコン(S
i)基板のシリコン(Si)原子が窒化チタン(Ti
N)膜を透過して、タングステン(W)層と反応しタン
グステンシリサイド(WSix)層を生成するためコンタ
クト部の抵抗が増大する。However, in the above-described semiconductor device and its manufacturing apparatus, titanium nitride (Ti
N) During crystal perfection by heat treatment after film formation, the titanium nitride (TiN) film shrinks and fine cracks occur in the titanium nitride (TiN) film. For this reason, titanium nitride (T
The barrier property of the iN) film is reduced, and the leak current at the contact portion is increased. When a high-temperature annealing such as a glass flow is applied after the tungsten (W) film is deposited, silicon (S)
i) The silicon (Si) atoms of the substrate are titanium nitride (Ti)
N), which penetrates the film and reacts with the tungsten (W) layer to generate a tungsten silicide (WSix) layer, thereby increasing the resistance of the contact portion.
【0005】[0005]
【課題を解決するための手段】本発明は、層間絶縁膜を
形成されたコンタクト構造において、シリコン(Si)
基板に設けられた不純物拡散上に、チタンシリサイド
(TiSix)層と複数の窒化チタン(TiN)層を設
け、複数の窒化チタン(TiN)層を[111]より
[200]にて結晶配向が強くなるように構成したもの
である。According to the present invention, there is provided a contact structure having an interlayer insulating film formed thereon.
On the impurity diffusion provided on the substrate, a titanium silicide (TiSix) layer and a plurality of titanium nitride (TiN) layer is provided, a strong crystal orientation in the [200] from a plurality of titanium nitride (TiN) layer [111] those configured such that.
【0006】[0006]
【作用】本発明は、前記構成により、高温アニールによ
ってもコンクタクト部のリーク電流の少ない、さらにコ
ンタクト抵抗の増大のない、高信頼性のオーミックコン
タクトの形成が可能となる。According to the present invention, it is possible to form a highly reliable ohmic contact having a small leak current in a contact portion and no increase in contact resistance even by high-temperature annealing.
【0007】[0007]
【実施例】図1は本発明の実施例を示すコンタクト部の
断面図である。図1において、シリコン(Si)基板1
上にCVD酸化(SiO2)膜やリンガラス(PSG)膜
等からなる第1の層間絶縁膜2を堆積した後、パターニ
ングし第1のコンタクト孔9を形成する。次に、第1の
コンタクト 孔9のシリコン(Si)基板1に不純物拡
散を行い不純物拡散層3を形成する。そして、スパッタ
リング法によりチタン(Ti)膜4を10乃至30nm
堆積する。FIG. 1 is a sectional view of a contact portion showing an embodiment of the present invention. In FIG. 1, a silicon (Si) substrate 1
A first interlayer insulating film 2 made of a CVD oxide (SiO2) film, a phosphor glass (PSG) film, or the like is deposited thereon, and then patterned to form a first contact hole 9. Next, impurity diffusion is performed on the silicon (Si) substrate 1 in the first contact hole 9 to form an impurity diffusion layer 3. Then, a titanium (Ti) film 4 is formed to a thickness of 10 to 30 nm by a sputtering method.
accumulate.
【0008】次に、800乃至900℃のN2雰囲気中
でランプアニール(RTN)を行い、チタン(Ti)膜
4を16乃至48nm程度のチタンシリサイド(TiS
ix)層5と2nm程度の第1の窒化チタン(TiN)
膜6に変成し、その上に反応性スパッタリング法により
第2の窒化チタン(TiN)膜7を30乃至100nm
堆積する。反応性スパッタリング条件は、N2ガス10
0%、ガス圧力4mmTorr、パワー6KWである。
この時の反応性スパッタリング法により形成された窒化
チタン(TiN)膜の結晶配向は[200]主体となる
傾向、即ち[111]より[200]にて結晶配向が強
くなる傾向があり、文献Solid State Devices and Mate
rials,Tokyo,1988,pp.569-572でも報告されている通り
である。さらに、CVD法にてタングステン(W)膜8
を200乃至400nm堆積し、パターニングを行いタ
ングステン(W)膜8、第2の窒化チタン(TiN)膜
7、第1の窒化チタン(TiN)膜6、チタン(Ti)
膜4を順次エッチングする。Next, lamp annealing (RTN) is performed in an N2 atmosphere at 800 to 900 ° C. to convert the titanium (Ti) film 4 to titanium silicide (TiS) of about 16 to 48 nm.
ix) Layer 5 and about 2 nm of first titanium nitride (TiN)
The film 6 is transformed into a film 6 and a second titanium nitride (TiN) film 7 is formed thereon by a reactive sputtering method in a thickness of 30 to 100 nm.
accumulate. The reactive sputtering condition is N2 gas 10
0%, gas pressure 4 mmTorr, power 6 KW.
At this time, the crystal orientation of the titanium nitride (TiN) film formed by the reactive sputtering method tends to be mainly [200], that is, the crystal orientation is stronger at [200] than at [111].
There is a tendency Kunar, literature Solid State Devices and Mate
rials, Tokyo, 1988, pp. 569-572. Further, a tungsten (W) film 8 is formed by CVD.
Is deposited to a thickness of 200 to 400 nm and patterned to form a tungsten (W) film 8, a second titanium nitride (TiN) film 7, a first titanium nitride (TiN) film 6, and titanium (Ti).
The film 4 is sequentially etched.
【0009】次に、図示はしないが、酸化シリコン(S
iO2)やリンガラス(PSG)等の第2の層間絶縁膜
を堆積し、850乃至950℃程度のガラスフローを行
ない、パターニングし第2のコンタクト孔を第2の層間
絶縁膜に開口し、アルミニウム(Al)膜を堆積する。Next, although not shown, silicon oxide (S
io2) and the second interlayer insulating film of phosphorus glass (PSG) or the like was deposited, the row of glass flow of about 850 to 950 ° C.
There Do, patterning and opening a second contact hole in the second interlayer insulating film, depositing aluminum (Al) film.
【0010】図2に、本実施例におけるコンタクト部の
シート抵抗のアニール温度依存性を示した。図から明ら
かなように従来の装置あるいは方法では達成できなかっ
た、850乃至950℃における高温アニールにおいて
も、コンタクト抵抗の顕著な増加はみられず、窒化チタ
ン(TiN)膜のバリア性が維持されていることがわか
る。[0010] Figure 2 shows the annealing temperature dependency of the sheet resistance of the contact portion of definitive to this embodiment. As is clear from the figure, even in the high-temperature annealing at 850 to 950 ° C., which could not be achieved by the conventional apparatus or method, no remarkable increase in the contact resistance was observed, and the barrier property of the titanium nitride (TiN) film was maintained. You can see that it is.
【0011】この現象は、窒化チタン(TiN)膜の結
晶性に依るものと考えられる。従来一般に広く用いられ
ている窒化チタン(TiN)膜は、周知であるように
[111]に結晶配向した、図3の模式図に示されたよ
うな柱状結晶である。柱状であるが故に熱処理の際の結
晶完全化により応力が集中し、クラックが発生し易い。
さらに、柱状の粒界のため原子が粒界拡散を起こして窒
化チタン(TiN)膜を透過し易くなる。この場合、シ
リコン(Si)基板より供給されたシリコン(Si)原
子は、窒化チタン(TiN)膜を透過しタングステン
(W)膜と反応し、チタンシリサイド(TiSix)膜
となりコンタクト部の抵抗が増加していたものと考えら
れる。This phenomenon is considered to be due to the crystallinity of the titanium nitride (TiN) film. Conventionally and widely used titanium nitride (TiN) films are columnar crystals having a crystal orientation of [111] as shown in the schematic diagram of FIG. 3, as is well known. Due to the columnar shape, stress is concentrated due to crystal perfection during heat treatment, and cracks are likely to occur.
In addition, the columnar grain boundaries cause atoms to diffuse into the grain boundaries, making it easier to permeate the titanium nitride (TiN) film. In this case, silicon (Si) atoms supplied from the silicon (Si) substrate penetrate the titanium nitride (TiN) film and react with the tungsten (W) film to become a titanium silicide (TiSix) film, and the resistance of the contact portion increases. It is thought that it was.
【0012】図4に本実施例におけるチタンシリサイド
(TiSix)膜と第1及び第2の窒化チタン(Ti
N)膜の試料のアニール後のX線回折の強度を示す。図
から明らかなように、積層した窒化チタン(TiN)膜
の結晶配向性は、第1の窒化チタン(TiN)膜を形成
するためのチタン(Ti)膜のランプアニール(RT
N)温度に依存していることが理解できる。700℃の
ランプアニール(RTN)では、[111]主体に結晶
配向しているが、800℃以上のランプアニール(RT
N)では、[200]に強く結晶配向した膜となってい
ることが分かる。本実施例は、800℃以上の高温のラ
ンプアニールを施すことにより第1の窒化チタン(Ti
N)膜を[111]より[200]にて結晶配向を強く
し、そして、第1の窒化チタン(TiN)膜を種結晶と
して、従来[200]に結晶配向し易いと考えられる生
成条件により第2の窒化チタン(TiN)膜を形成し、
[200]への結晶配向性が得られたものと推察でき
る。FIG. 4 shows a titanium silicide (TiSix) film and first and second titanium nitrides (Ti
N) X-ray diffraction intensity of the film sample after annealing is shown. As apparent from the figure, the crystal orientation of the laminated titanium nitride (TiN) film is determined by lamp annealing (RT) of the titanium (Ti) film for forming the first titanium nitride (TiN) film.
N) It can be seen that it depends on the temperature. In the lamp annealing (RTN) at 700 ° C., the crystal orientation is mainly of [111], but the lamp annealing (RTN) at 800 ° C. or more is performed.
In (N), it can be seen that the film was strongly oriented in [200]. In the present embodiment, the first titanium nitride (Ti
N) The crystal orientation is stronger at [200] than at [111].
And, then, the first titanium nitride (TiN) film as a seed crystal, a conventional [200] in the generation conditions that could be easily crystal orientation to form a second titanium nitride (TiN) film,
It can be inferred that crystal orientation to [200] was obtained.
【0013】結晶配向した窒化チタン(TiN)膜の構
造は、図5の模式図で示したように粒状結晶である。熱
処理の際、結晶完全化が起こっても応力が散漫し、クラ
ックが発生しにくい。また、粒状の粒界であるため、粒
界拡散がたとえ起こったとしてもシリコン(Si)基板
より供給されたシリコン(Si)原子が、窒化チタン
(TiN)膜を透過する確率は極めて低いと思われる。
以上の理由によりコンタクト部のリーク電流の発生も少
なく、タングステン(W)膜とのシリサイド反応も起こ
らず、コンタクト部の抵抗増加もあまり見られなかった
と考えられる。[0013] structure of the crystal oriented titanium nitride (TiN) film is a granular crystals as shown in the schematic diagram of FIG. During the heat treatment, stress is diffused even when crystal perfection occurs, and cracks are unlikely to occur. Further, since the grain boundary is a grain boundary, even if the grain boundary diffusion occurs, the probability that silicon (Si) atoms supplied from the silicon (Si) substrate permeate the titanium nitride (TiN) film seems to be extremely low. It is.
For the above reasons, it is considered that the occurrence of leakage current in the contact portion was small, the silicide reaction with the tungsten (W) film did not occur, and the resistance in the contact portion did not increase much.
【0014】[0014]
【発明の効果】以上説明したように本発明は、積層した
窒化チタン(TiN)膜の結晶配向性を[111]より
[200]にて強くするように構成したために、後の高
温の熱処理においても積層した窒化チタン(TiN)膜
のバリア性の劣化を防止することが可能となった。した
がって、コンタクト部における接合リーク不良の発生及
びコンタクト抵抗不良の発生が抑制され、高信頼性の半
導体装置及びその製造方法を実現することができた。As described above, according to the present invention, the crystal orientation of the laminated titanium nitride (TiN) film is determined from [111].
Since the structure is strengthened in [200], it is possible to prevent the barrier property of the laminated titanium nitride (TiN) film from deteriorating even in the subsequent high-temperature heat treatment. Therefore, the occurrence of junction leak failure and the occurrence of contact resistance failure in the contact portion are suppressed, and a highly reliable semiconductor device and a method of manufacturing the same can be realized.
【図1】本発明の実施例を説明するための半導体装置の
断面図である。FIG. 1 is a cross-sectional view of a semiconductor device for explaining an embodiment of the present invention.
【図2】コンタクト部におけるタングステン膜のシート
抵抗のアニール温度依存性を示す図である。FIG. 2 is a diagram showing the annealing temperature dependence of the sheet resistance of a tungsten film in a contact portion.
【図3】[111]に結晶配向した窒化チタン(Ti
N)膜の柱状結晶の模式図である。FIG. 3. Titanium nitride (Ti)
(N) It is a schematic diagram of a columnar crystal of a film.
【図4】本発明の実施例におけるチタンシリサイド(T
iSix)膜と第1及び第2の窒化チタン(TiN)膜
を積層した試料のアニール後におけるX線回折の強度を
示す図である。FIG. 4 shows a titanium silicide (T) according to an embodiment of the present invention.
FIG. 6 is a diagram showing the intensity of X-ray diffraction after annealing of a sample in which an iSix) film and first and second titanium nitride (TiN) films are stacked.
【図5】[200]に結晶配向した窒化チタン(Ti
N)膜の粒状結晶の模式図である。FIG. 5: Titanium nitride (Ti
(N) It is a schematic diagram of a granular crystal of a film.
1 シリコン基板 2 第1の層間絶縁膜 3 不純物拡散層 4 チタン膜 5 チタンシリサイド膜 6 第1の窒化チタン膜 7 第2の窒化チタン膜 8 タングステン膜 9 第1のコンタクト孔 Reference Signs List 1 silicon substrate 2 first interlayer insulating film 3 impurity diffusion layer 4 titanium film 5 titanium silicide film 6 first titanium nitride film 7 second titanium nitride film 8 tungsten film 9 first contact hole
───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 平2−119129(JP,A) 特開 平7−201779(JP,A) 特開 平7−45554(JP,A) 特開 平7−45553(JP,A) 特開 平6−260445(JP,A) 特開 平6−204170(JP,A) 特開 平6−151815(JP,A) 特開 平6−97112(JP,A) 特開 平6−20997(JP,A) 特開 平5−190493(JP,A) 特開 平4−112529(JP,A) 特開 平1−231318(JP,A) 特表 平9−500175(JP,A) (58)調査した分野(Int.Cl.7,DB名) H01L 21/285 301 H01L 21/768 ────────────────────────────────────────────────── ─── Continuation of front page (56) References JP-A-2-119129 (JP, A) JP-A-7-201779 (JP, A) JP-A-7-45554 (JP, A) JP-A-7-2017 45553 (JP, A) JP-A-6-260445 (JP, A) JP-A-6-204170 (JP, A) JP-A-6-151815 (JP, A) JP-A-6-97112 (JP, A) JP-A-6-20997 (JP, A) JP-A-5-190493 (JP, A) JP-A-4-112529 (JP, A) JP-A-1-231318 (JP, A) Table 9-500175 (JP, A) (58) Field surveyed (Int. Cl. 7 , DB name) H01L 21/285 301 H01L 21/768
Claims (4)
と金属配線のオーミックコンタクトを有する半導体装置
に於て、 該不純物拡散層とオーミック接触をすべき部分にチタン
シリサイド層を有し、該チタンシリサイド層上に複数の
窒化チタン層が形成され、前記複数の窒化チタン層は
[111]より[200]にて結晶配向が強いことを特
徴とする半導体装置。1. An impurity diffusion layer formed on a silicon substrate.
Device having ohmic contact between metal and metal wiring
In the step of forming an ohmic contact with the impurity diffusion layer,
Having a silicide layer,TheMultiple layers on the titanium silicide layer
A titanium nitride layer is formed,PreviousThe plurality of titanium nitride layersIs
Crystal orientation from [111] to [200]Is strongSpecially
Semiconductor device.
層と金属配線のオーミックコンタクトを有する半導体装
置の製造方法に於て、 上記拡散層上に存在する層間絶縁膜にコンタクト孔を開
口する工程と、 該コンタクト孔にチタン層を形成する工程と、[111]より[200]にて結晶配向が強くなる温度
での 熱処理により該チタン層の表面部を第1の窒化チタ
ン層に変え、該第1の窒化チタン層を[111]より
[200]にて結晶配向を強くさせる工程と、 該第1の窒化チタン層上に[111]より[200]に
て結晶配向を強くした第2の窒化チタン層を形成する工
程とを少なくとも備えたことを特徴とする半導体装置の
製造方法。2. A method of manufacturing a semiconductor device having an ohmic contact between an impurity diffusion layer formed on a silicon substrate and a metal wiring, comprising the steps of: opening a contact hole in an interlayer insulating film existing on the diffusion layer; Forming a titanium layer in the contact hole; and a temperature at which the crystal orientation becomes stronger from [111] to [200].
Heat treatment changes the surface portion of the titanium layer on the first titanium nitride layer by at, from the titanium nitride layer of the first [111]
A step of strengthening the crystal orientation in [200] , and changing from [111] to [200] on the first titanium nitride layer .
Forming a second titanium nitride layer whose crystal orientation is strengthened by performing the method.
あるいはアンモニア雰囲気のランプアニールであること
を特徴とする請求項2記載の半導体装置の製造方法。3. The method for producing a pre-Symbol heat treatment device according to claim 2, wherein it is a lamp annealing a nitrogen or ammonia atmosphere at 800 to 900 ° C..
に、850乃至900℃で熱処理する工程を含むことをFurther comprising a step of heat treatment at 850 to 900 ° C.
特徴とする請求項2又は3記載の半導体装置の製造方4. A method of manufacturing a semiconductor device according to claim 2, wherein
法。Law.
Priority Applications (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP19401694A JP3280803B2 (en) | 1994-08-18 | 1994-08-18 | Semiconductor device and manufacturing method thereof |
US08/493,581 US5654235A (en) | 1994-08-18 | 1995-06-22 | Method of manufacturing contact structure using barrier metal |
DE69522397T DE69522397T2 (en) | 1994-08-18 | 1995-06-23 | Contact structure with metallic barrier layer and manufacturing process |
EP95304445A EP0697729B1 (en) | 1994-08-18 | 1995-06-23 | Contact structure using barrier metal and method of manufacturing the same |
KR1019950024998A KR100269439B1 (en) | 1994-08-18 | 1995-08-14 | Semiconductor device and fabricating method thereof |
US08/835,060 US5920122A (en) | 1994-08-18 | 1997-04-03 | Contact structure using barrier metal and method of manufacturing the same |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP19401694A JP3280803B2 (en) | 1994-08-18 | 1994-08-18 | Semiconductor device and manufacturing method thereof |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH0864555A JPH0864555A (en) | 1996-03-08 |
JP3280803B2 true JP3280803B2 (en) | 2002-05-13 |
Family
ID=16317550
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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JP19401694A Expired - Fee Related JP3280803B2 (en) | 1994-08-18 | 1994-08-18 | Semiconductor device and manufacturing method thereof |
Country Status (5)
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---|---|
US (2) | US5654235A (en) |
EP (1) | EP0697729B1 (en) |
JP (1) | JP3280803B2 (en) |
KR (1) | KR100269439B1 (en) |
DE (1) | DE69522397T2 (en) |
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-
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-
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- 1995-06-23 EP EP95304445A patent/EP0697729B1/en not_active Expired - Lifetime
- 1995-06-23 DE DE69522397T patent/DE69522397T2/en not_active Expired - Fee Related
- 1995-08-14 KR KR1019950024998A patent/KR100269439B1/en not_active IP Right Cessation
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1997
- 1997-04-03 US US08/835,060 patent/US5920122A/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
DE69522397D1 (en) | 2001-10-04 |
US5654235A (en) | 1997-08-05 |
EP0697729A3 (en) | 1996-11-13 |
EP0697729A2 (en) | 1996-02-21 |
KR960009110A (en) | 1996-03-22 |
EP0697729B1 (en) | 2001-08-29 |
JPH0864555A (en) | 1996-03-08 |
US5920122A (en) | 1999-07-06 |
KR100269439B1 (en) | 2000-10-16 |
DE69522397T2 (en) | 2002-05-23 |
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