KR100290467B1 - Method of forming a metal barrier film in a semiconductor device - Google Patents

Method of forming a metal barrier film in a semiconductor device Download PDF

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KR100290467B1
KR100290467B1 KR1019970081150A KR19970081150A KR100290467B1 KR 100290467 B1 KR100290467 B1 KR 100290467B1 KR 1019970081150 A KR1019970081150 A KR 1019970081150A KR 19970081150 A KR19970081150 A KR 19970081150A KR 100290467 B1 KR100290467 B1 KR 100290467B1
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layer
titanium
titanium nitride
forming
nitride layer
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KR1019970081150A
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KR19990060904A (en
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홍상기
김우현
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박종섭
현대전자산업주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76855—After-treatment introducing at least one additional element into the layer
    • H01L21/76856—After-treatment introducing at least one additional element into the layer by treatment in plasmas or gaseous environments, e.g. nitriding a refractory metal liner
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76846—Layer combinations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
    • H01L21/76889—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances by forming silicides of refractory metals

Abstract

PURPOSE: A method for forming diffusion barrier layer of semiconductor device is provided to maximize a diffusion protection effect by using an RTN(Rapid Thermal Nitridation). CONSTITUTION: After forming an interlayer dielectric(22) on a silicon substrate(21), a contact hole(29) is formed by selectively etching the interlayer dielectric so as to expose the silicon substrate. A first titanium nitride and a titanium layers(23,24) are sequentially formed on the entire surface of the resultant structure. By performing RTN contained nitrogen gases, the titanium layer(24) is transformed to a second titanium nitride layer(24A), a titanium oxide layer(26) is formed between the first and second titanium nitride layers(23,24A), and the first titanium nitride layer formed at the bottom portion of the contact hole, is transformed to a titanium silicide(25).

Description

반도체 소자의 확산 방지막 형성 방법{Method of forming a metal barrier film in a semiconductor device}Method of forming a diffusion barrier in a semiconductor device {Method of forming a metal barrier film in a semiconductor device}

본 발명은 반도체 소자의 확산 방지막(metal barrier film) 형성 방법에 관한 것으로, 특히 콘택 저항을 감소시키며 확산 방지 효과를 증대시킬 수 있는 반도체 소자의 확산 방지막 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a metal barrier film of a semiconductor device, and more particularly, to a method of forming a diffusion barrier of a semiconductor device capable of reducing contact resistance and increasing diffusion prevention effect.

일반적으로, 반도체 소자가 고집적화 됨에 따라 콘택홀의 크기는 줄어들고 있다. 이에 따라 금속 콘택 공정시 콘택홀을 양호하게 매립하기 어렵고, 또한 콘택 저항이 증가되어 소자의 전기적 특성을 저하시키게 된다. 이를 해결하기 위하여, 티타늄(Ti)과 티타늄 나이트라이드(TiN)를 증착한 후 열처리하여 콘택홀 기저부에 티타늄 실리사이드(TiSi2)를 갖는 확산 방지막을 형성한다.In general, as semiconductor devices are highly integrated, the size of contact holes is decreasing. As a result, it is difficult to bury the contact hole well in the metal contact process, and the contact resistance is increased to lower the electrical characteristics of the device. In order to solve this problem, titanium (Ti) and titanium nitride (TiN) are deposited and heat-treated to form a diffusion barrier layer having titanium silicide (TiSi 2 ) at the bottom of the contact hole.

종래의 반도체 소자의 확산 방지막 형성 방법을 도 1(a) 내지 1(c)를 참조하여 설명하면 다음과 같다.A method of forming a diffusion barrier film of a conventional semiconductor device will be described below with reference to FIGS. 1A to 1C.

도 1(a)를 참조하면, 실리콘 기판(11) 상부에 형성된 층간 절연막(12)의 선택된 영역이 식각되어 실리콘 기판(11)의 소정 영역을 노출시키는 콘택홀(19)이 형성된다. 콘택홀(19)을 포함한 전체 구조 상부에 스퍼터링(sputtering) 방식으로 티타늄층(13) 및 티타늄 나이트라이드층(14)이 순차적으로 형성된다.Referring to FIG. 1A, a selected region of the interlayer insulating layer 12 formed on the silicon substrate 11 is etched to form a contact hole 19 exposing a predetermined region of the silicon substrate 11. The titanium layer 13 and the titanium nitride layer 14 are sequentially formed on the entire structure including the contact hole 19 by sputtering.

도 1(b)를 참조하면, 질소(N2) 또는 암모늄(NH3) 가스 분위기에서 급속 열처리(Rapid Thermal Process; RTP) 공정을 실시하여 콘택홀(19) 기저부의 티타늄층(13)이 티타늄 실리사이드층(15)으로 변형되게 한다. 티타늄 실리사이드층(15)은 급속 열처리 공정 동안에 실리콘 기판(11)의 실리콘 원자(Si)와 티타늄층(13)의 티타늄 원자(Ti)가 상호 반응하여 형성된다.Referring to FIG. 1 (b), the titanium layer 13 at the base of the contact hole 19 is formed by performing a rapid thermal process (RTP) process in a nitrogen (N 2 ) or ammonium (NH 3 ) gas atmosphere. To be deformed into the silicide layer 15. The titanium silicide layer 15 is formed by reacting silicon atoms Si of the silicon substrate 11 and titanium atoms Ti of the titanium layer 13 during the rapid heat treatment process.

이와 같이 티타늄층(13) 및 티타늄 나이트라이드층(14)을 순차적으로 형성한 후 급속 열처리 공정을 실시하여 확산 방지막이 형성되고, 이후 도 1(c)에 도시된 바와 같이, 텅스텐층(17)을 화학 기상 증착(Chemical Vapor Deposition; CVD) 방식으로 형성한 후 패터닝하여 금속 배선이 형성된다.As described above, the titanium layer 13 and the titanium nitride layer 14 are sequentially formed, and then a rapid heat treatment process is performed to form a diffusion barrier layer. Then, as shown in FIG. 1C, the tungsten layer 17 is formed. Is formed by Chemical Vapor Deposition (CVD) and then patterned to form a metal interconnect.

도 1(c)의 콘택홀 기저부를 확대한 도 2에 도시된 바와 같이, 티타늄 나이트라이드층(14)은 원주형(columnar) 구조로 형성된다. 티타늄층(13)은 그 두께가 두꺼울 경우 급속 열처리에 의해 균일한 티타늄 실리사이드층을 형성할 수 있으나, 반도체 소자가 고집적화 되어감에 따라 콘택홀 크기가 줄어들어 종횡비(aspect ratio)가 크게되기 때문에 스퍼터링 방식으로 형성되는 티타늄층(13)의층덮힘(step coverage)이 나쁘게 되므로 티타늄층(13)을 두껍게 형성하는데 한계가 있다. 티타늄층(13)을 두껍게 형성하기 위하여, 층덮힘이 우수한 CVD 방식을 적용하고 있으나, CVD 방식을 적용할 경우 박막에 불순물 함유량이 높아지는 등 많은 공정상의 문제점이 존재하므로 현재로서는 실질 공정에 적용하기 어려운 실정이다. 따라서, 텅스텐층(13)은 스퍼터링 방식으로 형성되며, 텅스텐층(13)의 두께가 임계 두께 이하일 경우 급속 열처리로 형성되는 티타늄 실리사이드층(15)은, 도 2에 도시된 바와 같이, 균일한 두께로 형성되지 못한다. 이와 같이 티타늄 나이트라이드층(14)이 원주형 구조를 갖고, 티타늄 실리사이드층(15)이 불균일하게 형성된 상태에서 WF6가스를 이용하여 텅스텐층(17)을 형성할 경우, 형성 공정중에 원주형 구조의 티타늄 나이트라이드층(14)의 그레인 바운더리와 티타늄 실리사이드층(15)의 얇은 부분을 통해 텅스텐 원자(W)/플루오린 원자(F)와 실리콘 원자(Si)가 상호 확산되어 접합 파괴, 누설 전류 및 콘택 저항을 증가시켜 소자의 신뢰성을 저하시키는 문제점이 발생된다.As shown in FIG. 2 in which the contact hole base of FIG. 1C is enlarged, the titanium nitride layer 14 is formed in a columnar structure. If the thickness of the titanium layer 13 is thick, a uniform titanium silicide layer may be formed by rapid heat treatment. However, as the semiconductor device becomes highly integrated, the contact hole size is reduced and the aspect ratio is increased. Since the layer coverage (step coverage) of the titanium layer 13 to be made worse, there is a limit in forming the titanium layer 13 thick. In order to form the titanium layer 13 thickly, the CVD method with excellent layer covering is applied. However, when the CVD method is used, many process problems such as high impurity content in the thin film exist. It is true. Therefore, the tungsten layer 13 is formed by sputtering, and when the thickness of the tungsten layer 13 is less than or equal to the critical thickness, the titanium silicide layer 15 formed by rapid heat treatment has a uniform thickness, as shown in FIG. 2. Cannot be formed into As described above, when the titanium nitride layer 14 has a columnar structure and the tungsten layer 17 is formed by using WF 6 gas in a state where the titanium silicide layer 15 is unevenly formed, the columnar structure is formed during the formation process. Tungsten atom (W) / fluorine atom (F) and silicon atom (Si) diffuse through each other through the grain boundary of the titanium nitride layer 14 and the thin layer of the titanium silicide layer 15 to bond breakage and leakage current. And a problem of lowering the reliability of the device by increasing the contact resistance.

따라서, 본 발명은 콘택 저항을 감소시키면서 확산 방지 효과를 증대시킬 수 있는 반도체 소자의 확산 방지막 및 그 형성 방법을 제공하는데 그 목적이 있다.Accordingly, an object of the present invention is to provide a diffusion preventing film of a semiconductor device and a method of forming the same which can increase the diffusion preventing effect while reducing the contact resistance.

상술한 목적을 달성하기 위한 본 발명의 확산 방지막 형성 방법은 반도체 소자를 제조하기 위한 소정의 구조가 형성된 실리콘 기판 상부에 형성된 층간 절연막의 소정 영역을 식각하여 상기 실리콘 기판의 소정 영역을 노출시키는 콘택홀을 형성하는 단계와, 상기 콘택홀을 포함한 전체 구조 상부에 제 1 티타늄 나이트라이드층 및 티타늄층을 순차적으로 형성하는 단계와, 질소가 함유된 가스 분위기에서 열처리 공정을 실시함으로써 상기 티타늄층은 제 2 티타늄 나이트라이드층이 되고, 상기 제 1 티타늄 나이트라이드층과 상기 제 2 티타늄 나이트라이드층 사이에는 티타늄 옥사이드층이 생성되며, 상기 콘택홀 기저부의 제 1 티타늄 나이트라이드층은 티타늄 실리사이드층으로 되는 단계를 포함하여 이루어진 것을 특징으로 한다.Diffusion prevention film forming method of the present invention for achieving the above object is a contact hole for exposing a predetermined region of the silicon substrate by etching a predetermined region of the interlayer insulating film formed on the silicon substrate having a predetermined structure for manufacturing a semiconductor device Forming a first layer, sequentially forming a first titanium nitride layer and a titanium layer on the entire structure including the contact hole, and performing a heat treatment process in a gas atmosphere containing nitrogen. A titanium nitride layer, a titanium oxide layer is formed between the first titanium nitride layer and the second titanium nitride layer, and the first titanium nitride layer at the bottom of the contact hole is a titanium silicide layer. Characterized in that the made up.

도 1(a) 내지 1(c)는 종래의 반도체 소자의 확산 방지막 형성 방법을 설명하기 위한 소자의 단면도.1 (a) to 1 (c) are cross-sectional views of a device for explaining a method of forming a diffusion barrier of a conventional semiconductor device.

도 2는 도 1(c)의 콘택홀 기저부를 확대한 도면.FIG. 2 is an enlarged view of the bottom of the contact hole of FIG. 1C. FIG.

도 3(a) 내지 3(c)는 본 발명에 따른 반도체 소자의 확산 방지막 형성 방법을 설명하기 위한 소자의 단면도.3 (a) to 3 (c) are cross-sectional views of a device for explaining a method for forming a diffusion barrier of a semiconductor device according to the present invention.

도 4는 도 3(c)의 콘택홀 기저부를 확대한 도면.4 is an enlarged view of the bottom of the contact hole of FIG.

도 5(a) 및 도 5(b)는 종래의 방법으로 형성된 반도체 소자의 확산 방지막의 SEM 사진.5 (a) and 5 (b) are SEM images of the diffusion barrier of the semiconductor device formed by a conventional method.

도 6(a) 및 도 6(b)는 본 발명에 따른 방법으로 형성된 반도체 소자의 확산 방지막의 SEM 사진.6 (a) and 6 (b) are SEM images of the diffusion barrier of the semiconductor device formed by the method according to the present invention.

<도면의 주요 부분에 대한 부호 설명><Description of the symbols for the main parts of the drawings>

11 및 21 : 실리콘 기판 12 및 22 : 층간 절연막11 and 21: silicon substrate 12 and 22: interlayer insulating film

13 및 24 : 티타늄(Ti)층13 and 24: titanium layer

14, 23 및 24A : 티타늄 나이트라이드(TiN)층14, 23 and 24A: titanium nitride (TiN) layer

15 및 25 : 티타늄 실리사이드(TiSi2)층15 and 25: titanium silicide (TiSi 2 ) layer

26 : 티타늄 옥사이드(TiO)층 17 및 27 : 텅스텐층26: titanium oxide (TiO) layer 17 and 27: tungsten layer

19 및 29 : 콘택홀19 and 29: contact hole

첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.The present invention will be described in detail with reference to the accompanying drawings.

도 3(a) 내지 3(c)는 본 발명에 따른 반도체 소자의 확산 방지막 형성 방법을 설명하기 위한 소자의 단면도이고, 도 4는 도 3(c)의 콘택홀 기저부를 확대한 도면이다.3 (a) to 3 (c) are cross-sectional views of a device for explaining a method of forming a diffusion barrier of a semiconductor device according to the present invention, and FIG. 4 is an enlarged view of the bottom of the contact hole of FIG. 3 (c).

도 3(a)를 참조하면, 반도체 소자를 제조하기 위한 소정의 구조가 형성된 실리콘 기판(21) 상부에 형성된 층간 절연막(22)의 선택된 영역을 식각하여 실리콘 기판(21)의 소정 영역을 노출시키는 콘택홀(29)이 형성된다. 콘택홀(29)을 포함한 전체 구조 상부에 스퍼터링 방식으로 제 1 티타늄 나이트라이드층(23) 및 티타늄층(24)이 순차적으로 형성된다. 제 1 티타늄 나이트라이드층(23)은 약 50Å의 두께로 형성되며, 티타늄층(24)은 약 400∼600Å의 두께로 형성된다.Referring to FIG. 3A, a selected region of the interlayer insulating layer 22 formed on the silicon substrate 21 having a predetermined structure for manufacturing a semiconductor device is etched to expose a predetermined region of the silicon substrate 21. The contact hole 29 is formed. The first titanium nitride layer 23 and the titanium layer 24 are sequentially formed on the entire structure including the contact hole 29 by sputtering. The first titanium nitride layer 23 is formed to a thickness of about 50 kPa, and the titanium layer 24 is formed to a thickness of about 400 to 600 kPa.

도 3(b)는 열처리 공정을 실시한 상태의 단면도로서, 열처리 공정은 저압용반응로(low pressure furnace)에서 실시하거나 급속 열질화 처리(Rapid Thermal Nitridation; RTN)로 하며, 이때 분위기는 질소(N2) 가스, 암모늄(NH3) 가스 및 질소(N2)와 암모늄(NH3)의 혼합 가스 분위기중 어느 하나의 분위기로 한다. 열처리 결과, 티타늄층(24)은 제 2 티타늄 나이트라이드층(24A)으로 되고, 제 1 티타늄 나이트라이드층(23)과 제 2 티타늄 나이트라이드층(24A) 사이에는 티타늄 옥사이드층(TiO; 26)이 생성되며, 콘택홀(29) 기저부의 제 1 티타늄 나이트라이드층(23)은 티타늄 실리사이드층(25)으로 된다. 티타늄 실리사이드층(25)은 열처리 동안에 실리콘 기판(21)의 실리콘 원자(Si)와 제 1 티타늄 나이트라이드층(23)의 티타늄 원자(Ti)가 상호 반응함으로써 형성된다.3 (b) is a cross-sectional view of the heat treatment step, the heat treatment step is carried out in a low pressure furnace (Rapid pressure furnace) or Rapid Thermal Nitridation (Rapid Thermal Nitridation (RTN)), the atmosphere is nitrogen (N 2 ) The atmosphere is either one of a gas, an ammonium (NH 3 ) gas, and a mixed gas atmosphere of nitrogen (N 2 ) and ammonium (NH 3 ). As a result of the heat treatment, the titanium layer 24 becomes the second titanium nitride layer 24A, and between the first titanium nitride layer 23 and the second titanium nitride layer 24A, a titanium oxide layer (TiO) 26 is formed. Is generated, and the first titanium nitride layer 23 at the base of the contact hole 29 becomes the titanium silicide layer 25. The titanium silicide layer 25 is formed by mutual reaction of silicon atoms Si of the silicon substrate 21 and titanium atoms Ti of the first titanium nitride layer 23 during the heat treatment.

이와 같이 제 1 티타늄 나이트라이드층(23) 및 티타늄층(24)을 순차적으로 형성한 후 질소 분위기에서 열처리를 실시하여 확산 방지막이 완성되고, 이후 도 3(c)에 도시된 바와 같이, 텅스텐층(27)을 화학 기상 증착(Chemical Vapor Deposition; CVD) 방식으로 형성한 후 패터닝하여 금속 배선이 형성한다.As described above, the first titanium nitride layer 23 and the titanium layer 24 are sequentially formed, followed by heat treatment in a nitrogen atmosphere to complete the diffusion barrier, and as shown in FIG. 3C, the tungsten layer. (27) is formed by Chemical Vapor Deposition (CVD) and then patterned to form a metal wiring.

도 3(c)의 콘택홀 기저부를 확대한 도 4에 도시된 바와 같이, 제 2 티타늄 나이트라이드층(24A)은 미세 결정(microcrystalline) 구조로 형성된다. 티타늄 실리사이드층(25) 형성을 위한 열처리 공정 동안에 제 1 티타늄 나이트라이드층(23)에 함유된 질소 원자가 티타늄 원자와 실리콘 원자의 반응 속도 및 양을 일정하게 제어해 주기 때문에 제 1 티타늄 나이트라이드층(23)이 약 50Å 두께로 얇게 형성되더라도, 도 4에 도시된 바와 같이, 티타늄 실리사이드층(25)은 균일하게 형성된다. 따라서, 제 2 티타늄 나이트라이드층(24A)이 미세 결정 구조를 갖고, 티타늄 실리사이드층(25)이 균일하게 형성된 상태에서 WF6가스를 이용하여 텅스텐층(27)을 형성할 경우, 형성 공정중에 텅스텐 원자(W)/플루오린 원자(F)와 실리콘 원자(Si)가 상호 확산되는 것이 방지된다. 한편, 열처리 동안에 극히 적은 산소(O2) 가스에 의해 형성된 티타늄 옥사이드층(26)이 제 2 티타늄 나이트라이드층(24A)과 티타늄 실리사이드층(25) 사이에 존재하므로써, 확산 방지 효과는 더욱 극대화된다.As shown in FIG. 4 in which the contact hole base of FIG. 3C is enlarged, the second titanium nitride layer 24A is formed in a microcrystalline structure. During the heat treatment process for forming the titanium silicide layer 25, since the nitrogen atom contained in the first titanium nitride layer 23 controls the reaction rate and amount of the titanium atom and the silicon atom constantly, the first titanium nitride layer ( Although 23) is thinly formed to a thickness of about 50 ms, the titanium silicide layer 25 is formed uniformly, as shown in FIG. Therefore, when the tungsten layer 27 is formed using the WF 6 gas while the second titanium nitride layer 24A has a fine crystal structure and the titanium silicide layer 25 is uniformly formed, tungsten is formed during the formation process. The diffusion of the atoms (W) / fluorine atoms (F) and silicon atoms (Si) is prevented. On the other hand, since the titanium oxide layer 26 formed by very little oxygen (O 2 ) gas during the heat treatment exists between the second titanium nitride layer 24A and the titanium silicide layer 25, the diffusion preventing effect is further maximized. .

본 발명의 다른 실시 예로서 실리콘을 함유한 막 상부에 티타늄을 증착한 후 상술한 방법과 동일한 조건에서 급속 열질화 공정을 실시한 후 티타늄 나이트라이드층을 형성해도 동일한 효과를 얻을 수 있다.In another embodiment of the present invention, the same effect may be obtained when the titanium nitride layer is formed after the deposition of titanium on the silicon-containing film and the rapid thermal nitriding process under the same conditions as described above.

도 5(a) 및 도 5(b)는 종래의 방법으로 형성된 반도체 소자의 확산 방지막의 SEM 사진이고, 도 6(a) 및 도 6(b)는 본 발명에 따른 방법으로 형성된 반도체 소자의 확산 방지막의 SEM 사진이다.5 (a) and 5 (b) are SEM images of the diffusion barrier of the semiconductor device formed by a conventional method, Figures 6 (a) and 6 (b) is a diffusion of the semiconductor device formed by the method according to the present invention SEM photograph of the protective film.

도 5(a)를 참조하면, 100Å의 티타늄층을 형성하고 200Å의 티타늄 나이트라이드층을 형성한 후 급속 열처리 공정을 실시하면 그레인 바운더리에서 티타늄 실리사이드의 덩어리가 형성된다. 이러한 상태에서 도 5(b)에서와 같이 890℃의 온도에서 1시간동안 열처리 공정을 실시하면 텅스텐 실리사이드층 하부에서 실리콘의 손실이 발생된다.Referring to FIG. 5 (a), when a titanium layer of 100 μs is formed, a titanium nitride layer of 200 μs is formed, and a rapid heat treatment is performed, a mass of titanium silicide is formed in the grain boundary. In this state, when the heat treatment process is performed at a temperature of 890 ° C. for 1 hour as shown in FIG. 5 (b), silicon loss occurs under the tungsten silicide layer.

도 6(a)를 참조하면, 100Å의 티타늄층을 형성하고 급속 열질화 공정을 실시한 후 200Å의 티타늄 나이트라이드층을 형성하고 급속 열질화 공정을 실시한다. 이러한 공정에 의해 티타늄층과 티타늄 나이트라이드층 사이에 티타늄 실리사이드층과 티타늄 옥사이드층이 형성된다. 이러한 상태에서 도 6(b)에서와 같이 890℃의 온도에서 1시간동안 열공정을 실시하더라도 균일한 막질을 얻을 수 있다.Referring to FIG. 6 (a), after forming a titanium layer of 100 μs and performing a rapid thermal nitriding process, a titanium nitride layer of 200 μs is formed and a rapid thermal nitriding process is performed. By this process, a titanium silicide layer and a titanium oxide layer are formed between the titanium layer and the titanium nitride layer. In this state, even when the thermal process is performed for 1 hour at a temperature of 890 ℃ as shown in Figure 6 (b) it can be obtained a uniform film quality.

상술한 바와 같이, 본 발명은 확산 방지막으로 스퍼터링 방식에 의해 제 1 티타늄 나이트라이드(TiN)층과 티타늄(Ti)층을 형성한 후 질소가 함유된 가스 분위기에서 급속 열질화 처리(RTN)를 실시하여 티타늄층을 미세 결정 구조의 제 2 티타늄 나이트라이드층으로 변형시키고, 콘택홀 기저부의 제 1 티타늄 나이트라이드층을 균일한 두께의 티타늄 실리사이드층으로 변형시키며, 제 1 티타늄 나이트라이드층과 티타늄 실리사이드층 사이에 티타늄 옥사이드(TiO)층이 형성되어 확산 방지 효과를 극대화시킬 수 있다.As described above, the present invention forms a first titanium nitride (TiN) layer and a titanium (Ti) layer by sputtering as a diffusion barrier, and then performs rapid thermal nitriding treatment (RTN) in a gas atmosphere containing nitrogen. The titanium layer is transformed into a second titanium nitride layer having a fine crystal structure, and the first titanium nitride layer of the contact hole base is transformed into a titanium silicide layer having a uniform thickness, and the first titanium nitride layer and the titanium silicide layer Titanium oxide (TiO) layer is formed in between to maximize the diffusion prevention effect.

Claims (3)

소정의 구조가 형성된 실리콘 기판 상부에 층간 절연막을 형성한 후 상기 층간 절연막의 소정 영역을 식각하여 상기 실리콘 기판의 소정 영역을 노출시키는 콘택홀을 형성하는 단계와,Forming a contact hole exposing a predetermined region of the silicon substrate by forming an interlayer insulating layer on the silicon substrate having a predetermined structure and then etching a predetermined region of the interlayer insulating layer; 상기 콘택홀을 포함한 전체 구조 상부에 제 1 티타늄 나이트라이드층 및 티타늄층을 순차적으로 형성하는 단계와,Sequentially forming a first titanium nitride layer and a titanium layer on the entire structure including the contact hole; 질소가 함유된 가스 분위기에서 열처리 공정을 실시하고, 이에 의해 상기 티타늄층은 제 2 티타늄 나이트라이드층으로 변화되고, 상기 제 1 티타늄 나이트라이드층과 상기 제 2 티타늄 나이트라이드층 사이에는 티타늄 옥사이드층이 생성되며, 상기 콘택홀 기저부의 제 1 티타늄 나이트라이드층은 티타늄 실리사이드층으로 변화되는 단계를 포함하여 이루어진 것을 특징으로 하는 반도체 소자의 확산 방지막 형성 방법.The heat treatment process is performed in a gas atmosphere containing nitrogen, whereby the titanium layer is changed into a second titanium nitride layer, and a titanium oxide layer is formed between the first titanium nitride layer and the second titanium nitride layer. A method of forming a diffusion barrier of a semiconductor device, wherein the first titanium nitride layer is formed into a titanium silicide layer. 제 1 항에 있어서, 상기 열처리 공정은 질소(N2) 가스, 암모늄(NH3) 가스 및 질소(N2)와 암모늄(NH3)의 혼합 가스 분위기중 어느 하나의 분위기에서 실시하는 급속 열질화 공정인 것을 특징으로 하는 반도체 소자의 확산 방지막 형성 방법.The method of claim 1, wherein the heat treatment step is rapid thermal nitriding carried out in any one atmosphere of nitrogen (N 2 ) gas, ammonium (NH 3 ) gas and mixed gas atmosphere of nitrogen (N 2 ) and ammonium (NH 3 ). It is a process, The diffusion prevention film formation method of the semiconductor element characterized by the above-mentioned. 제 1 항에 있어서, 상기 티타늄층은 400 내지 600Å의 두께로 형성되는 것을 특징으로 하는 반도체 소자의 확산 방지막 형성 방법.The method of claim 1, wherein the titanium layer is formed to a thickness of 400 to 600 kPa.
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