KR100322886B1 - Method for forming metal contact of a semiconductor device - Google Patents
Method for forming metal contact of a semiconductor device Download PDFInfo
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- KR100322886B1 KR100322886B1 KR1019990026399A KR19990026399A KR100322886B1 KR 100322886 B1 KR100322886 B1 KR 100322886B1 KR 1019990026399 A KR1019990026399 A KR 1019990026399A KR 19990026399 A KR19990026399 A KR 19990026399A KR 100322886 B1 KR100322886 B1 KR 100322886B1
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- Prior art keywords
- metal
- layer
- forming
- silicide
- contact
- Prior art date
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- 229910052751 metal Inorganic materials 0.000 title claims abstract description 52
- 239000002184 metal Substances 0.000 title claims abstract description 52
- 238000000034 method Methods 0.000 title claims abstract description 28
- 239000004065 semiconductor Substances 0.000 title claims abstract description 15
- 239000010410 layer Substances 0.000 claims abstract description 50
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 29
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 29
- 238000000151 deposition Methods 0.000 claims abstract description 21
- 238000010438 heat treatment Methods 0.000 claims abstract description 20
- 238000009792 diffusion process Methods 0.000 claims abstract description 15
- 230000004888 barrier function Effects 0.000 claims abstract description 8
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 8
- 238000000059 patterning Methods 0.000 claims abstract description 6
- 239000000758 substrate Substances 0.000 claims abstract description 6
- 239000011229 interlayer Substances 0.000 claims abstract description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 5
- 229920005591 polysilicon Polymers 0.000 claims abstract description 5
- 125000006850 spacer group Chemical group 0.000 claims abstract description 5
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 9
- 230000008021 deposition Effects 0.000 claims description 9
- 239000010936 titanium Substances 0.000 claims description 9
- 229910052719 titanium Inorganic materials 0.000 claims description 9
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 4
- 239000012300 argon atmosphere Substances 0.000 claims description 4
- 239000010941 cobalt Substances 0.000 claims description 4
- 229910017052 cobalt Inorganic materials 0.000 claims description 4
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims description 4
- 229910052757 nitrogen Inorganic materials 0.000 claims description 4
- 239000012299 nitrogen atmosphere Substances 0.000 claims description 4
- 239000011259 mixed solution Substances 0.000 claims description 3
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 3
- 238000005530 etching Methods 0.000 claims description 2
- 238000001039 wet etching Methods 0.000 claims description 2
- 239000000203 mixture Substances 0.000 claims 1
- 239000000376 reactant Substances 0.000 claims 1
- 229910021341 titanium silicide Inorganic materials 0.000 abstract description 10
- 238000005229 chemical vapour deposition Methods 0.000 abstract description 7
- 238000004519 manufacturing process Methods 0.000 abstract description 3
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 abstract 1
- 229910008484 TiSi Inorganic materials 0.000 description 5
- 238000005755 formation reaction Methods 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 3
- 239000010937 tungsten Substances 0.000 description 3
- 229910052721 tungsten Inorganic materials 0.000 description 3
- 230000008054 signal transmission Effects 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 229910003902 SiCl 4 Inorganic materials 0.000 description 1
- 239000012298 atmosphere Substances 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 238000000752 ionisation method Methods 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 230000006911 nucleation Effects 0.000 description 1
- 238000010899 nucleation Methods 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
- H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System the conductive layers comprising silicides
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
- H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
- H01L21/28061—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a metal or metal silicide formed by deposition, e.g. sputter deposition, i.e. without a silicidation reaction
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32134—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by liquid etching only
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
Abstract
본 발명은 콘택홀의 확산층에 스텝커버리지가 우수한 CVD법으로 선택적으로 확산층에만 열처리 없이 티타늄 실리사이드를 형성하여 애스팩트율이 큰 작은 콘택홀에서도 낮은 접촉저항의 금속배선을 가능하게 한 금속 콘택을 형성하는 반도체장치의 금속 콘택 형성 방법에 관한 것으로서, 반도체 기판(10) 위에 게이트산화막(60)과 폴리실리콘층(40)을 증착하여 게이트전극을 형성하고 스페이서(50)와 확산층(30)을 형성하는 단계와, 결과물에서 실리사이드를 형성시키지 않을 부분에 실리사이드형성을 막기 위한 장벽산화막(70)을 증착하는 단계와, 결과물 전면에 실리사이드 형성을 위한 금속층(80)을 형성하고 제 1차 열처리를 수행하여 제 1금속 실리사이드층(90)을 형성한 후 선택적 습식 에치를 통해 금속층(80)을 제거하고 제 2차 열처리를 하는 단계와, 결과물위로 층간절연막(100)을 증착하고 평탄화한 후 콘택홀(110)을 패터닝하는 단계와, 콘택홀(110) 하부면에 선택적으로 제 2금속 실리사이드층(95)을 형성하는 단계를 포함하여 이루어져 고집적 소자에서 누설전류가 낮고 안정적인 소자 제조를 가능하다는 이점이 있다.The present invention is a semiconductor that forms a metal contact which enables a metal contact with low contact resistance even in a small contact hole having a high aspect ratio by forming titanium silicide without heat treatment only on the diffusion layer by a CVD method having excellent step coverage in the contact layer diffusion layer. A method of forming a metal contact in a device, comprising: depositing a gate oxide film 60 and a polysilicon layer 40 on a semiconductor substrate 10 to form a gate electrode, and forming a spacer 50 and a diffusion layer 30; And depositing a barrier oxide film 70 to prevent silicide formation on a portion of the resultant that will not form silicide, and forming a metal layer 80 for silicide formation on the entire surface of the resultant and performing a first heat treatment. Forming the silicide layer 90 and then removing the metal layer 80 through a selective wet etch and performing a second heat treatment. Patterning the contact hole 110 after depositing and planarizing the interlayer insulating film 100 over water, and optionally forming a second metal silicide layer 95 on the bottom surface of the contact hole 110. In high-integration devices, there is an advantage that low leakage current and stable device manufacturing are possible.
Description
본 발명은 반도체장치의 금속 콘택 형성 방법에 관한 것으로서, 보다 상세하게는 금속배선을 위한 콘택홀의 확산층에 스텝커버리지가 우수한 CVD법으로 선택적으로 확산층에만 열처리 없이 티타늄 실리사이드를 바로 형성하여 애스팩트율이 큰 작은 콘택홀에서도 낮은 접촉저항의 금속배선을 가능하게 한 금속 콘택을 형성하는 반도체장치의 금속 콘택 형성 방법에 관한 것이다.The present invention relates to a method for forming a metal contact of a semiconductor device, and more particularly, by using a CVD method having excellent step coverage in a diffusion layer of a contact hole for metal wiring, selectively forming a titanium silicide without heat treatment only on the diffusion layer to have a large aspect ratio. The present invention relates to a method for forming a metal contact in a semiconductor device for forming a metal contact which enables a metal contact with low contact resistance even in a small contact hole.
최근에는 반도체 디자인 룰이 점점 미세화됨에 따라 반도체 소자를 다층배선 형태로 제조하고 있어 다층 금속배선간을 연결하기 위한 콘택이 매우 중요한 위치를 차지하게 되었다.In recent years, as semiconductor design rules become more and more sophisticated, semiconductor devices are manufactured in the form of multilayer interconnections, and contacts for interconnecting multilayer metal interconnections have become very important.
즉, 콘택을 통해 금속배선간의 신호전달이 이루어지기 때문에 접촉상태와 접촉저항에 따라 신호의 전달특성이 좌우되기 때문에 소자의 특성향상에 중요한 요인이된다.That is, since the signal transmission between the metal wiring is made through the contact, the signal transmission characteristic depends on the contact state and the contact resistance, which is an important factor in improving the characteristics of the device.
종래의 금속 콘택 접촉은 스퍼터링에 의한 티타늄이나 화학증착법에 의한 티타늄질화막을 증착한 후 열처리를 진행하고, 텅스텐을 증착하는 순으로 이루어진다.Conventional metal contact contact is made by depositing titanium by sputtering or titanium nitride by chemical vapor deposition, followed by heat treatment, and then depositing tungsten.
이때 열처리는 확산층과 티타늄을 서로 반응하게 하여 금속실리사이드를 형성시킴으로써 금속실리사이드가 형성되지 않은 부분의 접촉저항을 낮추기 위해 티타늄 증착후나 티타늄 질화막 증착후 이루어졌다.At this time, the heat treatment was performed after the titanium deposition or the titanium nitride film deposition to reduce the contact resistance of the portion where the metal silicide is not formed by reacting the diffusion layer and titanium to form a metal silicide.
하지만 소자가 점점 고집적화됨에 따라 콘택홀이 작아져 콘택홀의 지름에 대한 높이의 애스팩트율이 점점 커져 보통의 스퍼터링법에 의해서는 증착이 힘들어 collimator 법이나 금속이온화법(IMP)을 사용하나 이는 증착속도도 낮고 어디까지나 콘택홀의 증착에 한계를 갖게 된다. 그리고 불균질한 증착은 열처리후 누설전류의 원인이 되기도한다.However, as the device becomes more integrated, the contact hole becomes smaller and the aspect ratio of the height to the diameter of the contact hole becomes larger, so that it is difficult to deposit by the normal sputtering method, so that the collimator method or the metal ionization method (IMP) is used. In addition, there is a limit to the deposition of contact holes to the last. Inhomogeneous deposition may cause leakage current after heat treatment.
따라서 0.25㎛이하의 고집적 소자에서는 스텝커버리지(측면 도포성)이 우수한 CVD법이 필요하게 되었다. CVD티타늄/CVD티타늄질화막 구조도 연구되고 있으나 추가 열처리가 필요하고 CVD티타늄증착시 산소함유 농도 등 문제점이 발생한다.Therefore, the CVD method which is excellent in step coverage (side coating property) is needed for the highly integrated element below 0.25 micrometer. CVD titanium / CVD titanium nitride film structure is also being studied, but additional heat treatment is required, and problems such as oxygen concentration in CVD titanium deposition occur.
본 발명은 상기와 같은 문제점을 해결하기 위해 창작된 것으로서, 본 발명의 목적은 콘택홀의 확산층에 스텝커버리지가 우수한 CVD법으로 선택적으로 확산층에만 열처리 없이 티타늄 실리사이드를 바로 형성하여 애스팩트율이 큰 작은 금속 콘택홀에서 낮은 접촉 저항의 금속배선을 가능하게 하여 신뢰성이 있는 소자 제조할 수 있도록 한 반도체장치의 금속 콘택 형성 방법을 제공함에 있다.The present invention has been made to solve the above problems, and an object of the present invention is a small metal having a large aspect ratio by directly forming titanium silicide without heat treatment only on the diffusion layer by a CVD method having excellent step coverage in the diffusion layer of the contact hole. The present invention provides a method for forming a metal contact of a semiconductor device, which enables a low contact resistance metal wiring in a contact hole to manufacture a reliable device.
도 1내지 도 4는 본 발명에 의한 반도체장치의 금속 콘택 형성 방법을 설명하기 위해 도시한 단면도들이다.1 to 4 are cross-sectional views illustrating a metal contact forming method of a semiconductor device according to the present invention.
- 도면의 주요부분에 대한 부호의 설명 --Explanation of symbols for the main parts of the drawings-
10 : 기판 20 : 필드산화막10: substrate 20: field oxide film
60 : 게이트산화막 40 : 폴리실리콘층60 gate oxide film 40 polysilicon layer
50 : 스페이서 30 : 확산층50 spacer 30 diffusion layer
70 : 장벽산화막 80 : 금속층70: barrier oxide film 80: metal layer
90 : 제 1금속 실리사이드층 95 : 제 2금속 실리사이드층90: first metal silicide layer 95: second metal silicide layer
100 : 층간절연막 110 : 콘택홀100: interlayer insulating film 110: contact hole
상기와 같은 목적을 실현하기 위한 본 발명은 반도체 기판위에 게이트산화막과 폴리실리콘층을 증착하여 게이트 전극을 형성하고 스페이서와 확산층을 형성하는 단계와, 상기 결과물 상 후속 애스팩트율이 큰 작은 콘택홀이 형성될 부분으로 실리사이드를 형성 시키지 않을 부분에 장벽산화막을 증착하는 단계와, 상기 결과물 전면에 실리사이드 형성을 위한 금속층을 형성하고 제 1차 열처리를 수행하여 제 1금속 실리사이드층을 형성한 후 선택적 습식 에치를 통해 금속층을 제거하고 제 2차 열처리를 하는 단계와, 상기 결과물위로 층간절연막을 증착하고 평탄화한 후 콘택홀을 패터닝하는 단계와, 상기 콘택홀 하부면에 선택적으로 PECVD법을 이용하여 제 2금속 실리사이드층을 형성하는 단계를 포함하여 이루어진 것을 특징으로 한다.The present invention for achieving the above object is a step of forming a gate electrode, a spacer and a diffusion layer by depositing a gate oxide film and a polysilicon layer on a semiconductor substrate, and a small contact hole having a large subsequent aspect ratio on the result Depositing a barrier oxide film on a portion which will not form silicide as a portion to be formed, forming a metal layer for silicide formation on the entire surface of the resultant, and performing a first heat treatment to form a first metal silicide layer, followed by selective wet etching. Removing the metal layer through the second layer and performing a second heat treatment, depositing and planarizing the interlayer insulating film on the resultant, and patterning the contact hole, and selectively using a PECVD method on the lower surface of the contact hole. It characterized by comprising a step of forming a silicide layer.
상기와 같이 이루어진 본 발명에 의하면 금속실리사이드가 형성되지 않은 애스팩트율이 큰 작은 콘택홀 내에서도 CVD법에 의해 금속실리사이드를 형성함으로써 배선용 금속과의 접촉저항이 낮고 누설전류가 작은 고집적 소자 제조가 가능하게 된다.According to the present invention made as described above by forming the metal silicide by the CVD method even in a small contact hole having a large aspect ratio in which no metal silicide is formed, it is possible to manufacture a highly integrated device having a low contact resistance with a wiring metal and a small leakage current. do.
이하, 본 발명의 바람직한 실시예를 첨부된 도면을 참조하여 설명한다. 또한 본 실시예는 본 발명의 권리범위를 한정하는 것은 아니고, 단지 예시로 제시된 것이며 종래 구성과 동일한 부분은 동일한 부호 및 명칭을 사용한다.Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings. In addition, the present embodiment is not intended to limit the scope of the present invention, but is presented by way of example only and the same parts as in the conventional configuration using the same reference numerals and names.
도 1내지 도 4는 본 발명에 의한 반도체장치의 금속 콘택 형성 방법을 설명하기 위해 도시한 단면도들이다.1 to 4 are cross-sectional views illustrating a metal contact forming method of a semiconductor device according to the present invention.
도 1에 도시된 바와 같이 실리콘 기판(10) 위로 절연용 필드산화막(20)을 형성하고, 게이트산화막(60), 폴리실리콘층(40)을 증착한 후 패터닝공정을 통해 게이트전극을 형성한 후 LDD영역과 절연용 스페이서(50)를 형성하고 소오스/드레인 확산층(30)을 형성한다.As shown in FIG. 1, after forming the insulating field oxide film 20 on the silicon substrate 10, depositing the gate oxide film 60 and the polysilicon layer 40, and forming a gate electrode through a patterning process. The LDD region and the insulating spacer 50 are formed, and the source / drain diffusion layer 30 is formed.
그리고, 도 2에 도시된 바와 같이 상기 결과물위에 실리사이드형성을 막기 위한 장벽산화막(70)을 500∼1000Å의 두께로 증착하고 패터닝공정을 통해 특정부분에만 남긴다. 그리고 그 위에 금속실리사이드 형성을 위한 티타늄이나 코발트로이루어진 금속층(80)을 증착한다.As shown in FIG. 2, a barrier oxide film 70 is formed on the resultant to prevent silicide formation at a thickness of 500 to 1000 GPa and is left only in a specific portion through a patterning process. Then, a metal layer 80 made of titanium or cobalt is deposited thereon.
그런다음, 도 3에서 보는 바와 같이 결과물에 실리사이드형성을 위한 제 1차 열처리를 급속열처리 장비로 650℃∼750℃에서 질소 또는 아르곤 분위기에서 수십초간 진행하고 미반응 금속인 금속층(80)을 제거한다. 이때 금속층(80)이 티타늄인 경우에는 NH4OH : H2O2: H2O = 1:1:5 혼합액에서 에치하고 코발트인 경우에는 H2SO4: H2O2= 4 : 1 혼합액에서 에치한다. 이와 같이 습식 에치를 행한 후 2차열처리를 800℃∼900℃에서 질소 또는 아르곤 분위기에서 수십초 진행하면 실리사이드 형성을 막기 위한 장벽산화막(70)이 없는 쪽에만 제 1금속 실리사이드층(90)이 형성된다.이어서, 상기 장벽산화막(70)을 식각공정을 진행하여 제거한다.Then, as shown in FIG. 3, the first heat treatment for silicide formation in the resultant is carried out for 10 seconds in a nitrogen or argon atmosphere at 650 ° C. to 750 ° C. with rapid heat treatment equipment, and the metal layer 80, which is an unreacted metal, is removed. . In this case, when the metal layer 80 is titanium, NH 4 OH: H 2 O 2 : H 2 O = 1: 1: 5 etched in a mixed solution, and in the case of cobalt, H 2 SO 4 : H 2 O 2 = 4: 1 mixed solution Etch in After the wet etch, the secondary heat treatment is performed for 10 seconds in a nitrogen or argon atmosphere at 800 ° C. to 900 ° C., whereby the first metal silicide layer 90 is formed only on the side without the barrier oxide film 70 to prevent silicide formation. Subsequently, the barrier oxide layer 70 is removed by performing an etching process.
그리고, 도 4와 같이 소자와의 절연을 위한 층간절연막(100)을 증착한 후, 평탄화공정을 거친후 콘택홀(110)을 위한 패터닝 공정을 행하여 콘택홀(110)을 형성한다. 상기 콘택홀(110)을 형성한 다음 선택적인 CVD법으로 콘택홀(110)하부에 티타늄실리사이드를 핵생성시키면 실리콘이 노출되어 있는 콘택홀(110) 하부에만 제 2금속 실리사이드층(95)이 선택적으로 확산층(30)의 실리콘을 소모시키면서 증착된다.As shown in FIG. 4, after the interlayer insulating film 100 is insulated from the device, the contact hole 110 is formed by performing a patterning process for the contact hole 110 after the planarization process. After forming the contact hole 110 and nucleating titanium silicide under the contact hole 110 by selective CVD, the second metal silicide layer 95 is selectively formed only under the contact hole 110 where silicon is exposed. As a result, it is deposited while consuming silicon of the diffusion layer 30.
이때 선택적 제 2금속 실리사이드층(95)인 티타늄실리사이드(TiSi2)형성 반응은 다음과 같다.At this time, the titanium silicide (TiSi2) formation reaction of the selective second metal silicide layer 95 is as follows.
핵생성 : TiCl4+ 3Si(S) → TiSi2(S) + SiCl4(g) orNucleation: TiCl 4 + 3Si (S) → TiSi 2 (S) + SiCl 4 (g) or
TiCl4+ 4Si(S) → TiSi2(S) + 2SiCl4(g)TiCl 4 + 4Si (S) → TiSi 2 (S) + 2SiCl 4 (g)
증 착 : TiCl4+ 4SiH2Cl4→ TiSi2+ 4HCl(g) + 2SiCl4(g) + 2H2 Deposition: TiCl 4 + 4SiH 2 Cl 4 → TiSi 2 + 4HCl (g) + 2SiCl 4 (g) + 2H 2
여기에 환원성 분위기를 유지하기 위하여 H2기체를 추가할 수도 있다.H 2 gas may also be added thereto to maintain a reducing atmosphere.
위의 반응에 의해 산화막 위에는 제 2금속 실리사이드층(95)인 티타늄실리사이드(TiSi2)가 형성되지 않으면서 실리콘기판(10) 위에서만 티타늄실리사이드(TiSi2)가 선택적으로 형성된다.By the above reaction, titanium silicide (TiSi 2 ) is selectively formed only on the silicon substrate 10 without forming titanium silicide (TiSi 2 ), which is the second metal silicide layer 95, on the oxide film.
그리고, CVD티타늄질화물, 텅스텐을 증착한 후 평탄화 공정을 거쳐 텅스텐 플러그를 형성하고 후속 금속배선 공정을 진행한다.After the deposition of CVD titanium nitride and tungsten, a planarization process is performed to form a tungsten plug, followed by a subsequent metallization process.
이상의 공정을 통해 콘택홀이 작은 고집적 소자에서 실리사이드층이 형성되지 않은 확산층에 콘택이 접촉되는 부분에 선택적인 티타늄실리사이드층을 형성함으로써 소자의 저항을 낮춤으로써 고속도의 고집적 소자를 제조할 수 있다.Through the above process, a high-thickness integrated device can be manufactured by lowering the resistance of the device by forming a selective titanium silicide layer on the contact portion in the diffusion layer in which the silicide layer is not formed in the high-density device having small contact holes.
상기한 바와 같이 본 발명은 콘택홀의 크기가 작아 애스팩트율이 큰 고집적 소자에서 스텝커버리지가 우수한 CVD법을 이용해 선택적으로 확산 영역의 실리콘이 노출된 접촉영역에만 티타늄실리사이드를 형성함으로써 기존의 방법보다 작은 콘택홀에서도 균일하게 콘택형성이 가능하여 불균일한 증착에 의한 열처리로부터 생기는 누설전류를 줄일 수 있고 단순한 공정을 적용함으로써 고집적 소자에서 누설전류가 낮고 안정적인 소자 제조를 가능하다는 이점이 있다.As described above, according to the present invention, titanium silicide is selectively formed only in the silicon-contacted contact region of the diffusion region by the CVD method which has excellent step coverage in the highly integrated device having a small contact hole and a large aspect ratio. The contact hole can be formed uniformly in the contact hole, thereby reducing the leakage current resulting from the heat treatment by non-uniform deposition, and by applying a simple process, the leakage current is low and stable devices can be manufactured in the highly integrated device.
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