KR100342826B1 - Method for forming barrier metal layer of semiconductor device - Google Patents

Method for forming barrier metal layer of semiconductor device Download PDF

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KR100342826B1
KR100342826B1 KR1019950025926A KR19950025926A KR100342826B1 KR 100342826 B1 KR100342826 B1 KR 100342826B1 KR 1019950025926 A KR1019950025926 A KR 1019950025926A KR 19950025926 A KR19950025926 A KR 19950025926A KR 100342826 B1 KR100342826 B1 KR 100342826B1
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titanium
layer
forming
barrier metal
metal layer
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KR1019950025926A
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Korean (ko)
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KR970013219A (en
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김춘환
진성곤
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
    • H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
    • H01L21/28052—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a silicide layer formed by the silicidation reaction of silicon with a metal layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
    • H01L21/2855—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System by physical means, e.g. sputtering, evaporation

Abstract

PURPOSE: A method for forming a barrier metal layer of a semiconductor device is provided to be capable of simplifying forming processes by carrying out an RTP(Rapid Thermal Process) under N2 or NH3 gas condition after depositing a titanium layer. CONSTITUTION: An insulating layer(3) is formed on a silicon substrate(1) having a junction region(2). After forming a contact hole by selectively etching the insulating layer for exposing the junction region, a titanium layer is deposited on the entire surface of the resultant structure. The titanium layer is transformed into a titanium nitride layer(4A) while forming a titanium silicon layer(5) between the titanium layer and the silicon substrate by carrying out the first RTP at the temperature of 600-700 °C under nitrogen gas condition. The second RTP is carried out at the temperature of 800-1000 °C for reducing the resistivity value of the titanium silicon layer.

Description

반도체 소자의 베리어 금속층 형성방법Barrier metal layer formation method of semiconductor device

본 발명은 반도체 소자의 베리어 금속층 형성방법에 관한 것으로, 특히 티타늄을 증착한 후 N2또는 NH3가스 분위기하에서 급속 열처리공정을 실시하므로써 공정을 단순화시켜 소자의 수율을 향상시킬 수 있도록 한 반도체 소자의 베리어 금속층 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a barrier metal layer of a semiconductor device. In particular, a method of forming a barrier metal layer of a semiconductor device may be performed by performing a rapid heat treatment process under an N 2 or NH 3 gas atmosphere after vapor deposition of titanium. A method of forming a barrier metal layer.

일반적으로 반도체 소자의 제조에 사용되는 베리어 금속(Barrier Metal)은 실리콘기판에 형성된 접합영역에 알루미늄(Al)과 같은 금속이 접촉되는 경우 알루미늄(Al)과 실리콘(Si)의 상호 확산에 의해 발생되는 접합 파괴(Junction Spiking) 현상을 방지하기 위하여 금속층을 형성하기 전에 증착하는 확산 방지용 금속이다. 그러므로 알루미늄 및 실리콘과의 반응성이 없어야 하고 고온에서 열적 안정성이 우수해야 하며, 또한 알루미늄(Al), 실리콘(Si) 등에 대한 확산 억제 능력이 높고 실리콘과 저항성 접촉(Ohmic Contact)이 가능한 금속이어야 한다. 현재 이러한 베리어 금속층은 티타늄(Ti)/티타늄나이트라이드(TiN)가 적층된 이중 구조로 사용된다. 그러면 종래 반도체 소자의 베리어 금속층 형성방법을 설명하면 다음과 같다.In general, a barrier metal used in the manufacture of a semiconductor device is generated by mutual diffusion of aluminum (Al) and silicon (Si) when a metal such as aluminum (Al) contacts a junction region formed on a silicon substrate. It is a diffusion preventing metal that is deposited before forming a metal layer to prevent junction spiking. Therefore, it must be non-reactive with aluminum and silicon, have excellent thermal stability at high temperature, and be a metal with high diffusion suppression ability to aluminum (Al), silicon (Si), and the like, and capable of ohmic contact with silicon. Currently, this barrier metal layer is used as a dual structure in which titanium (Ti) / titanium nitride (TiN) is stacked. Next, a method of forming a barrier metal layer of a conventional semiconductor device will be described.

종래에는 접합영역이 형성된 실리콘기판상에 절연층을 형성하고 상기 접합영역이 노출되도록 상기 절연층을 패터닝하여 콘택홀(Contact Hole)을 형성한 상태에서, 먼저 상기 접합영역과의 접촉저항을 감소시키며 상기 실리콘기판과의 접착성을 증가시키기 위하여 전체 상부면에 티타늄(Ti)을 증착한다. 이후 반응성 스퍼터링(Reactive Sputtering) 방법을 이용하여 상기 티타늄(Ti)상에 티타늄나이트라이드(TiN)를 증착하고 확산 방지 효과를 증대시키며, 상기 접합영역의 실리콘기판 계면에 티타늄실리콘(TiSi2)층을 형성하기 위하여 600 내지 800℃의 온도에서 급속 열처리공정(Rapid Thermal Process)을 실시한다. 상기 티타늄실리콘층은 티타늄보다 전기적 비저항값이 낮기 때문에 상부에 형성될 금속층과 상기 접합영역과의 접촉저항이 감소된다. 이와 같이 베리어 금속층이 티타늄(Ti)/티타늄나이트라이드(TiN)가 적층된 이중 구조로 형성되는 이유를 설명하면 다음과 같다. 만일 상기 베리어 금속층이 티타늄(Ti)만으로 이루어졌다면, 그상부에 텅스텐(W)이 증착되는 경우 소오스 가스(Source Gas)인 WF6가 티타늄(Ti)과 반응하여 비휘발성 물질인 TiF3를 생성시키고, 생성된 TiF3에 의해 후속 열처리 공정시 상기 텅스텐(W)의 들뜸 현상이 발생된다. 그러한 이유로 인해 베리어 금속층은 이중 구조로 형성된다. 그러나 이러한 방법은 공정의 단계가 복잡하기 때문에 생산 수율을 저하시키는 단점이 있다.Conventionally, in the state in which a contact hole is formed by forming an insulating layer on a silicon substrate on which a junction region is formed and patterning the insulating layer so that the junction region is exposed, the contact resistance with the junction region is first reduced. In order to increase adhesion with the silicon substrate, titanium (Ti) is deposited on the entire upper surface. Then, titanium nitride (TiN) is deposited on the titanium (Ti) by using a reactive sputtering method, and the diffusion preventing effect is increased, and a titanium silicon (TiSi 2 ) layer is formed on the silicon substrate interface of the junction region. In order to form, a rapid thermal process is carried out at a temperature of 600 to 800 ℃. Since the titanium silicon layer has lower electrical resistivity than titanium, the contact resistance between the metal layer to be formed on the upper portion and the junction region is reduced. The reason why the barrier metal layer is formed in a double structure in which titanium (Ti) / titanium nitride (TiN) is stacked is as follows. If the barrier metal layer is made of only titanium (Ti), when tungsten (W) is deposited thereon, WF 6 , a source gas, reacts with titanium to generate non-volatile TiF 3 . In the subsequent heat treatment process, the tungsten (W) is lifted up by the generated TiF 3 . For that reason, the barrier metal layer is formed in a double structure. However, this method has the disadvantage of lowering the production yield because the process steps are complicated.

따라서 본 발명은 티타늄을 증착한 후 N2또는 NH3가스 분위기하에서 급속 열처리공정을 실시하므로써 상기한 단점을 해소할 수 있는 반도체 소자의 베리어 금속층 형성방법을 제공하는 데 그 목적이 있다.Accordingly, an object of the present invention is to provide a method for forming a barrier metal layer of a semiconductor device capable of solving the above-mentioned disadvantages by performing a rapid heat treatment process under an N 2 or NH 3 gas atmosphere after depositing titanium.

상기한 목적을 달성하기 위한 본 발명은 접합영역이 형성된 실리콘 기판상에 절연층을 형성하고, 상기 접합영역이 노출되도록 상기 절연층을 패터닝하여 콘택홀을 형성시킨 상태에서, 전체 상부면에 티타늄을 증착하는 단계와, 상기 단계로부터 상기 절연층상의 상기 티타늄을 티타늄나이트라이드로 변화시키며, 상기 접합영역의 실리콘기판상에는 티타늄실리콘층이 형성되도록 1차 급속 열처리공정을 실시하는 단계와, 상기 단계로부터 상기 티타늄실리콘층의 비저항값을 감소시키기 위하여 온도를 상승시킨 후 2차 급속 열처리공정을 실시하는 단계로 이루어지는 것을 특징으로 한다.In order to achieve the above object, the present invention provides an insulating layer on a silicon substrate on which a junction region is formed, and in which a contact hole is formed by patterning the insulation layer to expose the junction region, titanium is formed on the entire upper surface. And depositing the titanium on the insulating layer from the step into titanium nitride, and performing a first rapid heat treatment process so that a titanium silicon layer is formed on the silicon substrate in the bonding region. In order to reduce the specific resistance of the titanium silicon layer, the temperature is increased, and then the second rapid heat treatment process is performed.

이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

제 1A 및 제 1B 도는 본 발명에 따른 반도체 소자의 베리어 금속층 형성방법을 설명하기 위한 소자의 단면도로서,1A and 1B are cross-sectional views of a device for explaining a method of forming a barrier metal layer of a semiconductor device according to the present invention.

제 1A 도는 접합영역(2)이 형성된 실리콘기판(1)상에 절연층(3)을 형성하고, 상기 접합영역(2)이 노출되도록 상기 절연층(3)을 패터닝하여 콘택홀을 형성시킨 상태에서, 전체 상부면에 티타늄(Ti; 4)을 증착한 상태의 단면도이다.1A or the insulating layer 3 is formed on the silicon substrate 1 in which the junction area | region 2 was formed, and the insulating layer 3 is patterned so that the said junction area | region 2 may be exposed, and the contact hole was formed. Is a cross-sectional view of the titanium (Ti; 4) is deposited on the entire upper surface.

제 1B 도는 600 내지 700℃의 저온 및 N2또는 NH3가스 분위기 상태에서 1차 급속 열처리공정을 실시한 상태의 단면도인데, 이때 상기 절연층(3)상의 상기 티타늄(4)은 일부 또는 전부 티타늄나이트라이드(4A)로 변화되며, 상기 접합영역(2)의 실리콘기판(1)상에는 티타늄실리콘층(5)이 형성된다. 이후 온도를 800 내지 1000℃의 고온으로 상승시키고 2차 급속열처리를 실시하는데, 이때 상기 티타늄실리콘층(5)의 위상(Phase)이 비저항값이 높은 C49 상에서 비저항값이 낮은 C54 상으로 변화되어 상부에 형성될 금속층과 접합영역과의 접촉저항을 감소시킬 수 있다.FIG. 1B is a cross-sectional view of a first rapid heat treatment process at a low temperature of 600 to 700 ° C. and a N 2 or NH 3 gas atmosphere, wherein the titanium 4 on the insulating layer 3 is partially or entirely titanium nitride. The titanium silicon layer 5 is formed on the silicon substrate 1 of the junction region 2 and is changed to a ride 4A. Thereafter, the temperature is increased to a high temperature of 800 to 1000 ° C., and the second rapid heat treatment is performed. At this time, the phase of the titanium silicon layer 5 is changed from C49 having a high specific resistance to a C54 phase having a low specific resistance. It is possible to reduce the contact resistance between the metal layer to be formed in the junction region.

상술한 바와 같이 본 발명에 의하면 티타늄을 증착한 후 N2또는 NH3가스 분위기하에서 두번의 급속 열처리공정을 실시하므로써 실리콘기판과의 계면에 티타늄보다 낮은 비저항값을 갖는 티타늄실리콘(TiSi2)층을 형성하여 상부에 형성될 금속층과 접합영역과의 접촉저항을 감소시킬 수 있다. 또한 티타늄나이트라이드(TiN)를 증착하는 공정이 실시되지 않으므로 공정이 단순해져 소자의 생산 수율이 향상될 수 있는 탁월한 효과가 있다.As described above, according to the present invention, a titanium silicon (TiSi 2 ) layer having a lower resistivity than titanium is formed at an interface with a silicon substrate by performing two rapid heat treatment processes in a N 2 or NH 3 gas atmosphere after depositing titanium. The contact resistance between the metal layer and the junction region to be formed on the upper portion can be reduced. In addition, since the process of depositing titanium nitride (TiN) is not performed, the process is simplified, and thus the production yield of the device may be improved.

제 1A 및 제 1B 도는 본 발명에 따른 반도체 소자의 베리어 금속층 형성방법을 설명하기 위한 소자의 단면도.1A and 1B are cross-sectional views of a device for explaining a method for forming a barrier metal layer of a semiconductor device according to the present invention.

* 도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings

1: 실리콘기판 2: 접합영역1: silicon substrate 2: junction area

3: 절연막 4: 티타늄3: insulation film 4: titanium

4A: 티타늄나이트라이드 5: 티타늄실리콘층4A: titanium nitride 5: titanium silicon layer

Claims (3)

접합영역이 형성된 실리콘기판상에 절연층을 형성하고, 상기 접합영역이 노출되도록 상기 절연층을 패터닝하여 콘택홀을 형성시킨 상태에서, 전체 상부면에 티타늄을 증착하는 단계와,Forming an insulating layer on the silicon substrate on which the junction region is formed, and depositing titanium on the entire upper surface with the contact layer formed by patterning the insulating layer to expose the junction region; 상기 티타늄의 상부 표면을 티타늄나이트라이드로 변화시키며, 상기 티타늄막과 상기 실리콘 기판의 계면에 티타늄실리콘층이 형성되도록 질소 분위기에서 1차 급속 열처리공정을 실시하는 단계와,Changing the upper surface of the titanium to titanium nitride, and performing a first rapid heat treatment process in a nitrogen atmosphere to form a titanium silicon layer at an interface between the titanium film and the silicon substrate; 상기 티타늄 실리콘층의 비저항값을 감소시키기 위하여 상기 1차 급속 열처리 공정보다 높은 온도로 2차 급속 열처리공정을 실시하는 단계로 이루어지는 것을 특징으로 하는 반도체 소자의 베리어 금속층 형성방법.And performing a second rapid heat treatment process at a temperature higher than that of the first rapid heat treatment process to reduce the resistivity of the titanium silicon layer. 제 1 항에 있어서,The method of claim 1, 상기 1차 급속 열처리공정은 600 내지 700℃의 저온 및 N2또는 NH3가스 분위기 상태에서 실시되는 것을 특징으로 하는 반도체 소자의 베리어 금속층 형성방법.The first rapid heat treatment process is a method of forming a barrier metal layer of a semiconductor device, characterized in that the low temperature of 600 to 700 ℃ and N 2 or NH 3 gas atmosphere. 제 1 항에 있어서,The method of claim 1, 상기 2차 급속 열처리공정은 800 내지 1000℃의 고온에서 실시되는 것을 특징으로 하는 반도체 소자의 베리어 금속층 형성방법.The second rapid heat treatment process is a method for forming a barrier metal layer of a semiconductor device, characterized in that carried out at a high temperature of 800 to 1000 ℃.
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Publication number Priority date Publication date Assignee Title
JPH04186726A (en) * 1990-11-20 1992-07-03 Nec Corp Manufacture of semiconductor device

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04186726A (en) * 1990-11-20 1992-07-03 Nec Corp Manufacture of semiconductor device

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