JPS6384154A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS6384154A JPS6384154A JP22820386A JP22820386A JPS6384154A JP S6384154 A JPS6384154 A JP S6384154A JP 22820386 A JP22820386 A JP 22820386A JP 22820386 A JP22820386 A JP 22820386A JP S6384154 A JPS6384154 A JP S6384154A
- Authority
- JP
- Japan
- Prior art keywords
- film
- semiconductor device
- barrier
- aluminum
- nitriding
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 14
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 229910052751 metal Inorganic materials 0.000 claims abstract description 21
- 239000002184 metal Substances 0.000 claims abstract description 21
- 229910052721 tungsten Inorganic materials 0.000 claims abstract description 11
- 239000010937 tungsten Substances 0.000 claims abstract description 11
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims abstract description 9
- 230000008018 melting Effects 0.000 claims abstract description 7
- 238000002844 melting Methods 0.000 claims abstract description 7
- 238000005121 nitriding Methods 0.000 claims abstract description 7
- 239000012299 nitrogen atmosphere Substances 0.000 claims abstract 2
- 238000000034 method Methods 0.000 claims description 13
- 239000000758 substrate Substances 0.000 claims description 8
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 claims description 5
- 238000007740 vapor deposition Methods 0.000 claims description 3
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims 1
- 229910021529 ammonia Inorganic materials 0.000 claims 1
- 229910052750 molybdenum Inorganic materials 0.000 claims 1
- 239000011733 molybdenum Substances 0.000 claims 1
- 230000004888 barrier function Effects 0.000 abstract description 18
- 229910052782 aluminium Inorganic materials 0.000 abstract description 15
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 15
- 238000009792 diffusion process Methods 0.000 abstract description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 6
- 230000000694 effects Effects 0.000 abstract description 6
- 229910052681 coesite Inorganic materials 0.000 abstract description 3
- 229910052906 cristobalite Inorganic materials 0.000 abstract description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 3
- 239000000377 silicon dioxide Substances 0.000 abstract description 3
- 235000012239 silicon dioxide Nutrition 0.000 abstract description 3
- 229910052682 stishovite Inorganic materials 0.000 abstract description 3
- 229910052905 tridymite Inorganic materials 0.000 abstract description 3
- -1 tungsten nitride Chemical class 0.000 abstract description 2
- 239000010408 film Substances 0.000 abstract 4
- 239000010409 thin film Substances 0.000 abstract 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 16
- 229910052710 silicon Inorganic materials 0.000 description 16
- 239000010703 silicon Substances 0.000 description 16
- 238000010438 heat treatment Methods 0.000 description 4
- 150000004767 nitrides Chemical class 0.000 description 4
- 230000003993 interaction Effects 0.000 description 3
- CSDREXVUYHZDNP-UHFFFAOYSA-N alumanylidynesilicon Chemical compound [Al].[Si] CSDREXVUYHZDNP-UHFFFAOYSA-N 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- NXHILIPIEUBEPD-UHFFFAOYSA-H tungsten hexafluoride Chemical compound F[W](F)(F)(F)(F)F NXHILIPIEUBEPD-UHFFFAOYSA-H 0.000 description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 229910001873 dinitrogen Inorganic materials 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 239000002244 precipitate Substances 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 150000003376 silicon Chemical class 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000001947 vapour-phase growth Methods 0.000 description 1
Abstract
Description
【発明の詳細な説明】
[発明の目的]
(産業上の利用分野)
この発明は半導体装置の製造方法に関し、特に半導体装
置の配線接続方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for connecting wiring of a semiconductor device.
(従来の技術)
従来、例えばシリコン基板上に半導体装置を形成する場
合、シリコン基板あるいはシリコン配線とアルミニウム
配線の接続をおこなう場合、シリコンとアルミニウムの
後熱工程での相互反応を防止するため以下の様な各方法
がとられていた。(Prior Art) Conventionally, for example, when forming a semiconductor device on a silicon substrate, or when connecting a silicon substrate or silicon wiring to an aluminum wiring, the following steps have been taken to prevent interaction between silicon and aluminum during a post-heating process. Various methods were used.
■アルミニウム中に後熱工程温度における過飽和シリコ
ンをあらかじめ含有させる。■Pre-contain supersaturated silicon at the post-heating process temperature in aluminum.
■シリコンとアルミニウムの接触面に拡散・反応障壁と
してのバリア・メタル、例えば数千オングストローム厚
の高融点金属膜を介在させる。■A barrier metal, for example, a high melting point metal film several thousand angstroms thick, is interposed at the interface between silicon and aluminum to act as a diffusion/reaction barrier.
(発明が解決しようとする問題点)
上記の■の方法は配線アルミニウム中にシリコンが過剰
に含まれているために配線中、あるいは接続孔でのシリ
コンの析出が問題となる。後熱工程を経たのちにこの様
に発生したシリコン析出部は配線寿命を著しく劣化させ
たり、コンタクト特性を大幅に劣化させるなど、半導体
装置の生産歩留りの低下、設計上の制約などの問題があ
った。(Problems to be Solved by the Invention) The above method (1) has a problem in that silicon is precipitated in the wiring or in the connection hole because silicon is excessively contained in the wiring aluminum. Silicon precipitates generated in this way after the post-heating process can significantly shorten the lifespan of interconnects and contact characteristics, leading to problems such as lower production yields and design constraints for semiconductor devices. Ta.
一方■の方法は基本的にはアルミニウムとシリコンの°
相互拡散を防止する方法である。On the other hand, method ■ basically uses aluminum and silicon.
This is a method to prevent mutual diffusion.
しかし、バリア・メタルの膜厚とその効果は密接な関係
を持っており、十分な膜厚がないとアルミニウムとシリ
コンの反応がみられる。However, the film thickness of the barrier metal and its effectiveness are closely related, and if the film is not thick enough, a reaction between aluminum and silicon will occur.
さらに上記バリア・メタルはピンホール的な欠陥を有し
ている場合があり、この欠陥を通した拡散現象がバリア
・メタルの性能を低下させる。Furthermore, the barrier metal may have defects such as pinholes, and the diffusion phenomenon through these defects degrades the performance of the barrier metal.
この様に従来のバリア・メタルは十分な膜厚の確保が必
要で半導体装置の製造コスト、時間の増大の一因となっ
ていた。As described above, it is necessary to ensure a sufficient film thickness for conventional barrier metals, which is one of the causes of increased manufacturing costs and time for semiconductor devices.
[発明の構成]
(問題点を解決するための手段)
本発明は以上の聞届に鑑みてなされたもので従来のバリ
ア・メタルの表面を金属窒化膜とすることで従来より薄
膜でも拡散・反応障壁効果のきわめて高いバリア・メタ
ルを有する配線接続方法を提供するものである。[Structure of the Invention] (Means for Solving the Problems) The present invention has been made in view of the above-mentioned findings, and by forming a metal nitride film on the surface of the conventional barrier metal, diffusion and diffusion can be achieved even with a thinner film than in the past. The present invention provides a wiring connection method using a barrier metal having an extremely high reaction barrier effect.
(作用)
本発明は従来のバリア・メタルの表面をアンモニアガス
あるいは窒素ガスで窒化し金属窒化膜を形成することに
より、膜の拡散・反応障壁効果を飛躍的に向上させたも
のである。(Function) The present invention dramatically improves the diffusion and reaction barrier effect of the film by nitriding the surface of a conventional barrier metal with ammonia gas or nitrogen gas to form a metal nitride film.
金属窒化膜は未窒化の金属に比べ一般に拡散・反応障壁
性が高いという事実を利用したものである。This method takes advantage of the fact that metal nitride films generally have higher diffusion and reaction barrier properties than non-nitrided metals.
(実施例)
以下、本発明の一実施例としてタングステンおよびその
窒化膜の選択成長を用いた例を第1図を用いて説明する
。(Example) Hereinafter, as an example of the present invention, an example using selective growth of tungsten and its nitride film will be described with reference to FIG.
例えば、P型シリコン基板(101)上に多結晶シリコ
ンゲート電極(103)とヒ素を拡散したソース・ドレ
ン電極(104) (拡散深さは例えば1700人)
を有するMOSFETを形成し、その上に絶縁膜として
気相成長法でSiO2膜(105)を5000人形成す
る。この後写真蝕刻法として反応性イオンエツチングを
用いて各電極接続孔(106)を形成する(第1図(a
))。For example, a polycrystalline silicon gate electrode (103) and arsenic-diffused source/drain electrodes (104) on a P-type silicon substrate (101) (diffusion depth is, for example, 1700 people)
A MOSFET having the following structure is formed, and 5,000 SiO2 films (105) are formed thereon as insulating films by vapor phase growth. Thereafter, each electrode connection hole (106) is formed using reactive ion etching as a photolithography method (Fig. 1(a)
)).
次に接続孔の開孔部分、すなわちシリコンの露出部分の
みに六弗化タングステンガスを用いた選択気相成長法を
利用して約300人のタングステン膜(107)を形成
する。Next, a tungsten film (107) of approximately 300 layers is formed only on the open portion of the contact hole, that is, on the exposed silicon portion, by selective vapor deposition using tungsten hexafluoride gas.
さらに例えば550℃のアンモニア・ガス雰囲気(アン
モニアガス分圧は例えばI Torr)で60分熱処理
することによりタングステン膜(107)上に約30人
のタングステン窒化膜(108)を形成した(第1図(
b))。Furthermore, a tungsten nitride film (108) of about 30 layers was formed on the tungsten film (107) by heat treatment for 60 minutes in an ammonia gas atmosphere (ammonia gas partial pressure is, for example, I Torr) at, for example, 550°C (Fig. 1). (
b)).
この後例えばアルミ純度99.9999%のターゲット
を用いてスパッタ法によりアルミニウム膜を8000人
形成し、これを写真蝕刻法と反応性イオンエツチングを
用いて配線(109)として加工したく第1図(C))
。After this, for example, using a target with an aluminum purity of 99.9999%, 8,000 aluminum films are formed by sputtering, and this is processed as wiring (109) using photolithography and reactive ion etching (see Figure 1). C))
.
以上のようにして製造した半導体装置を配線のアルミニ
ウムの焼ならしのため450℃で30分間熱処理したと
ころ、配線接続孔でのシリコンとアルミニウムの相互反
応は認められなかった。When the semiconductor device manufactured as described above was heat treated at 450° C. for 30 minutes to normalize the aluminum of the wiring, no interaction between silicon and aluminum was observed in the wiring connection hole.
一方、本実施例の如く窒化処理を行なわない場合はタン
グステン膜厚300人ではシリコン・アルミニウム反応
は著しく、本実施例の10倍の3000人のタングステ
ン膜を形成した場合にも部分的にシリコンとアルミニウ
ムの相互反応が観察され、接続部分でのコンタクト特性
の劣化が見られた。On the other hand, when nitriding is not performed as in this example, the silicon-aluminum reaction is significant at a tungsten film thickness of 300 people, and even when a tungsten film is formed with a thickness of 3,000 people, which is 10 times that of this example, some parts of the silicon-aluminum reaction occur. Interaction of aluminum was observed, and contact characteristics were degraded at the connection area.
なお、本実施例では六弗化タングステンガスを用いた選
択気相成長法を用いてタングステン膜の形成を行なった
が非選択の気相成長法、あるいはスパッタ法等により絶
縁膜(105)およびシリコン露出部分の双方にタング
ステン膜を形成しても良い。また、本発明の趣旨を逸脱
しない限り、その窒化条件、装置構造などが制限されな
いのはいうまでもない。In this example, the tungsten film was formed using selective vapor deposition using tungsten hexafluoride gas, but the insulating film (105) and silicon A tungsten film may be formed on both exposed portions. Furthermore, it goes without saying that the nitriding conditions, device structure, etc. are not limited as long as they do not depart from the spirit of the present invention.
[発明の効果コ
本発明により従来法に較べてより完全性の高いアルミニ
ウム配線とシリコンの拡散・反応障壁の容易な形成が可
能となり、半導体装置の性能向上および設計上の自由度
の増大、製造歩留りの向上が実現できた。[Effects of the Invention] The present invention enables the easy formation of more complete aluminum wiring and silicon diffusion/reaction barriers than conventional methods, improving the performance of semiconductor devices and increasing the degree of freedom in design and manufacturing. An improvement in yield was achieved.
第1図は本発明の一実施例を示す工程断面図である。
101・・・・・・P型シリコン基板
102・・・・・・ゲート絶縁膜
103・・・・・・多結晶シリコンゲート104・・・
・・・ソース拳ドレン電極105・・・・・・SiO2
膜
106・・・・・・接続孔FIG. 1 is a process sectional view showing an embodiment of the present invention. 101... P-type silicon substrate 102... Gate insulating film 103... Polycrystalline silicon gate 104...
...Source fist drain electrode 105...SiO2
Membrane 106... Connection hole
Claims (4)
とその上層配線を絶縁膜に形成された接続孔を介して接
続する方法において、前記基板または該基板上に形成さ
れた配線層の上層配線との接続面に高融点金属膜を形成
する第1の工程と、前記高融点金属膜表面をアンモニア
あるいはチッ素雰囲気で窒化する第2の工程とを備えた
ことを特徴とする半導体装置の製造方法。(1) In a method of connecting a semiconductor substrate or a wiring layer formed on the substrate and its upper layer wiring through a connection hole formed in an insulating film, the upper layer of the wiring layer formed on the substrate or the substrate A semiconductor device comprising a first step of forming a high melting point metal film on a connection surface with wiring, and a second step of nitriding the surface of the high melting point metal film in an ammonia or nitrogen atmosphere. Production method.
行うことを特徴とする特許請求の範囲第1項記載の半導
体装置の製造方法。(2) The method of manufacturing a semiconductor device according to claim 1, wherein the high melting point metal film is formed by selective vapor deposition.
を特徴とする特許請求の範囲第1項または第2項記載の
半導体装置の製造方法。(3) The method for manufacturing a semiconductor device according to claim 1 or 2, wherein the high melting point metal film is formed of tungsten.
特徴とする特許請求の範囲第1項または第2項記載の半
導体装置の製造方法。(4) The method for manufacturing a semiconductor device according to claim 1 or 2, wherein the high melting point metal film is formed of molybdenum.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP61228203A JP2554634B2 (en) | 1986-09-29 | 1986-09-29 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP61228203A JP2554634B2 (en) | 1986-09-29 | 1986-09-29 | Method for manufacturing semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS6384154A true JPS6384154A (en) | 1988-04-14 |
JP2554634B2 JP2554634B2 (en) | 1996-11-13 |
Family
ID=16872812
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP61228203A Expired - Fee Related JP2554634B2 (en) | 1986-09-29 | 1986-09-29 | Method for manufacturing semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2554634B2 (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01274454A (en) * | 1988-04-26 | 1989-11-02 | Seiko Epson Corp | Semiconductor and manufacture thereof |
JPH01298717A (en) * | 1988-05-27 | 1989-12-01 | Agency Of Ind Science & Technol | Manufacture of semiconductor device |
JPH09102544A (en) * | 1995-05-09 | 1997-04-15 | Matsushita Electric Ind Co Ltd | Semiconductor device and its manufacture |
JPH1056065A (en) * | 1997-06-02 | 1998-02-24 | Seiko Epson Corp | Semiconductor device and manufacturing method thereof |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS57153475A (en) * | 1981-03-17 | 1982-09-22 | Nec Corp | Multi layer electrode |
JPS58116750A (en) * | 1981-12-30 | 1983-07-12 | Fujitsu Ltd | Manufacture of semiconductor device |
JPS59210656A (en) * | 1983-05-16 | 1984-11-29 | Fujitsu Ltd | Semiconductor device |
JPS61120469A (en) * | 1984-11-16 | 1986-06-07 | Oki Electric Ind Co Ltd | Manufacture of electrode wiring |
JPS61133646A (en) * | 1984-12-03 | 1986-06-20 | Toshiba Corp | Manufacture of semiconductor device |
JPS62283625A (en) * | 1986-06-02 | 1987-12-09 | Fujitsu Ltd | Manufacture of electrode of semiconductor device |
-
1986
- 1986-09-29 JP JP61228203A patent/JP2554634B2/en not_active Expired - Fee Related
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS57153475A (en) * | 1981-03-17 | 1982-09-22 | Nec Corp | Multi layer electrode |
JPS58116750A (en) * | 1981-12-30 | 1983-07-12 | Fujitsu Ltd | Manufacture of semiconductor device |
JPS59210656A (en) * | 1983-05-16 | 1984-11-29 | Fujitsu Ltd | Semiconductor device |
JPS61120469A (en) * | 1984-11-16 | 1986-06-07 | Oki Electric Ind Co Ltd | Manufacture of electrode wiring |
JPS61133646A (en) * | 1984-12-03 | 1986-06-20 | Toshiba Corp | Manufacture of semiconductor device |
JPS62283625A (en) * | 1986-06-02 | 1987-12-09 | Fujitsu Ltd | Manufacture of electrode of semiconductor device |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01274454A (en) * | 1988-04-26 | 1989-11-02 | Seiko Epson Corp | Semiconductor and manufacture thereof |
JPH01298717A (en) * | 1988-05-27 | 1989-12-01 | Agency Of Ind Science & Technol | Manufacture of semiconductor device |
JPH09102544A (en) * | 1995-05-09 | 1997-04-15 | Matsushita Electric Ind Co Ltd | Semiconductor device and its manufacture |
JPH1056065A (en) * | 1997-06-02 | 1998-02-24 | Seiko Epson Corp | Semiconductor device and manufacturing method thereof |
Also Published As
Publication number | Publication date |
---|---|
JP2554634B2 (en) | 1996-11-13 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
LAPS | Cancellation because of no payment of annual fees |