JP3122845B2 - Method for forming metal wiring of semiconductor device - Google Patents
Method for forming metal wiring of semiconductor deviceInfo
- Publication number
- JP3122845B2 JP3122845B2 JP11290109A JP29010999A JP3122845B2 JP 3122845 B2 JP3122845 B2 JP 3122845B2 JP 11290109 A JP11290109 A JP 11290109A JP 29010999 A JP29010999 A JP 29010999A JP 3122845 B2 JP3122845 B2 JP 3122845B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- forming
- titanium nitride
- nitride film
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76861—Post-treatment or after-treatment not introducing additional chemical elements into the layer
- H01L21/76864—Thermal treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76846—Layer combinations
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
Description
【０００１】[0001]
【発明の属する技術分野】本発明は半導体装置の形成方
法に関し、特に拡散防止用金属層を含む金属配線の形成
方法に関する。The present invention relates to a method for forming a semiconductor device, and more particularly to a method for forming a metal wiring including a metal layer for preventing diffusion.
【０００２】[0002]
【従来の技術】近年、半導体装置の集積度が増加するこ
とにより配線設計が自由に容易に行われており、配線抵
抗及び電流容量等を自由にできる金属配線技術に関する
研究が活発になっている。一般に、半導体装置の金属配
線の材料としては低抵抗を有するアルミニウムが広く利
用されている。このようなアルミニウム配線は装置の集
積度が増加することによりその幅が微細化されるため、
電流密度が増加することになる。電流密度の増加は電子
移動、乱反射及びストレスの移動による配線の不良を起
こすことになり、これは結果的に半導体素子の信頼性を
低下させるという問題点が生じた。2. Description of the Related Art In recent years, as the degree of integration of semiconductor devices has increased, wiring design has been freely and easily performed, and research on metal wiring technology capable of freely setting wiring resistance, current capacity, and the like has been active. . In general, aluminum having a low resistance is widely used as a material of a metal wiring of a semiconductor device. Since the width of such aluminum wiring is miniaturized by increasing the degree of integration of the device,
The current density will increase. An increase in the current density causes a wiring failure due to electron transfer, diffuse reflection and stress transfer, which results in a problem that the reliability of the semiconductor device is reduced.
【０００３】上記の問題点を解決するために従来アルミ
ニウム配線膜上に銅（Ｃｕ）又はチタニウム（Ｔｉ）膜
等を積層して電子移動及びストレスの移動を減少させる
ことで、金属配線の断線を防止することができたが、ヒ
ロック（hillock）及びウィスカ（wisker）等の現象が
発生して配線の相互ショート及び絶縁膜破壊等の問題が
発生した。図２は従来の実施例によるもので、半導体素
子の金属配線形成工程でヒロック及びウィスカ等の問題
点を解決するために拡散防止膜を形成した後に金属配線
を形成した状態の断面図である。In order to solve the above-mentioned problems, a copper (Cu) or titanium (Ti) film or the like is conventionally stacked on an aluminum wiring film to reduce the movement of electrons and the movement of stress, thereby preventing disconnection of the metal wiring. Although it could be prevented, phenomena such as hillocks and whiskers occurred, causing problems such as mutual short-circuiting of wirings and breakdown of insulating films. FIG. 2 is a cross-sectional view showing a state in which a metal wiring is formed after a diffusion preventing film is formed in order to solve problems such as hillocks and whiskers in a metal wiring forming process of a semiconductor device according to a conventional example.
【０００４】この方法は図２に示すように、先ず、半導
体基板１上に絶縁膜２を形成した後、絶縁膜２の所定の
部位にコンタクトホールを形成する。コンタクトホール
を形成する段階でコンタクトホールは下部の半導体基板
１の表面が露出される深さで食刻される。そして、絶縁
膜２内の所定部分にコンタクトホールを含む構造物全面
に拡散防止膜としてチタニウム膜３とチタニウム窒化膜
４とを物理的気相蒸着法（ＰＶＤ：physical vapor dep
osition ）により順次積層する。その後、チタニウム窒
化膜４の上部に金属層８を形成する。In this method, as shown in FIG. 2, first, after an insulating film 2 is formed on a semiconductor substrate 1, a contact hole is formed in a predetermined portion of the insulating film 2. In forming the contact hole, the contact hole is etched to a depth where the surface of the lower semiconductor substrate 1 is exposed. Then, a titanium film 3 and a titanium nitride film 4 are formed as a diffusion preventing film on the entire surface of the structure including a contact hole in a predetermined portion in the insulating film 2 by physical vapor deposition (PVD).
osition). After that, a metal layer 8 is formed on the titanium nitride film 4.
【０００５】[0005]
【発明が解決しようとする課題】しかし、現在高集積化
が進んだことにより、コンタクトホールの大きさが減少
し、これに比例してコンタクトホールの段差が相対的に
増加することになった。従って、上記のように拡散防止
膜を物理的気相蒸着法により積層して金属配線を形成す
る場合、ステップカバレージ（step coverage ）が減少
して拡散防止膜がコンタクトホール下部に均一に蒸着で
きず、更に金属層の厚さが増加した場合にコンタクトホ
ール上部の角部分に陰影効果（shadow effect ）が増加
して後続工程の遂行が不可能となった。However, as the degree of integration becomes higher at present, the size of the contact hole is reduced, and the step of the contact hole is relatively increased in proportion thereto. Therefore, when the metal wiring is formed by stacking the diffusion barrier film by the physical vapor deposition method as described above, the step coverage is reduced and the diffusion barrier film cannot be uniformly deposited under the contact hole. In addition, when the thickness of the metal layer is further increased, a shadow effect is increased at a corner portion above the contact hole, so that a subsequent process cannot be performed.
【０００６】又、拡散防止膜のステップカバレージを向
上するために化学気相蒸着法を使用し、ＴｉＣｌ4を原
料ガスとしてチタニウム膜を形成し、更にＴｉＣｌ4と
ＮＨ3とを反応させてチタニウム窒化膜とする場合、チ
タニウム窒化膜内にパーティクル（particle）が発生し
て素子の歩留り低下及び装置の信頼性が低下するという
問題点があった。又、上記チタニウム窒化膜の蒸着時に
チタニウム窒化膜の相が非晶質であるためにチタニウム
窒化膜の内部の抵抗が増加して装置の電導スピードが落
ちるという問題点があった。従って、本発明の目的は拡
散防止膜のステップカバレージを向上させ、拡散防止膜
内部の抵抗及び拡散防止膜のパーティクルを減少させる
ことにより、半導体装置の歩留り及び信頼性を向上する
ことのできる半導体装置の金属配線形成方法を提供する
ことにある。Further, in order to improve the step coverage of the diffusion preventing film, a titanium film is formed using TiCl 4 as a source gas by using a chemical vapor deposition method, and the titanium nitride is reacted by reacting TiCl 4 with NH 3. In the case of a film, there is a problem that particles are generated in the titanium nitride film, thereby lowering the yield of the device and the reliability of the device. In addition, since the phase of the titanium nitride film is amorphous during the deposition of the titanium nitride film, the internal resistance of the titanium nitride film increases and the conduction speed of the device decreases. Accordingly, an object of the present invention is to improve the step coverage of a diffusion barrier film and reduce the resistance inside the diffusion barrier film and particles of the diffusion barrier film, thereby improving the yield and reliability of the semiconductor device. Another object of the present invention is to provide a method for forming a metal wiring.
【０００７】[0007]
【課題を解決するための手段】上記の本発明の目的を達
成するために、本発明の方法は、先ず、絶縁膜が形成さ
れた半導体基板上の所定部位にコンタクトホールを形成
した後、コンタクトホールを含む絶縁膜全面にチタニウ
ム膜とチタニウム窒化膜とを化学気相蒸着法により所定
厚さで順次形成し、その後、形成されたチタニウム窒化
膜を窒素雰囲気中で熱処理して、窒素含有量と相とが異
なる三層構造のチタニウム窒化膜に相転移させる。その
後、コンタクトホール部分を電気的に連結させる金属配
線を形成する。本発明は上記金属配線を形成した後、ア
ーク薄膜を蒸着する工程を含むことも可能である。In order to achieve the above-mentioned object of the present invention, a method of the present invention firstly forms a contact hole in a predetermined portion on a semiconductor substrate on which an insulating film has been formed, and then forms a contact hole. A titanium film and a titanium nitride film are sequentially formed in a predetermined thickness by a chemical vapor deposition method on the entire surface of the insulating film including the holes, and thereafter, the formed titanium nitride film is heat-treated in a nitrogen atmosphere to obtain a nitrogen content and The phase is changed to a three-layered titanium nitride film having a different phase. Thereafter, a metal wiring for electrically connecting the contact holes is formed. The present invention can include a step of depositing an arc thin film after forming the metal wiring.
【０００８】[0008]
【発明の実施の形態】以下、添付図面を参照して本発明
の好ましい実施形態を説明する。図１の（ａ）乃至
（ｄ）は、本発明の実施例により金属配線を形成する工
程を示す断面図である。先ず、図１の（ａ）に示すよう
に、活性領域を含む半導体基板１の上部に絶縁膜２を蒸
着し、フォトリソグラフィ法により絶縁膜２の所定部分
にコンタクトホールが形成される。コンタクトホールは
絶縁膜２の所定部分が半導体基板１の表面が露出される
まで食刻されて形成される。Preferred embodiments of the present invention will be described below with reference to the accompanying drawings. FIGS. 1A to 1D are cross-sectional views showing steps of forming a metal wiring according to an embodiment of the present invention. First, as shown in FIG. 1A, an insulating film 2 is deposited on a semiconductor substrate 1 including an active region, and a contact hole is formed in a predetermined portion of the insulating film 2 by a photolithography method. The contact hole is formed by etching a predetermined portion of the insulating film 2 until the surface of the semiconductor substrate 1 is exposed.
【０００９】その後、図１の（ｂ）に示すように、上記
コンタクトホール内部及び絶縁膜２全面にチタニウム膜
を蒸着する。上記チタニウム膜３は、ＴｉＣｌ4を原料
ガスとして化学気相蒸着法（ＣＶＤ）により形成し、そ
れはコンタクトホールの形状を維持できるほどに充分薄
く形成する。上記化学気相蒸着法はコンタクトホール内
部のステップカバレージを向上させるための蒸着方法で
ある。その後、上記チタニウム膜３上部にチタニウム窒
化膜４を形成する。ここで、チタニウム窒化膜４はパー
ティクル発生を抑えるためにテトラジメチルアミノチタ
ニウム（Ｔｉ（Ｎ（ＣＨ3）2）4 ）又はテトラジエチル
アミノチタニウム（Ｔｉ（Ｎ（Ｃ2Ｈ5） 2 ）4 ）だけを
原料として化学気相蒸着法により蒸着され、チタニウム
窒化膜４を形成するときのキャリアガスはヘリウムなど
の不活性ガス、窒素又はこれらの混合ガスの中から適宜
に選ばれる。又、上記チタニウム窒化膜の蒸着時、温度
は３００乃至５００℃にし、圧力は５乃至１０ｍＴｏｒ
ｒの範囲で調節するが、この時に形成される膜質は非晶
質相である。Thereafter, as shown in FIG.
Titanium film inside contact hole and over the entire surface of insulating film 2
Is deposited. The titanium film 3 is made of TiClFourThe raw material
It is formed as a gas by chemical vapor deposition (CVD).
Is thin enough to maintain the shape of the contact hole
Formed. Above chemical vapor deposition method in contact hole
Deposition method to improve the step coverage of the part
is there. Thereafter, a titanium nitride film is formed on the titanium film 3.
An oxide film 4 is formed. Here, the titanium nitride film 4 is
Tetradimethylamino tita to reduce tickle generation
(Ti (N (CHThree)Two)Four ) Or tetradiethyl
Amino titanium (Ti (N (CTwoHFive) Two )Four Only)
Titanium is deposited as a raw material by chemical vapor deposition.
The carrier gas for forming the nitride film 4 is helium or the like.
Inert gas, nitrogen or a mixture of these as appropriate
Is chosen. In addition, when depositing the titanium nitride film,
Is between 300 and 500 ° C and the pressure is between 5 and 10 mTorr
r, but the quality of the film formed at this time is amorphous
It is a quality phase.
【００１０】次に、上記のような状態の層が形成された
半導体基板を窒素雰囲気中で４００乃至６００℃の温度
範囲で３０分乃至６０分の間熱処理した。この熱処理に
より上記チタニウム窒化膜４は物性が異なる３つのチタ
ニウム窒化膜に分かれる。即ち、図１（ｃ）に示すよう
に、下部層から非晶質の第１チタニウム窒化膜５、中間
層の結晶質の第２チタニウム窒化膜６及び窒素の豊富な
結晶質の第３チタニウム窒化膜７とに分かれる。又、上
記熱処理の代わりにＲＴＰ（rapid thermal process ）
法を利用する場合には温度範囲を７００乃至９００℃に
し、１０乃至３０秒の間熱処理を施す。Next, the semiconductor substrate on which the layer having the above-mentioned state is formed is heat-treated in a nitrogen atmosphere at a temperature of 400 to 600 ° C. for 30 to 60 minutes. By this heat treatment, the titanium nitride film 4 is divided into three titanium nitride films having different physical properties. That is, as shown in FIG. 1C, an amorphous first titanium nitride film 5, an intermediate crystalline second titanium nitride film 6, and a nitrogen-rich crystalline third titanium nitride film 5 are formed from the lower layer. It is divided into the membrane 7. Also, instead of the above heat treatment, RTP (rapid thermal process)
When using the method, the temperature range is set to 700 to 900 ° C., and the heat treatment is performed for 10 to 30 seconds.
【００１１】図１の（ｂ）に示した単一のチタニウム窒
化膜４は非晶質であるために抵抗が非常に高いが、単一
チタニウム窒化膜４が上記のような条件で熱処理により
各々の物性の異なる三層のチタニウム窒化膜に相転移さ
せることで、チタニウム窒化膜の内部抵抗を減少するこ
とができる。続いて、図１の（ｃ）に示すように、銅、
アルミニウムまたはこれらの合金を通常の物理的気相蒸
着法（ＰＶＤ）により上記の拡散防止膜（チタニウム窒
化膜）の全面に蒸着して金属層８を形成する。その後、
金属層８の上にアーク薄膜（arc-metal layer ）９を蒸
着する。上記アーク薄膜９は化学気相蒸着法により蒸着
される。このアーク薄膜９は、金属配線パターン形成用
フォトレジスト膜が露光されたとき、金属配線パターン
からの反射光を遮る役をする。アーク薄膜９の原料とし
てはテトラジメチルアミノチタニウム又はテトラジエチ
ルアミノチタニウムであり、蒸着温度は３００乃至４５
０℃である。アーク薄膜９の形成工程は場合によって省
略することもできる。The single titanium nitride film 4 shown in FIG. 1B has an extremely high resistance because it is amorphous. However, the single titanium nitride film 4 is heat-treated under the above-described conditions. The internal resistance of the titanium nitride film can be reduced by performing a phase transition to a three-layer titanium nitride film having different physical properties. Subsequently, as shown in FIG.
Aluminum or an alloy thereof is deposited on the entire surface of the diffusion preventing film (titanium nitride film) by ordinary physical vapor deposition (PVD) to form a metal layer 8. afterwards,
An arc-metal layer 9 is deposited on the metal layer 8. The arc thin film 9 is deposited by a chemical vapor deposition method. The arc thin film 9 plays a role of blocking light reflected from the metal wiring pattern when the photoresist film for forming a metal wiring pattern is exposed. The material of the arc thin film 9 is tetradimethylaminotitanium or tetradiethylaminotitanium, and the deposition temperature is 300 to 45.
0 ° C. The step of forming the arc thin film 9 may be omitted in some cases.
【００１２】その後、図１の（ｄ）に示すように、上記
金属層（８）をパターン化して金属配線パターンを形成
する。上記の実施形態で記述した金属層８は銅、アルミ
ニウムの合金で形成されたが、ダングステンのように電
導性の高い金属に代替することも可能である。以上の好
ましい実施の形態で詳細に説明したように、本発明は金
属配線工程において、拡散防止膜として、チタニウム膜
の上に形成するチタニウム窒化膜をチタニウムと窒素と
を含む原料の熱分解を利用して形成し、この単層のチタ
ニウム窒化膜を窒素雰囲気中で熱処理して特性の異なる
三層構造に相転移させることにより、ステップカバレー
ジを向上させ、チタニウム窒化膜の電気抵抗を減少し、
パーティクル生成を減少することができる。Thereafter, as shown in FIG. 1D, the metal layer (8) is patterned to form a metal wiring pattern. Although the metal layer 8 described in the above embodiment is formed of an alloy of copper and aluminum, it can be replaced with a metal having high conductivity such as dangsten. As described in detail in the above preferred embodiment, the present invention utilizes the thermal decomposition of a titanium nitride and a nitrogen-containing raw material as a diffusion prevention film in a metal wiring process. By heat-treating this single-layer titanium nitride film in a nitrogen atmosphere to cause a phase transition to a three-layer structure having different characteristics, step coverage is improved, and the electric resistance of the titanium nitride film is reduced.
Particle generation can be reduced.
【００１３】[0013]
【発明の効果】本発明の方法によれば、半導体装置の歩
留りと信頼性を向上し、その信号伝達速度を向上させる
という効果をもたらす。上記した本発明の特定実施形態
について図面を添付して説明したが、当業者によりこれ
についての修正及び変形をすることができる。従って、
特許請求の範囲は本発明の思想と範囲に属する限り全て
の修正と変形を含むものと理解することができる。According to the method of the present invention, the yield and reliability of a semiconductor device are improved, and the signal transmission speed is improved. Although the specific embodiments of the present invention have been described with reference to the drawings, those skilled in the art can make modifications and variations thereto. Therefore,
It can be understood that the appended claims include all modifications and variations as long as they fall within the spirit and scope of the present invention.
【図１】（ａ）乃至（ｄ）は本発明の実施形態により金
属配線を形成する工程を示す断面図である。FIGS. 1A to 1D are cross-sectional views illustrating a process of forming a metal wiring according to an embodiment of the present invention.
【図２】従来の金属配線を形成する方法を説明するため
の半導体装置の断面図である。FIG. 2 is a cross-sectional view of a semiconductor device for explaining a conventional method for forming a metal wiring.
１ 半導体基板 ２ 絶縁膜 ３ チタニウム膜 ４ チタニウム窒化膜 ５ 第１チタニウム窒化膜 ６ 第２チタニウム窒化膜 ７ 第３チタニウム窒化膜 ８ 金属層 ９ アーク薄膜 DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Insulating film 3 Titanium film 4 Titanium nitride film 5 First titanium nitride film 6 Second titanium nitride film 7 Third titanium nitride film 8 Metal layer 9 Arc thin film
───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 21/28 - 21/288 H01L 21/3205 - 21/3213 H01L 21/768 ──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. 7 , DB name) H01L 21/28-21/288 H01L 21/3205-21/3213 H01L 21/768
Claims (11)
形成する工程；上記絶縁膜が形成された半導体基板上部
の所定の部位にコンタクトホールを形成する工程；上記
コンタクトホールを含む絶縁膜に化学気相蒸着法により
チタニウム膜と、チタニウム窒化膜を所定厚さで順次形
成する工程；上記チタニウム窒化膜を窒素雰囲気中で熱
処理して窒素含有量と相が互いに異なる下部層，中間
層，上部層の三層構造で構成され、上記下部層は非晶質
状態、上記中間層は結晶質状態、上記上部層は窒素の豊
富な結晶質状態で存在するチタニウム窒化膜に相移転さ
せる工程；上記コンタクトホール部分を電気的に連結さ
せる金属線を形成する工程を含むことを特徴とする半導
体装置の金属配線形成方法。Forming an insulating film on a semiconductor substrate including an active region; forming a contact hole on a predetermined portion of the semiconductor substrate on which the insulating film is formed; Forming a titanium film and a titanium nitride film in order by a chemical vapor deposition method in a predetermined thickness; heat treating the titanium nitride film in a nitrogen atmosphere to form a lower layer, an intermediate layer, and an upper layer having different nitrogen contents and phases; The lower layer being in an amorphous state, the intermediate layer being in a crystalline state, and the upper layer being phase-transferred to a titanium nitride film present in a nitrogen-rich crystalline state; A method for forming a metal wiring of a semiconductor device, comprising a step of forming a metal line for electrically connecting a contact hole portion.
アミノチタニウムの化学気相蒸着法により形成されるこ
とを特徴とする請求項１記載の半導体装置の金属配線形
成方法。2. The method according to claim 1, wherein the titanium nitride film is formed by chemical vapor deposition of tetradimethylaminotitanium.
ミノチタニウムの化学気相蒸着法により形成されること
を特徴とする半導体装置の金属形成方法。3. The method for forming a metal of a semiconductor device according to claim 1, wherein said titanium nitride film is formed by a chemical vapor deposition method of tetradialaminotitanium.
０℃の温度、５乃至１０ｍＴｏｒｒの圧力の条件で形成
されることを特徴とする請求項２又は３記載の半導体装
置の金属配線形成方法。4. The method according to claim 1, wherein the titanium nitride film has a thickness of 300 to 50.
4. The method according to claim 2, wherein the semiconductor device is formed at a temperature of 0 [deg.] C. and a pressure of 5 to 10 mTorr.
熱処理は窒素雰囲気中で、４００乃至６００℃の温度範
囲で３０乃至６０分の間行うことを特徴とする請求項１
記載の半導体装置の金属配線形成方法。5. The heat treatment for phase transition of the titanium nitride film is performed in a nitrogen atmosphere at a temperature of 400 to 600 ° C. for 30 to 60 minutes.
A method for forming a metal wiring of a semiconductor device according to the above.
熱処理は窒素雰囲気中で７００乃至９００℃の温度範囲
で１０乃至３０秒の間行うことを特徴とする請求項１記
載の半導体装置の金属配線形成方法。6. The metal of the semiconductor device according to claim 1, wherein the heat treatment for phase transition of the titanium nitride film is performed in a nitrogen atmosphere at a temperature range of 700 to 900 ° C. for 10 to 30 seconds. Wiring formation method.
成されたことを特徴とする請求項１記載の半導体装置の
金属配線形成方法。7. The method according to claim 1, wherein said metal wiring is formed of aluminum or copper.
膜又は銅膜のパターン形成工程前に、アルミニウム膜又
は銅膜による反射を防止するためのアーク薄膜を形成す
る工程を含むことを特徴とする請求項７記載の半導体装
置の金属配線形成方法。8. The method according to claim 1, further comprising a step of forming an arc thin film for preventing reflection by the aluminum film or the copper film before the pattern forming process of the aluminum film or the copper film for forming the metal wiring. Item 8. The method for forming a metal wiring of a semiconductor device according to Item 7.
チタニウムの熱分解により形成されることを特徴とする
請求項８記載の半導体装置の金属配線形成方法。9. The method according to claim 8, wherein the arc thin film is formed by thermal decomposition of tetradimethylaminotitanium.
ノチタニウムの熱分解により形成されることを特徴とす
る請求項８記載の半導体装置の金属配線形成方法。10. The method according to claim 8, wherein the arc thin film is formed by thermal decomposition of tetradiethylaminotitanium.
５０℃であることを特徴とする請求項９又は１０記載の
半導体装置の金属配線形成方法。11. The temperature range of the thermal decomposition is 300 to 4
The method according to claim 9, wherein the temperature is 50 ° C. 11.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1995/P4447 | 1995-03-04 | ||
| KR1019950004447A KR0148325B1 (en) | 1995-03-04 | 1995-03-04 | Formation method of metal layer in semiconductor device |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8070955A Division JPH08250596A (en) | 1995-03-04 | 1996-03-04 | Metal wiring formation of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2000082742A JP2000082742A (en) | 2000-03-21 |
| JP3122845B2 true JP3122845B2 (en) | 2001-01-09 |
Family
ID=19409231
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8070955A Pending JPH08250596A (en) | 1995-03-04 | 1996-03-04 | Metal wiring formation of semiconductor device |
| JP11290109A Expired - Fee Related JP3122845B2 (en) | 1995-03-04 | 1999-10-12 | Method for forming metal wiring of semiconductor device |
Family Applications Before (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8070955A Pending JPH08250596A (en) | 1995-03-04 | 1996-03-04 | Metal wiring formation of semiconductor device |
Country Status (6)
| Country | Link |
|---|---|
| JP (2) | JPH08250596A (en) |
| KR (1) | KR0148325B1 (en) |
| CN (1) | CN1057868C (en) |
| DE (1) | DE19608208B4 (en) |
| GB (1) | GB2298657B (en) |
| TW (1) | TW288171B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3040715U (en) * | 1997-02-19 | 1997-08-26 | 株式会社熊谷 | Packaging bag |
Families Citing this family (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100430684B1 (en) * | 1996-12-31 | 2004-07-30 | 주식회사 하이닉스반도체 | Method of forming thermally stable metal line of semiconductor device using doubly or triply deposited amorphous and crystalline tungsten nitride layer |
| KR100480576B1 (en) * | 1997-12-15 | 2005-05-16 | 삼성전자주식회사 | Forming method of metal wiring in semiconductor device |
| KR100494320B1 (en) * | 1997-12-30 | 2005-08-31 | 주식회사 하이닉스반도체 | Diffusion prevention film formation method of semiconductor device |
| KR100559028B1 (en) * | 1998-12-29 | 2006-06-15 | 주식회사 하이닉스반도체 | Copper wiring formation method of semiconductor device |
| KR100495856B1 (en) * | 1998-12-30 | 2005-09-02 | 주식회사 하이닉스반도체 | Copper metal wiring formation method of semiconductor device |
| JP3562628B2 (en) * | 1999-06-24 | 2004-09-08 | 日本電気株式会社 | Diffusion barrier film, multilayer wiring structure, and method of manufacturing the same |
| US6569751B1 (en) * | 2000-07-17 | 2003-05-27 | Lsi Logic Corporation | Low via resistance system |
| DE10154500B4 (en) * | 2001-11-07 | 2004-09-23 | Infineon Technologies Ag | Process for the production of thin, structured, metal-containing layers with low electrical resistance |
| WO2004051726A1 (en) | 2002-11-29 | 2004-06-17 | Nec Corporation | Semiconductor device and its manufacturing method |
| JP4222841B2 (en) * | 2003-01-15 | 2009-02-12 | 三洋電機株式会社 | Manufacturing method of semiconductor device |
| TW200526806A (en) * | 2004-01-15 | 2005-08-16 | Tokyo Electron Ltd | Film-forming method |
| US7253501B2 (en) * | 2004-08-03 | 2007-08-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | High performance metallization cap layer |
| US20060113675A1 (en) * | 2004-12-01 | 2006-06-01 | Chung-Liang Chang | Barrier material and process for Cu interconnect |
| JP5204964B2 (en) * | 2006-10-17 | 2013-06-05 | ルネサスエレクトロニクス株式会社 | Manufacturing method of semiconductor device |
| CN101017793B (en) * | 2007-02-16 | 2013-06-05 | 上海集成电路研发中心有限公司 | A making method for diffusing blocking layer |
| CN101459174B (en) * | 2007-12-13 | 2010-07-07 | 和舰科技(苏州)有限公司 | Conductive structure for semiconductor chip and its producing method |
| CN102810504A (en) * | 2011-05-31 | 2012-12-05 | 无锡华润上华半导体有限公司 | Process for growing thick aluminium |
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| EP0174743A3 (en) * | 1984-09-05 | 1988-06-08 | Morton Thiokol, Inc. | Process for transition metal nitrides thin film deposition |
| EP0209654B1 (en) * | 1985-05-13 | 1994-12-14 | Kabushiki Kaisha Toshiba | Semiconductor device having wiring electrodes |
| US4998157A (en) * | 1988-08-06 | 1991-03-05 | Seiko Epson Corporation | Ohmic contact to silicon substrate |
| EP0448763A1 (en) * | 1990-03-30 | 1991-10-02 | Siemens Aktiengesellschaft | Process and apparatus for manufacturing conductive layers or structures for highly integrated circuits |
| US5136362A (en) * | 1990-11-27 | 1992-08-04 | Grief Malcolm K | Electrical contact with diffusion barrier |
| EP0514103A1 (en) * | 1991-05-14 | 1992-11-19 | STMicroelectronics, Inc. | Barrier metal process for sub-micron contacts |
| US5242860A (en) * | 1991-07-24 | 1993-09-07 | Applied Materials, Inc. | Method for the formation of tin barrier layer with preferential (111) crystallographic orientation |
| US5308655A (en) * | 1991-08-16 | 1994-05-03 | Materials Research Corporation | Processing for forming low resistivity titanium nitride films |
| US5462895A (en) * | 1991-09-04 | 1995-10-31 | Oki Electric Industry Co., Ltd. | Method of making semiconductor device comprising a titanium nitride film |
| JPH05121378A (en) * | 1991-10-29 | 1993-05-18 | Sony Corp | Method of manufacturing semiconductor device |
| US5254499A (en) * | 1992-07-14 | 1993-10-19 | Micron Technology, Inc. | Method of depositing high density titanium nitride films on semiconductor wafers |
| JP2570576B2 (en) * | 1993-06-25 | 1997-01-08 | 日本電気株式会社 | Method for manufacturing semiconductor device |
| US5494860A (en) * | 1995-03-14 | 1996-02-27 | International Business Machines Corporation | Two step annealing process for decreasing contact resistance |
-
1995
- 1995-03-04 KR KR1019950004447A patent/KR0148325B1/en not_active IP Right Cessation
-
1996
- 1996-03-04 JP JP8070955A patent/JPH08250596A/en active Pending
- 1996-03-04 CN CN96104048A patent/CN1057868C/en not_active Expired - Fee Related
- 1996-03-04 TW TW085102622A patent/TW288171B/zh active
- 1996-03-04 DE DE19608208A patent/DE19608208B4/en not_active Expired - Fee Related
- 1996-03-04 GB GB9604614A patent/GB2298657B/en not_active Expired - Fee Related
-
1999
- 1999-10-12 JP JP11290109A patent/JP3122845B2/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3040715U (en) * | 1997-02-19 | 1997-08-26 | 株式会社熊谷 | Packaging bag |
Also Published As
| Publication number | Publication date |
|---|---|
| DE19608208A1 (en) | 1996-09-05 |
| DE19608208B4 (en) | 2006-02-23 |
| JP2000082742A (en) | 2000-03-21 |
| GB9604614D0 (en) | 1996-05-01 |
| KR0148325B1 (en) | 1998-12-01 |
| TW288171B (en) | 1996-10-11 |
| GB2298657A (en) | 1996-09-11 |
| GB2298657B (en) | 1998-09-30 |
| CN1057868C (en) | 2000-10-25 |
| KR960035843A (en) | 1996-10-28 |
| CN1141506A (en) | 1997-01-29 |
| JPH08250596A (en) | 1996-09-27 |
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