JPH08250596A - Metal wiring formation of semiconductor device - Google Patents
Metal wiring formation of semiconductor deviceInfo
- Publication number
- JPH08250596A JPH08250596A JP8070955A JP7095596A JPH08250596A JP H08250596 A JPH08250596 A JP H08250596A JP 8070955 A JP8070955 A JP 8070955A JP 7095596 A JP7095596 A JP 7095596A JP H08250596 A JPH08250596 A JP H08250596A
- Authority
- JP
- Japan
- Prior art keywords
- film
- forming
- metal wiring
- semiconductor device
- titanium nitride
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 229910052751 metal Inorganic materials 0.000 title claims abstract description 47
- 239000002184 metal Substances 0.000 title claims abstract description 47
- 239000004065 semiconductor Substances 0.000 title claims abstract description 32
- 230000015572 biosynthetic process Effects 0.000 title claims 3
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims abstract description 43
- 238000000034 method Methods 0.000 claims abstract description 36
- 239000010936 titanium Substances 0.000 claims abstract description 19
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims abstract description 16
- 229910052719 titanium Inorganic materials 0.000 claims abstract description 16
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims abstract description 14
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 229910052782 aluminium Inorganic materials 0.000 claims abstract description 9
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims abstract description 9
- 239000012299 nitrogen atmosphere Substances 0.000 claims abstract description 8
- 239000010949 copper Substances 0.000 claims abstract description 7
- 229910052757 nitrogen Inorganic materials 0.000 claims abstract description 7
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 6
- 229910052802 copper Inorganic materials 0.000 claims abstract description 6
- 239000010408 film Substances 0.000 claims description 82
- 238000005229 chemical vapour deposition Methods 0.000 claims description 8
- 239000010409 thin film Substances 0.000 claims description 8
- 238000005979 thermal decomposition reaction Methods 0.000 claims description 6
- 230000007704 transition Effects 0.000 claims description 6
- 238000010438 heat treatment Methods 0.000 claims description 5
- 238000006243 chemical reaction Methods 0.000 claims description 2
- 238000009792 diffusion process Methods 0.000 abstract description 14
- 230000008569 process Effects 0.000 abstract description 7
- 239000002245 particle Substances 0.000 abstract description 5
- 230000002265 prevention Effects 0.000 abstract description 5
- 238000009413 insulation Methods 0.000 abstract 3
- 230000009466 transformation Effects 0.000 abstract 2
- 230000007261 regionalization Effects 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 16
- 230000004888 barrier function Effects 0.000 description 7
- 238000005240 physical vapour deposition Methods 0.000 description 4
- 238000007740 vapor deposition Methods 0.000 description 4
- 238000000151 deposition Methods 0.000 description 3
- 230000010354 integration Effects 0.000 description 3
- 239000002994 raw material Substances 0.000 description 3
- 230000008021 deposition Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 238000013508 migration Methods 0.000 description 2
- 230000005012 migration Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000000704 physical effect Effects 0.000 description 2
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000001307 helium Substances 0.000 description 1
- 229910052734 helium Inorganic materials 0.000 description 1
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 1
- 230000001788 irregular Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76861—Post-treatment or after-treatment not introducing additional chemical elements into the layer
- H01L21/76864—Thermal treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76846—Layer combinations
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は半導体装置の形成方
法に関し、特に拡散防止用金属層を含む金属配線の形成
方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a semiconductor device, and more particularly to a method of forming a metal wiring including a diffusion preventing metal layer.
【０００２】[0002]
【従来の技術】近年、半導体装置の集積度が増加するこ
とにより配線設計が自由に容易に行われており、配線抵
抗及び電流容量等を自由にできる金属配線技術に関する
研究が活発になっている。一般に、半導体装置の金属配
線の材料としては低抵抗を有するアルミニウムが広く利
用されている。このようなアルミニウム配線は装置の集
積度が増加することによりその幅が微細化されるため、
電流密度が増加することになる。電流密度の増加は電子
移動、乱反射及びストレスの移動による配線の不良を起
こすことになり、これは結果的に半導体素子の信頼性を
低下させるという問題点を発生した。2. Description of the Related Art In recent years, wiring design has been freely and easily performed due to an increase in the degree of integration of semiconductor devices, and researches on metal wiring technology capable of freely setting wiring resistance and current capacity have become active. . Generally, aluminum having a low resistance is widely used as a material for metal wiring of a semiconductor device. Such an aluminum wiring is miniaturized in width due to an increase in the degree of integration of the device.
The current density will increase. The increase of the current density causes the defects of the wiring due to the movement of electrons, the irregular reflection and the movement of stress, resulting in a problem that the reliability of the semiconductor device is deteriorated.
【０００３】上記の問題点を解決するために従来アルミ
ニウム配線膜上に銅（Ｃｕ）又はチタニウム（Ｔｉ）膜
等を積層して電子移動及びストレスの移動を減少させる
ことで、金属配線の断線を防止することができたが、ヒ
ロック（ｈｉｌｌｏｃｋ）及びウィスカ（ｗｈｉｓｋｅ
ｒ）等の現象が発生して配線の相互ショート及び絶縁膜
破壊等の問題が発生した。図２は従来の実施例によるも
ので、半導体素子の金属配線形成工程でヒロック及びウ
ィスカ等の問題点を解決するために拡散防止膜を形成し
た後に金属配線を形成した状態の断面図である。In order to solve the above-mentioned problems, a copper (Cu) or titanium (Ti) film or the like is laminated on an aluminum wiring film in the related art to reduce electron migration and stress migration, thereby breaking the metal wiring. It could have been prevented, but hillocks and whiskers
The phenomenon such as r) occurs, and problems such as mutual short-circuiting of wiring and breakdown of the insulating film occur. FIG. 2 is a cross-sectional view of a conventional embodiment, in which a metal wiring is formed after a diffusion prevention film is formed in order to solve problems such as hillocks and whiskers in a metal wiring forming process of a semiconductor device.
【０００４】この方法は図２に示すように、先ず、半導
体基板１上に絶縁膜２を形成した後、絶縁膜２の所定の
部位にコンタクトホールを形成する。コンタクトホール
を形成する段階でコンタクトホールは下部の半導体基板
１の表面が露出される深さで食刻される。そして、絶縁
膜２内の所定部分にコンタクトホールを含む構造物全面
に拡散防止膜としてチタニウム膜３とチタニウム窒化膜
４とを物理的気相蒸着法（ＰＶＤ：ｐｈｙｓｉｃａｌ
ｖａｐｏｒ ｄｅｐｏｓｉｔｉｏｎ）により順次積層す
る。その後、チタニウム窒化膜４の上部に金属層８を形
成する。According to this method, as shown in FIG. 2, first, an insulating film 2 is formed on a semiconductor substrate 1, and then a contact hole is formed at a predetermined portion of the insulating film 2. At the stage of forming the contact hole, the contact hole is etched to a depth where the surface of the lower semiconductor substrate 1 is exposed. Then, a titanium film 3 and a titanium nitride film 4 as diffusion preventing films are formed on the entire surface of the structure including a contact hole at a predetermined portion in the insulating film 2 by a physical vapor deposition method (PVD: physical).
The layers are sequentially laminated by vapor deposition. After that, the metal layer 8 is formed on the titanium nitride film 4.
【０００５】[0005]
【発明が解決しようとする課題】しかし、現在高集積化
が進んだことにより、コンタクトホールの大きさが減少
し、これに比例してコンタクトホールの段差が相対的に
増加することになった。従って、上記のように拡散防止
膜を物理的気相蒸着法により積層して金属配線を形成す
る場合、ステップガバレージ（ｓｔｅｐ ｃｏｖｅｒａ
ｇｅ）が減少して拡散防止膜がコンタクトホール下部に
均一に蒸着できず、更に金属層の厚さが増加した場合に
コンタクトホール上部の角部分に陰影効果（ｓｈａｄｏ
ｗ ｅｆｆｅｃｔ）が増加して後続工程の遂行が不可能
となった。However, due to the progress of high integration at present, the size of the contact hole is reduced, and the step difference of the contact hole is relatively increased in proportion thereto. Therefore, when the diffusion barrier layer is stacked by the physical vapor deposition method to form the metal wiring, the step coverage may be reduced.
ge) is reduced and the diffusion barrier film cannot be uniformly deposited under the contact hole, and when the thickness of the metal layer is further increased, a shadow effect may occur at a corner of the contact hole.
w effect) increased and it became impossible to perform the subsequent process.
【０００６】又、拡散防止膜のステップカバレージを向
上するために化学気相蒸着法を使用してＴｉＣｌ4 をＮ
Ｈ3 等と反応させる場合、チタニウム膜とチタニウム窒
化膜内にパーティクル（ｐａｒｔｉｃｌｅ）が発生して
素子の歩留り低下及び装置の信頼性が低下するという問
題点があった。又、上記チタニウム窒化膜の蒸着時にチ
タニウム窒化膜の相が非晶質であるためにチタニウム窒
化膜の内部の抵抗が増加して装置の電導スピードが落ち
るという問題点があった。従って、本発明の目的は拡散
防止膜のステップカバレージを向上させ、拡散防止膜内
部の抵抗及び拡散防止膜のパーティクルを減少させるこ
とにより、半導体装置の歩留り及び信頼性を向上するこ
とのできる半導体装置の金属配線形成方法を提供するこ
とにある。Also, in order to improve the step coverage of the diffusion barrier film, the chemical vapor deposition method is used to remove TiCl 4 into N 2 gas.
In the case of reacting with H 3 or the like, there is a problem that particles are generated in the titanium film and the titanium nitride film to reduce the yield of the device and the reliability of the device. In addition, since the phase of the titanium nitride film is amorphous during the deposition of the titanium nitride film, the internal resistance of the titanium nitride film increases, and the conduction speed of the device decreases. Therefore, an object of the present invention is to improve the step coverage of the diffusion barrier film, and to reduce the resistance inside the diffusion barrier film and the particles of the diffusion barrier film, thereby improving the yield and reliability of the semiconductor device. Another object of the present invention is to provide a metal wiring forming method.
【０００７】[0007]
【課題を解決するための手段】上記の本発明の目的を達
成するために、本発明の方法は、先ず、絶縁膜が形成さ
れた半導体基板上の所定部位にコンタクトホールを形成
した後、コンタクトホールを含む絶縁膜全面にチタニウ
ム膜とチタニウム窒化膜とを化学気相蒸着法により所定
厚さで順次形成し、その後、形成されたチタニウム窒化
膜を窒素雰囲気中で熱処理して、窒素含有量と相とが異
なる三層構造のチタニウム窒化膜に相転移させる。その
後、コンタクトホール部分を電気的に連結させる金属配
線を形成する。本発明は上記金属配線を形成した後、ア
ーク薄膜を蒸着する工程を含むことも可能である。In order to achieve the above-mentioned object of the present invention, the method of the present invention comprises first forming a contact hole at a predetermined site on a semiconductor substrate on which an insulating film is formed, and then forming a contact. A titanium film and a titanium nitride film are sequentially formed with a predetermined thickness by a chemical vapor deposition method on the entire surface of the insulating film including holes, and then the formed titanium nitride film is heat-treated in a nitrogen atmosphere to obtain a nitrogen content and A phase transition is made to a titanium nitride film having a three-layer structure having different phases. After that, metal wiring is formed to electrically connect the contact hole portions. The present invention may include a step of depositing an arc thin film after forming the metal wiring.
【０００８】[0008]
【発明の実施の形態】以下、添付図面を参照して本発明
の好ましい実施形態を説明する。図１の（ａ）乃至
（ｄ）は、本発明の実施例により金属配線を形成する工
程を示す断面図である。先ず、図１の（ａ）に示すよう
に、活性領域を含む半導体基板１の上部に絶縁膜２を蒸
着し、フォトリソグラフィ法により絶縁膜２の所定部分
にコンタクトホールが形成される。コンタクトホールは
絶縁膜２の所定部分が半導体基板１の表面が露出される
まで食刻されて形成される。BEST MODE FOR CARRYING OUT THE INVENTION Preferred embodiments of the present invention will be described below with reference to the accompanying drawings. 1A to 1D are cross-sectional views showing a process of forming a metal wiring according to an embodiment of the present invention. First, as shown in FIG. 1A, the insulating film 2 is deposited on the semiconductor substrate 1 including the active region, and a contact hole is formed in a predetermined portion of the insulating film 2 by photolithography. The contact hole is formed by etching a predetermined portion of the insulating film 2 until the surface of the semiconductor substrate 1 is exposed.
【０００９】その後、図１の（ｂ）に示すように、上記
コンタクトホール内部及び絶縁膜２全面にチタニウム膜
を蒸着する。上記チタニウム膜３はＴｉｃｌ4 とＮＨ3
またはＮＦ3 との反応により化学気相蒸着法（ＣＶＰ）
により形成し、それはコンタクトホールの形状を維持で
きるほどに充分薄く形成する。上記化学気相蒸着法はコ
ンタクトホール内部のステップカバレージを向上させる
ための蒸着方法である。その後、上記チタニウム膜３上
部にチタニウム窒化膜４を形成する。ここで、チタニウ
ム窒化膜４はパーティクル発生を抑えるためにテトラジ
メチルアミノチタニウム（Ｔｉ（Ｎ（ＣＨ3 ）2 ）4 ）
又はテトラジエチルアミノチタニウム（Ｔｉ（Ｎ（Ｃ2
Ｈ5 ）4 ）だけを原料として化学気相蒸着法により蒸着
され、チタニウム窒化膜４を形成するための供給ガスは
窒素及び／又はヘリウムである。又、上記チタニウム窒
化膜の蒸着時、温度は３００乃至５００℃にし、圧力は
５乃至１０ｍＴｏｒｒの範囲で調節するが、この時に形
成される膜質は非晶質相である。Thereafter, as shown in FIG. 1B, a titanium film is deposited inside the contact hole and on the entire surface of the insulating film 2. The titanium film 3 is Ticl 4 and NH 3
Or chemical vapor deposition (CVP) by reaction with NF 3.
And is formed thin enough to maintain the shape of the contact hole. The chemical vapor deposition method is a vapor deposition method for improving the step coverage inside the contact hole. After that, a titanium nitride film 4 is formed on the titanium film 3. Here, the titanium nitride film 4 is made of tetradimethylaminotitanium (Ti (N (CH 3 ) 2 ) 4 ) in order to suppress particle generation.
Or tetradiethylaminotitanium (Ti (N (C 2
The supply gas for forming the titanium nitride film 4 is nitrogen and / or helium, which is vapor-deposited by a chemical vapor deposition method using only H 5 ) 4 ) as a raw material. During the deposition of the titanium nitride film, the temperature is set to 300 to 500 ° C. and the pressure is adjusted to 5 to 10 mTorr. The film quality formed at this time is an amorphous phase.
【００１０】次に、上記のような状態の層が形成された
半導体基板を窒素雰囲気中で４００乃至６００℃の温度
範囲で３０分乃至６０分の間熱処理した。この熱処理に
より上記チタニウム窒化膜４は物性が異なる３つのチタ
ニウム窒化膜に分かれる。即ち、図１（ｃ）に示すよう
に、下部層から非晶質の第１チタニウム窒化膜５、中間
層の結晶質の第２チタニウム窒化膜６及び窒素の豊富な
結晶質の第３チタニウム窒化膜７とに分かれる。又、上
記熱処理の代わりにＲＴＰ（ｒａｐｉｄ ｔｈｅｒｍａ
ｌ ｐｒｏｃｅｓｓ）法を利用する場合には温度範囲を
７００乃至９００℃にし、１０乃至３０秒の間熱処理を
施す。Next, the semiconductor substrate on which the layer in the above-mentioned state was formed was heat-treated in a nitrogen atmosphere at a temperature range of 400 to 600 ° C. for 30 to 60 minutes. By this heat treatment, the titanium nitride film 4 is divided into three titanium nitride films having different physical properties. That is, as shown in FIG. 1C, from the lower layer to the amorphous first titanium nitride film 5, the intermediate second crystalline titanium nitride film 6 and the nitrogen-rich crystalline third titanium nitride film. The membrane 7 is divided. Also, instead of the above heat treatment, RTP (rapid thermal)
When the 1 process) is used, the temperature range is set to 700 to 900 ° C. and heat treatment is performed for 10 to 30 seconds.
【００１１】図１の（ｂ）に示した単一のチタニウム窒
化膜４は非晶質であるために抵抗が非常に高いが、単一
チタニウム窒化膜４が上記のような条件で熱処理により
各々の物性の異なる三層のチタニウム窒化膜に相転移さ
せることで、チタニウム窒化膜の内部抵抗を減少するこ
とができる。続いて、図１の（ｃ）に示すように、銅、
アルミニウムまたはこれらの合金を通常の物理的気相蒸
着法により上記の拡散防止膜（チタニウム窒化膜）の全
面に蒸着して金属層８を形成する。その後、金属層８の
上にアーク薄膜（ａｒｃ−ｍｅｔａｌ ｌａｙｅｒ）９
を蒸着する。上記アーク薄膜９は化学気相蒸着法により
蒸着される。このアーク薄膜９は、金属配線パターン形
成用フォトレジスト膜が露光されたとき、金属配線パタ
ーンからの反射光を遮る役をする。アーク薄膜９の原料
としてはテトラジメチルアミノチタニウム又はテトラジ
エチルアミノチタニウムであり、蒸着温度は３００乃至
４５０℃である。アーク薄膜９の形成工程は場合によっ
て省略することもできる。The single titanium nitride film 4 shown in FIG. 1B has a very high resistance because it is amorphous, but the single titanium nitride film 4 is heat-treated under the above-mentioned conditions. The internal resistance of the titanium nitride film can be reduced by performing the phase transition to the three-layer titanium nitride film having different physical properties. Then, as shown in FIG. 1C, copper,
Aluminum or an alloy thereof is vapor-deposited on the entire surface of the diffusion barrier film (titanium nitride film) by a normal physical vapor deposition method to form the metal layer 8. Then, an arc-metal layer 9 is formed on the metal layer 8.
Vapor deposition. The arc thin film 9 is deposited by a chemical vapor deposition method. The arc thin film 9 serves to block the light reflected from the metal wiring pattern when the metal wiring pattern forming photoresist film is exposed. The raw material of the arc thin film 9 is tetradimethylaminotitanium or tetradiethylaminotitanium, and the vapor deposition temperature is 300 to 450 ° C. The step of forming the arc thin film 9 may be omitted in some cases.
【００１２】その後、図１の（ｄ）に示すように、上記
金属層（３、５、６、７、８、９）をパターン化して金
属配線パターンを形成する。上記の実施形態で記述した
金属層８は銅、アルミニウムの合金で形成されたが、ダ
ングステンのように電導性の高い金属に代替することも
可能である。以上の好ましい実施形態で詳細に説明した
ように、本発明は金属配線工程において、拡散防止膜と
して、チタニウム膜の上に形成するチタニウム窒化膜を
チタニウムと窒素とを含む原料の熱分解を利用して形成
し、この単層のチタニウム窒化膜を窒素雰囲気中で熱処
理して特性の異なる三層構造に相転移させることによ
り、ステップカバレージを向上させ、チタニウム窒化膜
の電気抵抗を減少し、パーティクル生成を減少すること
ができる。Thereafter, as shown in FIG. 1D, the metal layers (3, 5, 6, 7, 8, 9) are patterned to form a metal wiring pattern. Although the metal layer 8 described in the above embodiment is formed of an alloy of copper and aluminum, it can be replaced with a metal having high conductivity such as dangsten. As described in detail in the above preferred embodiment, in the metal wiring process, the present invention utilizes a titanium nitride film formed on a titanium film as a diffusion prevention film by utilizing thermal decomposition of a raw material containing titanium and nitrogen. The single-layer titanium nitride film is heat treated in a nitrogen atmosphere to undergo a phase transition to a three-layer structure with different characteristics, improving step coverage, reducing the electrical resistance of the titanium nitride film, and generating particles. Can be reduced.
【００１３】[0013]
【発明の効果】これは結果的に装置の歩留りと信頼性を
向上し、信号伝達速度を向上させるという効果をもたら
す。上記した本発明の特定実施形態について図面を添付
して説明したが、当業者によりこれについての修正及び
変形をすることができる。従って、特許請求の範囲は本
発明の思想と範囲に属する限り全ての修正と変形を含む
ものと理解することができる。As a result, the yield and reliability of the device are improved, and the signal transmission speed is improved. Although the specific embodiment of the present invention has been described with reference to the drawings, modifications and variations can be made by those skilled in the art. Therefore, the claims can be understood to include all modifications and variations as long as they fall within the spirit and scope of the present invention.
【図１】（ａ）乃至（ｄ）は本発明の実施形態により金
属配線を形成する工程を示す断面図である。1A to 1D are cross-sectional views showing a process of forming a metal wiring according to an embodiment of the present invention.
【図２】従来の金属配線を形成する方法を説明するため
の半導体装置の断面図である。FIG. 2 is a cross-sectional view of a semiconductor device for explaining a conventional method for forming metal wiring.
１ 半導体基板 ２ 絶縁膜 ３ チタニウム膜 ４ チタニウム窒化膜 ５ 第１チタニウム窒化膜 ６ 第２チタニウム窒化膜 ７ 第３チタニウム窒化膜 ８ 金属層 ９ アーク薄膜 1 Semiconductor Substrate 2 Insulating Film 3 Titanium Film 4 Titanium Nitride Film 5 First Titanium Nitride Film 6 Second Titanium Nitride Film 7 Third Titanium Nitride Film 8 Metal Layer 9 Arc Thin Film
Claims (13)
形成する工程；上記絶縁膜が形成された半導体基板上部
の所定の部位にコンタクトホールを形成する工程；上記
コンタクトホールを含む絶縁膜にチタニウム膜とチタニ
ウム窒化膜を所定厚さで順次形成する工程；上記チタニ
ウム窒化膜を窒素雰囲気中で熱処理して窒素含有量と相
が互いに異なる三層構造のチタニウム窒化膜に相転移さ
せる工程；上記コンタクトホール部分を電気的に連結さ
せる金属配線を形成する工程を含むことを特徴とする半
導体装置の金属配線形成方法。1. A step of forming an insulating film on a semiconductor substrate including an active region; a step of forming a contact hole at a predetermined portion of the semiconductor substrate on which the insulating film is formed; a step of forming an insulating film including the contact hole. A step of sequentially forming a titanium film and a titanium nitride film with a predetermined thickness; a step of heat-treating the titanium nitride film in a nitrogen atmosphere to cause a phase transition to a titanium nitride film having a three-layer structure having different nitrogen contents and phases; A method for forming a metal wiring of a semiconductor device, comprising the step of forming a metal wiring electrically connecting contact hole portions.
との反応による化学気相蒸着法により形成されることを
特徴とする請求項１記載の半導体装置の金属配線形成方
法。2. The titanium film comprises TiCl 4 and NH 3
2. The method for forming a metal wiring of a semiconductor device according to claim 1, wherein the method is formed by a chemical vapor deposition method by a reaction with.
アミノチタニウムの熱分解により形成されることを特徴
とする請求項１記載の半導体装置の金属配線形成方法。3. The method for forming a metal wiring of a semiconductor device according to claim 1, wherein the titanium nitride film is formed by thermal decomposition of tetradimethylaminotitanium.
アミノチタニウムの熱分解により形成されることを特徴
とする請求項１記載の半導体装置の金属配線形成方法。4. The method for forming a metal wiring of a semiconductor device according to claim 1, wherein the titanium nitride film is formed by thermal decomposition of tetradiethylaminotitanium.
０℃の温度、５乃至１０ｍＴｏｒｒの圧力の条件で形成
されることを特徴とする請求項３又は４記載の半導体装
置の金属配線形成方法。5. The titanium nitride film has a thickness of 300 to 50.
5. The method for forming metal wiring of a semiconductor device according to claim 3, wherein the metal wiring is formed under the conditions of a temperature of 0 ° C. and a pressure of 5 to 10 mTorr.
熱処理は窒素雰囲気中で、４００乃至６００℃の温度範
囲で３０乃至６０分の間行うことを特徴とする請求項１
記載の半導体装置の金属配線形成方法。6. The heat treatment for the phase transition of the titanium nitride film is performed in a nitrogen atmosphere at a temperature range of 400 to 600 ° C. for 30 to 60 minutes.
A method for forming a metal wiring of a semiconductor device as described above.
熱処理は窒素雰囲気中で７００乃至９００℃の温度範囲
で１０乃至３０秒の間行うことを特徴とする請求項１記
載の半導体装置の金属配線形成方法。7. The metal of the semiconductor device according to claim 1, wherein the heat treatment for the phase transition of the titanium nitride film is performed in a nitrogen atmosphere at a temperature range of 700 to 900 ° C. for 10 to 30 seconds. Wiring formation method.
成されたことを特徴とする請求項１記載の半導体装置の
金属配線形成方法。8. The method for forming a metal wiring of a semiconductor device according to claim 1, wherein the metal wiring is formed of aluminum or copper.
膜又は銅膜のパターン形成工程前に、アルミニウム膜又
は銅膜による反射を防止するためのアーク薄膜を形成す
る工程を含むことを特徴とする請求項８記載の半導体装
置の金属配線形成方法。9. A step of forming an arc thin film for preventing reflection by the aluminum film or the copper film before the step of forming the pattern of the aluminum film or the copper film for forming the metal wiring is included. Item 9. A method for forming metal wiring of a semiconductor device according to item 8.
ことを特徴とする請求項９記載の半導体装置の金属配線
形成方法。10. The method for forming metal wiring of a semiconductor device according to claim 9, wherein the arc thin film is a titanium film.
ミノチタニウムの熱分解により形成されることを特徴と
する請求項１０記載の半導体装置の金属配線形成方法。11. The method for forming a metal wiring of a semiconductor device according to claim 10, wherein the titanium film is formed by thermal decomposition of tetradimethylaminotitanium.
ミノチタニウムの熱分解により形成されることを特徴と
する請求項１０記載の半導体装置の金属配線形成方法。12. The method for forming a metal wiring of a semiconductor device according to claim 10, wherein the titanium film is formed by thermal decomposition of tetradiethylaminotitanium.
５０℃であることを特徴とする請求項１１又は１２記載
の半導体装置の金属配線形成方法。13. The thermal decomposition temperature range is 300 to 4
It is 50 degreeC, The metal wiring formation method of the semiconductor device of Claim 11 or 12 characterized by the above-mentioned.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950004447A KR0148325B1 (en) | 1995-03-04 | 1995-03-04 | Formation method of metal layer in semiconductor device |
| KR1995-4447 | 1995-03-04 |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11290109A Division JP3122845B2 (en) | 1995-03-04 | 1999-10-12 | Method for forming metal wiring of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH08250596A true JPH08250596A (en) | 1996-09-27 |
Family
ID=19409231
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8070955A Pending JPH08250596A (en) | 1995-03-04 | 1996-03-04 | Metal wiring formation of semiconductor device |
| JP11290109A Expired - Fee Related JP3122845B2 (en) | 1995-03-04 | 1999-10-12 | Method for forming metal wiring of semiconductor device |
Family Applications After (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11290109A Expired - Fee Related JP3122845B2 (en) | 1995-03-04 | 1999-10-12 | Method for forming metal wiring of semiconductor device |
Country Status (6)
| Country | Link |
|---|---|
| JP (2) | JPH08250596A (en) |
| KR (1) | KR0148325B1 (en) |
| CN (1) | CN1057868C (en) |
| DE (1) | DE19608208B4 (en) |
| GB (1) | GB2298657B (en) |
| TW (1) | TW288171B (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001007204A (en) * | 1999-06-24 | 2001-01-12 | Nec Corp | Structure of multilayer wiring and manufacture thereof |
| WO2005069358A1 (en) * | 2004-01-15 | 2005-07-28 | Tokyo Electron Limited | Film-forming method |
| KR100495856B1 (en) * | 1998-12-30 | 2005-09-02 | 주식회사 하이닉스반도체 | Copper metal wiring formation method of semiconductor device |
Families Citing this family (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100430684B1 (en) * | 1996-12-31 | 2004-07-30 | 주식회사 하이닉스반도체 | Method of forming thermally stable metal line of semiconductor device using doubly or triply deposited amorphous and crystalline tungsten nitride layer |
| JP3040715U (en) * | 1997-02-19 | 1997-08-26 | 株式会社熊谷 | Packaging bag |
| KR100480576B1 (en) * | 1997-12-15 | 2005-05-16 | 삼성전자주식회사 | Forming method of metal wiring in semiconductor device |
| KR100494320B1 (en) * | 1997-12-30 | 2005-08-31 | 주식회사 하이닉스반도체 | Diffusion prevention film formation method of semiconductor device |
| KR100559028B1 (en) * | 1998-12-29 | 2006-06-15 | 주식회사 하이닉스반도체 | Copper wiring formation method of semiconductor device |
| US6569751B1 (en) * | 2000-07-17 | 2003-05-27 | Lsi Logic Corporation | Low via resistance system |
| DE10154500B4 (en) * | 2001-11-07 | 2004-09-23 | Infineon Technologies Ag | Process for the production of thin, structured, metal-containing layers with low electrical resistance |
| JP4683188B2 (en) | 2002-11-29 | 2011-05-11 | 日本電気株式会社 | Semiconductor device and manufacturing method thereof |
| JP4222841B2 (en) * | 2003-01-15 | 2009-02-12 | 三洋電機株式会社 | Manufacturing method of semiconductor device |
| US7253501B2 (en) * | 2004-08-03 | 2007-08-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | High performance metallization cap layer |
| US20060113675A1 (en) * | 2004-12-01 | 2006-06-01 | Chung-Liang Chang | Barrier material and process for Cu interconnect |
| JP5204964B2 (en) * | 2006-10-17 | 2013-06-05 | ルネサスエレクトロニクス株式会社 | Manufacturing method of semiconductor device |
| CN101017793B (en) * | 2007-02-16 | 2013-06-05 | 上海集成电路研发中心有限公司 | A making method for diffusing blocking layer |
| CN101459174B (en) * | 2007-12-13 | 2010-07-07 | 和舰科技(苏州)有限公司 | Conductive structure for semiconductor chip and its producing method |
| CN102810504A (en) * | 2011-05-31 | 2012-12-05 | 无锡华润上华半导体有限公司 | Process for growing thick aluminium |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6169969A (en) * | 1984-09-05 | 1986-04-10 | モートン チオコール インコーポレーテツド | Vapor deposition of thin film of transition metal nitride |
| JPH05121378A (en) * | 1991-10-29 | 1993-05-18 | Sony Corp | Method of manufacturing semiconductor device |
| JPH0729853A (en) * | 1993-06-25 | 1995-01-31 | Nec Corp | Manufacture of semiconductor device |
Family Cites Families (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0209654B1 (en) * | 1985-05-13 | 1994-12-14 | Kabushiki Kaisha Toshiba | Semiconductor device having wiring electrodes |
| US4998157A (en) * | 1988-08-06 | 1991-03-05 | Seiko Epson Corporation | Ohmic contact to silicon substrate |
| EP0448763A1 (en) * | 1990-03-30 | 1991-10-02 | Siemens Aktiengesellschaft | Process and apparatus for manufacturing conductive layers or structures for highly integrated circuits |
| US5136362A (en) * | 1990-11-27 | 1992-08-04 | Grief Malcolm K | Electrical contact with diffusion barrier |
| EP0514103A1 (en) * | 1991-05-14 | 1992-11-19 | STMicroelectronics, Inc. | Barrier metal process for sub-micron contacts |
| US5242860A (en) * | 1991-07-24 | 1993-09-07 | Applied Materials, Inc. | Method for the formation of tin barrier layer with preferential (111) crystallographic orientation |
| US5308655A (en) * | 1991-08-16 | 1994-05-03 | Materials Research Corporation | Processing for forming low resistivity titanium nitride films |
| US5462895A (en) * | 1991-09-04 | 1995-10-31 | Oki Electric Industry Co., Ltd. | Method of making semiconductor device comprising a titanium nitride film |
| US5254499A (en) * | 1992-07-14 | 1993-10-19 | Micron Technology, Inc. | Method of depositing high density titanium nitride films on semiconductor wafers |
| US5494860A (en) * | 1995-03-14 | 1996-02-27 | International Business Machines Corporation | Two step annealing process for decreasing contact resistance |
-
1995
- 1995-03-04 KR KR1019950004447A patent/KR0148325B1/en not_active IP Right Cessation
-
1996
- 1996-03-04 TW TW085102622A patent/TW288171B/zh active
- 1996-03-04 GB GB9604614A patent/GB2298657B/en not_active Expired - Fee Related
- 1996-03-04 DE DE19608208A patent/DE19608208B4/en not_active Expired - Fee Related
- 1996-03-04 JP JP8070955A patent/JPH08250596A/en active Pending
- 1996-03-04 CN CN96104048A patent/CN1057868C/en not_active Expired - Fee Related
-
1999
- 1999-10-12 JP JP11290109A patent/JP3122845B2/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6169969A (en) * | 1984-09-05 | 1986-04-10 | モートン チオコール インコーポレーテツド | Vapor deposition of thin film of transition metal nitride |
| JPH05121378A (en) * | 1991-10-29 | 1993-05-18 | Sony Corp | Method of manufacturing semiconductor device |
| JPH0729853A (en) * | 1993-06-25 | 1995-01-31 | Nec Corp | Manufacture of semiconductor device |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100495856B1 (en) * | 1998-12-30 | 2005-09-02 | 주식회사 하이닉스반도체 | Copper metal wiring formation method of semiconductor device |
| JP2001007204A (en) * | 1999-06-24 | 2001-01-12 | Nec Corp | Structure of multilayer wiring and manufacture thereof |
| WO2005069358A1 (en) * | 2004-01-15 | 2005-07-28 | Tokyo Electron Limited | Film-forming method |
| KR100762525B1 (en) * | 2004-01-15 | 2007-10-01 | 동경 엘렉트론 주식회사 | Film-forming method |
| US7776742B2 (en) | 2004-01-15 | 2010-08-17 | Tokyo Electron Limited | Film-forming method |
| JP4787020B2 (en) * | 2004-01-15 | 2011-10-05 | 東京エレクトロン株式会社 | Deposition method |
Also Published As
| Publication number | Publication date |
|---|---|
| GB9604614D0 (en) | 1996-05-01 |
| KR0148325B1 (en) | 1998-12-01 |
| CN1141506A (en) | 1997-01-29 |
| GB2298657B (en) | 1998-09-30 |
| JP2000082742A (en) | 2000-03-21 |
| DE19608208B4 (en) | 2006-02-23 |
| CN1057868C (en) | 2000-10-25 |
| KR960035843A (en) | 1996-10-28 |
| TW288171B (en) | 1996-10-11 |
| DE19608208A1 (en) | 1996-09-05 |
| JP3122845B2 (en) | 2001-01-09 |
| GB2298657A (en) | 1996-09-11 |
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