KR0148325B1 - Formation method of metal layer in semiconductor device - Google Patents
Formation method of metal layer in semiconductor device Download PDFInfo
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- KR0148325B1 KR0148325B1 KR1019950004447A KR19950004447A KR0148325B1 KR 0148325 B1 KR0148325 B1 KR 0148325B1 KR 1019950004447 A KR1019950004447 A KR 1019950004447A KR 19950004447 A KR19950004447 A KR 19950004447A KR 0148325 B1 KR0148325 B1 KR 0148325B1
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- titanium nitride
- nitride film
- film
- forming
- titanium
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- 238000000034 method Methods 0.000 title claims abstract description 33
- 229910052751 metal Inorganic materials 0.000 title claims abstract description 29
- 239000002184 metal Substances 0.000 title claims abstract description 29
- 239000004065 semiconductor Substances 0.000 title claims abstract description 21
- 230000015572 biosynthetic process Effects 0.000 title 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims abstract description 44
- 239000010936 titanium Substances 0.000 claims abstract description 19
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims abstract description 17
- 229910052719 titanium Inorganic materials 0.000 claims abstract description 16
- 238000005229 chemical vapour deposition Methods 0.000 claims abstract description 13
- 238000000151 deposition Methods 0.000 claims abstract description 11
- 239000010408 film Substances 0.000 claims description 61
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 10
- 239000010409 thin film Substances 0.000 claims description 7
- 239000000758 substrate Substances 0.000 claims description 6
- 229910052757 nitrogen Inorganic materials 0.000 claims description 5
- 239000012299 nitrogen atmosphere Substances 0.000 claims description 2
- 230000004888 barrier function Effects 0.000 abstract description 13
- 238000009792 diffusion process Methods 0.000 abstract description 13
- 239000002245 particle Substances 0.000 abstract description 9
- 239000002994 raw material Substances 0.000 abstract description 5
- 230000008021 deposition Effects 0.000 abstract description 3
- 238000010438 heat treatment Methods 0.000 abstract description 3
- 238000004519 manufacturing process Methods 0.000 abstract description 3
- 238000005240 physical vapour deposition Methods 0.000 abstract description 3
- 239000012528 membrane Substances 0.000 abstract 1
- 229910052782 aluminium Inorganic materials 0.000 description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 6
- 239000010949 copper Substances 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- AZDRQVAHHNSJOQ-UHFFFAOYSA-N alumane Chemical group [AlH3] AZDRQVAHHNSJOQ-UHFFFAOYSA-N 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 239000001307 helium Substances 0.000 description 1
- 229910052734 helium Inorganic materials 0.000 description 1
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000000197 pyrolysis Methods 0.000 description 1
- 239000000376 reactant Substances 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 239000012808 vapor phase Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76861—Post-treatment or after-treatment not introducing additional chemical elements into the layer
- H01L21/76864—Thermal treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76846—Layer combinations
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
본 발명은 반도체 소자의 금속 배선 형성 방법 중 금속의 확산 방지층의 제조 방법에 관한 것으로 보다 구체적으로는 확산 방지층을 테트라디메틸아미노티타늄 등을 원료로 증착 후 열처리하여 삼중의 확산 방지층을 구성함으로써 금속 층의 스텝 커버리지 향상 및 파티클을 감소시키는 반도체 소자의 금속 배선 형성 방법에 관한 것으로서, 종래의 반도체 소자의 금속 배선은 확산 방지막으로서 티타늄막과 티타늄 질화막을 물리적 증착법에 의해 증착하므로써 미세한 콘택홀일수록 스텝 커버러지가 감소하고, 콘택홀 내벽에 고르게 증착되지 않으므로 그림자 현상이 발생하게 되고, 스텝 커버러지 특성이 좋은 화학 기상 증착에 의해 증착할 경우에는 파티클이 발생하고, 또한 티타늄 질화막 증착시 증착상태가 비정질막으로 형성되므로 인하여 막질의 저항이 증가하는 문제점이 있으므로, 본 발명은 스텝 커버러지 향상과 파티클 감소 및 저항을 감소하기 위하여 티타늄 질화막을 테트라디메틸아미노티타늄 또는 테트라디메틸아미노티타늄을 원료로 화학 기상 증착법에 의하여 증착하고, 열공정을 진행함으로써 비정질의 티타늄 질화막을 삼중의 티타늄 질화막으로 형성하여 막질의 저항을 감소시키고, 스텝 커버러지가 향상될 뿐만 아니라 파티클이 감소하여 소자의 수율 및 신뢰성을 향상시킬 수 있다.The present invention relates to a method for producing a metal diffusion barrier layer of the method of forming a metal wiring of a semiconductor device, and more specifically, to a metal layer by forming a triple diffusion barrier layer by depositing heat treatment after tetradimethylamino titanium, etc. as a raw material to form a diffusion barrier layer The present invention relates to a method for forming a metal wiring of a semiconductor device that improves step coverage and reduces particles, and the metal wiring of a conventional semiconductor device is a diffusion preventing film, and the step coverage is increased as fine contact holes are formed by depositing a titanium film and a titanium nitride film by physical vapor deposition. Since it is reduced, the shadow phenomenon occurs because it is not evenly deposited on the inner wall of the contact hole. Particles are generated when deposited by chemical vapor deposition with good step coverage properties, and the deposition state is formed as an amorphous film when the titanium nitride film is deposited. Due to the membrane In order to improve the step coverage, reduce particles and reduce resistance, the present invention is to deposit a titanium nitride film by chemical vapor deposition using tetradimethylaminotitanium or tetradimethylaminotitanium as a raw material, and to perform a thermal process. By proceeding, the amorphous titanium nitride film is formed into a triple titanium nitride film to reduce the film quality resistance, to improve step coverage, and to reduce particles, thereby improving the yield and reliability of the device.
Description
제1도는 종래의 반도체 소자의 금속 배선을 보인 단면도.1 is a cross-sectional view showing a metal wiring of a conventional semiconductor device.
제2도의 (a) 내지 (d)는 본 발명의 일 실시예의 제조방법을 설명하기 위한 각 제조방법에 있어서의 반도체 소자의 요부 단면도.(A)-(d) is sectional drawing of the principal part of the semiconductor element in each manufacturing method for demonstrating the manufacturing method of one Embodiment of this invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 반도체 기판 2 : 절연막1 semiconductor substrate 2 insulating film
3 : 티타늄막 4 : 티타늄 질화막3: titanium film 4: titanium nitride film
5 : 비정질 티타늄 질화막 6 : 결정질 티타늄 질화막5: amorphous titanium nitride film 6: crystalline titanium nitride film
7 : 질소가 풍부한 티타늄 질화막 8 : 금속층7: nitrogen-rich titanium nitride film 8: metal layer
9 : 아크 박막9: arc thin film
본 발명은 티타늄과 티타늄 질화막으로 확산 방지층을 구성하는 반도체 소자의 금속 배선 형성 방법에 관한 것으로, 보다 구체적으로는 확산 방지층을 화학 기상 증착법에 의해 증착하고, 티타늄 질화막을 열처리를 통하여 삼중의 방지층으로 구성함으로써 금속층의 스텝 커버러지를 향상시키고, 막질의 저항을 감소시키는 반도체 소자의 금속 배선 형성 방법에 관한 것이다.The present invention relates to a method for forming a metal wiring of a semiconductor device constituting a diffusion barrier layer of titanium and titanium nitride film, more specifically, to deposit a diffusion barrier layer by a chemical vapor deposition method, the titanium nitride film is composed of a triple barrier layer through heat treatment The present invention relates to a method for forming a metal wiring of a semiconductor device by improving the step coverage of the metal layer and reducing the film quality resistance.
최근 반도체 소자의 집적도가 증가함에 따라 배선 설계가 자유롭고 용이하며 배선 저항 및 전류용량 등의 설정을 여유있게 할 수 있는 금속 배선 기술에 관한 연구가 활발히 진행되고 있다.Recently, as the degree of integration of semiconductor devices increases, research on metallization technologies that can freely and easily design wiring and allow setting of wiring resistance and current capacity, etc., has been actively conducted.
일반적으로 반도체 금속 배선의 재료로는 저저항을 가지고 있는 알루미늄이 널리 이용되고 있는데 소자의 집적도가 증가함으로 인하여 배선의 폭이 미세화되어 전류 밀도의 증가로 인한 전자 이동, 난반사 및 스트레스의 이동이 배선의 불량을 야기시킴으로써 반도체 소자의 신뢰성을 저하시키는 문제점이 발생하였다. 상기의 문제점을 보완하기 위하여 알루미늄 배선막 상에 구리(Cu) 또는 티타늄(Ti) 등을 적층하여 전자이동 및 스트레스의 이동으로 인한 알루미늄의 단선은 방지할 수 있었지만, 힐록(hillock) 및 휘스커(whisker) 등의 현상이 발생하여 쇼트 및 절연막 파괴 등의 문제가 발생되었다. 따라서 반도체소자의 금속 배선 형성 공정에서는 힐록 및 휘스커 등의 문제점을 보완하기 위하여 종래에는 제1도에 도시된 바와 같이, 반도체 기판(1) 상부에 절연막(2)을 도포한 후, 소정의 부위에 콘택홀을 형성한 다음, 확산 방지막으로 티타늄(3)과 티타늄 질화막(4)을 물리적 기상 증착법(PVD : physical vapor deposition)에 의하여 적층하고, 그 상부에 금속 배선막(도시 안됨)을 형성하므로써 알루미늄 배선막의 배선 불량 및 힐록과 휘스커를 방지하였다.In general, aluminum having low resistance is widely used as a material for semiconductor metal wiring. As the degree of integration of devices increases, the width of the wiring becomes finer, and the movement of electrons, diffuse reflection, and stress caused by the increase of current density are caused by There arises a problem of lowering the reliability of the semiconductor device by causing a defect. In order to compensate for the above problems, aluminum (Cu) or titanium (Ti) may be stacked on the aluminum wiring layer to prevent disconnection of aluminum due to electron movement and stress movement, but hillock and whiskers may be prevented. Phenomena, such as), and short circuits and breakdown of the insulating layer. Accordingly, in order to compensate for problems such as hillock and whiskers in the process of forming a metal wiring of the semiconductor device, as shown in FIG. 1, the insulating film 2 is coated on the semiconductor substrate 1 and then applied to a predetermined portion. After forming the contact hole, the titanium (3) and the titanium nitride film (4) were laminated by physical vapor deposition (PVD) as a diffusion barrier, and a metal wiring film (not shown) was formed thereon to form aluminum. The wiring defect of the wiring film, the hillock, and the whisker were prevented.
그러나, 상기와 같이 확산 방지막을 물리적 기상 방법에 의해 적충하여 금속 배선을 이룰 경우, 콘택홀의 크기가 미세화 되어짐에 따라 이에 비례하여 콘택홀의 단차비가 증가하게 되고, 스텝 커버러지(step coverage)가 감소하여 확산 방지막이 콘택홀 하부에 고르게 증착되지 못하고, 금속층의 두께가 증가될 경우 콘택홀 상부의 모서리 부분에 그림자 효과(shadow effect)가 증가하게 되어 후속 공정의 진행이 불가능하게 된다.However, as described above, when the diffusion barrier is formed by the physical vapor phase method to form the metal wiring, as the size of the contact hole becomes smaller, the step ratio of the contact hole increases in proportion to this, and the step coverage decreases. If the diffusion barrier is not evenly deposited on the bottom of the contact hole, and the thickness of the metal layer is increased, the shadow effect is increased in the corner portion of the upper part of the contact hole, thereby making it impossible to proceed with the subsequent process.
또한, 확산 방지막의 스텝 커버러지를 향상시키기 위하여 화학 기상 증착법(CVD : chemical vapor deposition)을 사용하여 TiCl4를 NH3등과 반응시킬 경우, 티타늄 과 티타늄 질화막 내에 파티클이 발생되어 소자의 수를 저하 및 소자의 신뢰성이 감소하는 곤란을 수반하게 되었을 뿐만 아니라, 상기 티타늄 질화막이 증착시 증착상태가 비정질임을 감안하여 볼 때 막 내부의 저항이 증가하여 소자의 스피드가 떨어지게 된다.In addition, when TiCl 4 is reacted with NH 3 using chemical vapor deposition (CVD) to improve the step coverage of the diffusion barrier, particles are generated in the titanium and titanium nitride films to reduce the number of devices. In addition to the difficulty of reducing the reliability of the device, in view of the amorphous state of the deposition when the titanium nitride film is deposited, the internal resistance of the film is increased to reduce the speed of the device.
따라서, 본 발명이 목적은 확산 방지막의 스텝 커버러지를 향상시키고, 막 내부의 저항 및 파티클을 감소시키어 소자의 수율 및 신뢰성을 향상할 수 있는 반도체 소자의 금속 배선 형성방법을 제공하는데 에 있다.Accordingly, an object of the present invention is to provide a method for forming a metal wiring of a semiconductor device which can improve the step coverage of the diffusion barrier film and reduce the resistance and particles in the film to improve the yield and reliability of the device.
상기한 본 발명의 목적을 달성하기 위하여, 본 발명은 반도체 기판 상부에 산화막을 형성하고 소정부위에 콘택홀을 형성하는 반도체 소자에 있어서, 티타늄과 티타늄 질화막을 상기 콘택홀 및 산화막 전면에 화학 기상 증착법에 의해 증착하는 단계, 상기 티타늄 질화막을 열공정에 의하여 질소가 풍부한 티타늄 질화막과 결정질 티타늄 질화막과 비정질 티타늄 질화막을 형성하는 단계 및 금속 배선을 형성하는 단계로 이루어진 것을 특징으로 한다.In order to achieve the above object of the present invention, the present invention is a semiconductor device for forming an oxide film on a semiconductor substrate and forming a contact hole in a predetermined portion, the chemical vapor deposition method of titanium and titanium nitride film on the contact hole and the oxide film By depositing the titanium nitride film, forming a titanium nitride film, a crystalline titanium nitride film, an amorphous titanium nitride film, and a metal wiring by means of a thermal process.
또한 본 발명은 상기 금속 배선을 형성한 다음, 아크박막을 증착하는 단계를 포함하는 것을 특징으로 한다.In addition, the present invention is characterized in that it comprises the step of depositing an arc thin film after forming the metal wiring.
이하, 첨부한 도면에 의거하여 본 발명의 바람직한 실시 예를 자세히 설명하기로 한다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
먼저, 제2도 (a)에 도시된 바와 같이, 반도체 기판(1) 상부에 절연막(2)을 증착하고, 사진 식각 공정에 의하여 소정 부분에 콘택홀을 형성한다.First, as shown in FIG. 2A, an insulating film 2 is deposited on the semiconductor substrate 1, and contact holes are formed in predetermined portions by a photolithography process.
그 후, (b)에서 나타낸 바와 같이, 상기 콘택홀 내부 및 절연막(2) 전면에 티타늄막(3)을 증착한다. 상기 티타늄막(3)은 TiCl4과 NH3내지는 NF3와의 반응에 의하여 화학 기상 증착법에 의하여 형성한다. 상기 화학 기상 증착법은 콘택홀 내부의 스텝 커버러지를 향상시키기 위한 증착 방법이다. 그 후, 상기 티타늄막(3) 상부에 티타늄 질화막(4)을 형성한다. 이때, 상기 티타늄 질화막은 다른 반응물 없이 파티클 발생을 억제시키기 위하여 테트라디메틸아미노티타늄(Ti(N(CH3)2)4)) 또는 테트라디에틸아미노티타늄(Ti(N(C2H5)4) 만을 원료로 하여 화학 기상 증착법에 이하여 증착시키고, 전달용 가스로는 질소, 헬륨 모두 가능하다. 또한 상기 티타늄 질화막 증착시 온도는 300 내지 500℃로 하고, 압력은 5 내지 10mTorr 에서 실시하며, 막질의 상태는 거의 비정질 상태이다.Thereafter, as shown in (b), a titanium film 3 is deposited inside the contact hole and on the entire surface of the insulating film 2. The titanium film 3 is formed by chemical vapor deposition by the reaction of TiCl 4 with NH 3 or NF 3 . The chemical vapor deposition method is a deposition method for improving the step coverage inside the contact hole. Thereafter, a titanium nitride film 4 is formed on the titanium film 3. In this case, the titanium nitride film is tetradimethylaminotitanium (Ti (N (CH 3 ) 2 ) 4 )) or tetradiethylaminotitanium (Ti (N (C 2 H 5 ) 4 ) to suppress particle generation without other reactants. It can be deposited by chemical vapor deposition method using only as a raw material, and nitrogen or helium can be used as a delivery gas, and the temperature of the titanium nitride film is 300-500 ° C., the pressure is 5-10 mTorr, The state is almost amorphous.
그런 다음, (c)에 도시된 바와 같이, 상기와 같이 구성된 반도체 기판을 질소 분위기 하에서 400 내지 600℃의 온도 범위에서 30분 내지 60분 가열하면 상기 티타늄 질화막(4)은 하부로부터 비정질 티타늄 질화막(5)과 결정질 티타늄 질화막(6)과 질소가 풍부한 티타늄 질화막(7)으로 나누어진다. 또한 상기 열처리 대신 RTP(rapid thermal process) 방법을 이용할 경우에는 700 내지 900℃의 온도에서 10 내지 30sec로 진행한다. 상기와 같이 단일의 티타늄 질화막이 삼중의 티타늄 질화막으로 구성하게 된 것은 열분해에 의해 구성된 티타늄 질화막(4)은 비정질 상태이므로 저항이 매우 높으나, 열공정에 의하여 성질이 다른 상기 비정질 티타늄 질화막(5)과 결정질 티타늄 질화막(6)과 질소가 풍부한 티타늄 질화막(7)으로 구성되면 티타늄 질화막의 막 내부의 저항 감소의 효과가 크다. 그 후, 구리와 알루미늄이 합금으로 금속층(8)을 형성한 다음, 아크 박막(9)을 증착한다. 상기 아크 박막(9)은 화학 기상 증착법에 의해 증착하는데, 상기 아크 박막의 원료로는 테트라디메틸아미노티타늄 또는 테트라디에틸아미노티타늄을 이용하여 300 내지 450℃의 증착온도로 형성한다.Then, as shown in (c), when the semiconductor substrate constructed as described above is heated for 30 minutes to 60 minutes in a temperature range of 400 to 600 ° C. under a nitrogen atmosphere, the titanium nitride film 4 is formed from an amorphous titanium nitride film ( 5) and crystalline titanium nitride film 6 and nitrogen-rich titanium nitride film 7. In addition, when the rapid thermal process (RTP) method is used instead of the heat treatment, the process proceeds at 10 to 30 sec at a temperature of 700 to 900 ° C. As described above, the single titanium nitride film is composed of a triple titanium nitride film. The titanium nitride film 4 formed by pyrolysis has an extremely high resistance because it is in an amorphous state, but the amorphous titanium nitride film 5 having different properties by thermal process and When the crystalline titanium nitride film 6 and the nitrogen-rich titanium nitride film 7 are constituted, the effect of reducing the resistance inside the film of the titanium nitride film is large. Thereafter, copper and aluminum form a metal layer 8 from an alloy, and then an arc thin film 9 is deposited. The arc thin film 9 is deposited by chemical vapor deposition, and as the raw material of the arc thin film, tetradimethylamino titanium or tetradiethylamino titanium is formed at a deposition temperature of 300 to 450 ° C.
이 후,(d)에서와 같이, 상기 금속층(8)을 패턴화하여 금속배선을 이룬다.Thereafter, as in (d), the metal layer 8 is patterned to form metal wiring.
이상의 바람직한 실시 예에서 상세히 설명한 바와 같이, 본 발명은 금속 배선 공정시 확산 방지막으로 쓰이는 티타늄막과 티타늄 질화막의 스텝 커버러지를 향상시키고, 티타늄 질화막의 저항 감소 및 파티클을 감소시키기 위하여 화학 기상 증착법에 의하여 증착하고, 티타늄 질화막을 테트라디메틸아미노티타늄 또는 테트라디에틸아미노티타늄을 원료로 하여 열공정을 진행함으로써 저항이 적은 삼중의 티타늄 질화막을 형성하여 확산 방지막의 저항을 감소시켜 스피드 면이 개선되고, 스텝 커버러지가 향상될 뿐만 아니라 파티클이 감소하여 소자의 수율 및 신뢰성을 향상시킬 수 있다.As described in detail in the above-described preferred embodiment, the present invention is to improve the step coverage of the titanium film and titanium nitride film used as the diffusion barrier during the metal wiring process, to reduce the resistance of the titanium nitride film and to reduce the particles by chemical vapor deposition By depositing, the titanium nitride film is made of tetradimethylaminotitanium or tetradiethylaminotitanium as a raw material, and the thermal process is carried out to form a triple titanium nitride film having low resistance, thereby reducing the resistance of the diffusion barrier film and improving the speed surface. In addition to improved rubbing, particles can be reduced to improve device yield and reliability.
또한, 본 발명은 상기 실시 예에 한정되는 것은 아니다. 예를 들면, 상기 금속층은 구리, 알루미늄의 합금으로 이루어졌지만 텅스텐 등 전도성이 높은 금속을 사용하여 금속 배선을 이룰 수 있다.In addition, this invention is not limited to the said Example. For example, the metal layer is made of an alloy of copper and aluminum, but may be made of metal wiring using a highly conductive metal such as tungsten.
기타, 본 발명은 그 요지를 일탈하지 않는 범위에서 다양하게 변경하여 실시할 수 있다.In addition, this invention can be implemented in various changes within the range which does not deviate from the summary.
Claims (8)
Priority Applications (7)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950004447A KR0148325B1 (en) | 1995-03-04 | 1995-03-04 | Formation method of metal layer in semiconductor device |
| JP8070955A JPH08250596A (en) | 1995-03-04 | 1996-03-04 | Metal wiring formation of semiconductor device |
| CN96104048A CN1057868C (en) | 1995-03-04 | 1996-03-04 | Method of forming metal interconnects in semiconductor devices |
| DE19608208A DE19608208B4 (en) | 1995-03-04 | 1996-03-04 | Process for the preparation of metal interconnects in semiconductor devices |
| GB9604614A GB2298657B (en) | 1995-03-04 | 1996-03-04 | Methods of forming metal interconnects in semiconductor devices |
| TW085102622A TW288171B (en) | 1995-03-04 | 1996-03-04 | |
| JP11290109A JP3122845B2 (en) | 1995-03-04 | 1999-10-12 | Method for forming metal wiring of semiconductor device |
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| KR1019950004447A KR0148325B1 (en) | 1995-03-04 | 1995-03-04 | Formation method of metal layer in semiconductor device |
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| KR960035843A KR960035843A (en) | 1996-10-28 |
| KR0148325B1 true KR0148325B1 (en) | 1998-12-01 |
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| KR1019950004447A KR0148325B1 (en) | 1995-03-04 | 1995-03-04 | Formation method of metal layer in semiconductor device |
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| JP (2) | JPH08250596A (en) |
| KR (1) | KR0148325B1 (en) |
| CN (1) | CN1057868C (en) |
| DE (1) | DE19608208B4 (en) |
| GB (1) | GB2298657B (en) |
| TW (1) | TW288171B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100480576B1 (en) * | 1997-12-15 | 2005-05-16 | 삼성전자주식회사 | Forming method of metal wiring in semiconductor device |
| KR100494320B1 (en) * | 1997-12-30 | 2005-08-31 | 주식회사 하이닉스반도체 | Diffusion prevention film formation method of semiconductor device |
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| KR100430684B1 (en) * | 1996-12-31 | 2004-07-30 | 주식회사 하이닉스반도체 | Method of forming thermally stable metal line of semiconductor device using doubly or triply deposited amorphous and crystalline tungsten nitride layer |
| JP3040715U (en) * | 1997-02-19 | 1997-08-26 | 株式会社熊谷 | Packaging bag |
| KR100559028B1 (en) * | 1998-12-29 | 2006-06-15 | 주식회사 하이닉스반도체 | Copper wiring formation method of semiconductor device |
| KR100495856B1 (en) * | 1998-12-30 | 2005-09-02 | 주식회사 하이닉스반도체 | Copper metal wiring formation method of semiconductor device |
| JP3562628B2 (en) * | 1999-06-24 | 2004-09-08 | 日本電気株式会社 | Diffusion barrier film, multilayer wiring structure, and method of manufacturing the same |
| US6569751B1 (en) * | 2000-07-17 | 2003-05-27 | Lsi Logic Corporation | Low via resistance system |
| DE10154500B4 (en) * | 2001-11-07 | 2004-09-23 | Infineon Technologies Ag | Process for the production of thin, structured, metal-containing layers with low electrical resistance |
| WO2004051726A1 (en) | 2002-11-29 | 2004-06-17 | Nec Corporation | Semiconductor device and its manufacturing method |
| JP4222841B2 (en) * | 2003-01-15 | 2009-02-12 | 三洋電機株式会社 | Manufacturing method of semiconductor device |
| TW200526806A (en) * | 2004-01-15 | 2005-08-16 | Tokyo Electron Ltd | Film-forming method |
| US7253501B2 (en) * | 2004-08-03 | 2007-08-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | High performance metallization cap layer |
| US20060113675A1 (en) * | 2004-12-01 | 2006-06-01 | Chung-Liang Chang | Barrier material and process for Cu interconnect |
| JP5204964B2 (en) * | 2006-10-17 | 2013-06-05 | ルネサスエレクトロニクス株式会社 | Manufacturing method of semiconductor device |
| CN101017793B (en) * | 2007-02-16 | 2013-06-05 | 上海集成电路研发中心有限公司 | A making method for diffusing blocking layer |
| CN101459174B (en) * | 2007-12-13 | 2010-07-07 | 和舰科技(苏州)有限公司 | Conductive structure for semiconductor chip and its producing method |
| CN102810504A (en) * | 2011-05-31 | 2012-12-05 | 无锡华润上华半导体有限公司 | Process for growing thick aluminium |
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| EP0174743A3 (en) * | 1984-09-05 | 1988-06-08 | Morton Thiokol, Inc. | Process for transition metal nitrides thin film deposition |
| DE3650170T2 (en) * | 1985-05-13 | 1995-05-18 | Toshiba Kawasaki Kk | Semiconductor arrangement with connecting electrodes. |
| US4998157A (en) * | 1988-08-06 | 1991-03-05 | Seiko Epson Corporation | Ohmic contact to silicon substrate |
| EP0448763A1 (en) * | 1990-03-30 | 1991-10-02 | Siemens Aktiengesellschaft | Process and apparatus for manufacturing conductive layers or structures for highly integrated circuits |
| US5136362A (en) * | 1990-11-27 | 1992-08-04 | Grief Malcolm K | Electrical contact with diffusion barrier |
| EP0514103A1 (en) * | 1991-05-14 | 1992-11-19 | STMicroelectronics, Inc. | Barrier metal process for sub-micron contacts |
| US5242860A (en) * | 1991-07-24 | 1993-09-07 | Applied Materials, Inc. | Method for the formation of tin barrier layer with preferential (111) crystallographic orientation |
| US5308655A (en) * | 1991-08-16 | 1994-05-03 | Materials Research Corporation | Processing for forming low resistivity titanium nitride films |
| US5462895A (en) * | 1991-09-04 | 1995-10-31 | Oki Electric Industry Co., Ltd. | Method of making semiconductor device comprising a titanium nitride film |
| JPH05121378A (en) * | 1991-10-29 | 1993-05-18 | Sony Corp | Method of manufacturing semiconductor device |
| US5254499A (en) * | 1992-07-14 | 1993-10-19 | Micron Technology, Inc. | Method of depositing high density titanium nitride films on semiconductor wafers |
| JP2570576B2 (en) * | 1993-06-25 | 1997-01-08 | 日本電気株式会社 | Method for manufacturing semiconductor device |
| US5494860A (en) * | 1995-03-14 | 1996-02-27 | International Business Machines Corporation | Two step annealing process for decreasing contact resistance |
-
1995
- 1995-03-04 KR KR1019950004447A patent/KR0148325B1/en not_active IP Right Cessation
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1996
- 1996-03-04 GB GB9604614A patent/GB2298657B/en not_active Expired - Fee Related
- 1996-03-04 CN CN96104048A patent/CN1057868C/en not_active Expired - Fee Related
- 1996-03-04 TW TW085102622A patent/TW288171B/zh active
- 1996-03-04 DE DE19608208A patent/DE19608208B4/en not_active Expired - Fee Related
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100480576B1 (en) * | 1997-12-15 | 2005-05-16 | 삼성전자주식회사 | Forming method of metal wiring in semiconductor device |
| KR100494320B1 (en) * | 1997-12-30 | 2005-08-31 | 주식회사 하이닉스반도체 | Diffusion prevention film formation method of semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| GB9604614D0 (en) | 1996-05-01 |
| CN1057868C (en) | 2000-10-25 |
| JP2000082742A (en) | 2000-03-21 |
| GB2298657B (en) | 1998-09-30 |
| CN1141506A (en) | 1997-01-29 |
| DE19608208A1 (en) | 1996-09-05 |
| DE19608208B4 (en) | 2006-02-23 |
| KR960035843A (en) | 1996-10-28 |
| JP3122845B2 (en) | 2001-01-09 |
| TW288171B (en) | 1996-10-11 |
| JPH08250596A (en) | 1996-09-27 |
| GB2298657A (en) | 1996-09-11 |
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