KR100430684B1 - Method of forming thermally stable metal line of semiconductor device using doubly or triply deposited amorphous and crystalline tungsten nitride layer - Google Patents
Method of forming thermally stable metal line of semiconductor device using doubly or triply deposited amorphous and crystalline tungsten nitride layer Download PDFInfo
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- KR100430684B1 KR100430684B1 KR1019960079954A KR19960079954A KR100430684B1 KR 100430684 B1 KR100430684 B1 KR 100430684B1 KR 1019960079954 A KR1019960079954 A KR 1019960079954A KR 19960079954 A KR19960079954 A KR 19960079954A KR 100430684 B1 KR100430684 B1 KR 100430684B1
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- layer
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- tungsten nitride
- diffusion barrier
- crystalline
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- 229910052721 tungsten Inorganic materials 0.000 title claims abstract description 43
- 239000010937 tungsten Substances 0.000 title claims abstract description 43
- 229910052751 metal Inorganic materials 0.000 title claims abstract description 37
- 239000002184 metal Substances 0.000 title claims abstract description 37
- 238000000034 method Methods 0.000 title claims abstract description 21
- 239000004065 semiconductor Substances 0.000 title claims abstract description 7
- -1 tungsten nitride Chemical class 0.000 title abstract description 38
- 238000009792 diffusion process Methods 0.000 claims abstract description 29
- 238000000151 deposition Methods 0.000 claims abstract description 23
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 20
- 229910052802 copper Inorganic materials 0.000 claims abstract description 20
- 239000010949 copper Substances 0.000 claims abstract description 20
- 230000004888 barrier function Effects 0.000 claims abstract description 15
- 238000004544 sputter deposition Methods 0.000 claims abstract description 10
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims abstract description 9
- 239000010936 titanium Substances 0.000 claims abstract description 9
- 229910052719 titanium Inorganic materials 0.000 claims abstract description 9
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 8
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 5
- 238000000059 patterning Methods 0.000 claims description 4
- 238000005229 chemical vapour deposition Methods 0.000 claims description 3
- 229910052757 nitrogen Inorganic materials 0.000 claims description 3
- 238000005240 physical vapour deposition Methods 0.000 claims description 3
- 239000004020 conductor Substances 0.000 claims description 2
- 230000015572 biosynthetic process Effects 0.000 claims 2
- 239000013078 crystal Substances 0.000 claims 1
- 229910052715 tantalum Inorganic materials 0.000 claims 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims 1
- 238000011065 in-situ storage Methods 0.000 abstract 1
- 239000010408 film Substances 0.000 description 24
- 230000008021 deposition Effects 0.000 description 8
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 6
- 239000002245 particle Substances 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 239000000758 substrate Substances 0.000 description 4
- 229910052786 argon Inorganic materials 0.000 description 3
- 150000002739 metals Chemical class 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 229910001873 dinitrogen Inorganic materials 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 238000007792 addition Methods 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 1
- 239000013077 target material Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76846—Layer combinations
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/2855—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by physical means, e.g. sputtering, evaporation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76849—Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned on top of the main fill metal
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
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Abstract
Description
본 발명은 반도체소자의 금속배선 형성방법에 관한것으로, 특히 구리 배선의 확산방지 금속막으로 텅스텐 나이트라이드를 스퍼터링 방법으로 형성하는 금속배선 형성방법에 관한것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming metal wiring in semiconductor devices, and more particularly, to a method for forming metal wiring in which tungsten nitride is formed by a sputtering method with a diffusion preventing metal film of copper wiring.
구리를 증착할때 산화막에 대한 열적 안정성을 확보하기 위해서는 구리를 증착하기 전에 확산 방지 금속막의 증착이 필요하다. 구리 배선용 확산 방지 금속은 아직 확실하게 재료가 결정된바 없고 많은 연구자들이 여러 금속 특히 나이트라이드 계통의 금속을 고려하고 있다. 이들 대상 재료중 텅스텐 나이트라이드와 탄탈륨 나이트라이드의 확산 방지 효과가 우수한 것으로 보고 되고 있다.In order to ensure thermal stability of the oxide film when depositing copper, deposition of a diffusion barrier metal film is required before depositing copper. Anti-diffusion metals for copper wiring have not yet been reliably determined, and many researchers are considering various metals, especially metals of the nitride system. Among these target materials, tungsten nitride and tantalum nitride have been reported to be excellent in preventing diffusion.
텅스텐 나이트라이드층의 스퍼터링은 아르곤 가스에 대한 질소 가스의 유량에 따라 비정질 혹은 결정질 상을 갖는 텅스텐 나이트라이드층이 형성되어 확산 방지 금속막으로 사용하고 있다.Sputtering of the tungsten nitride layer is used as a diffusion preventing metal film by forming a tungsten nitride layer having an amorphous or crystalline phase depending on the flow rate of nitrogen gas to an argon gas.
그러나 비정질 혹은 결정구조의 텅스텐 나이트라이드층은 응력에 의한 파티클 문제와, 고저항 문제, 낮은 증착 속도 등 여러 공정상의 문제점을 가지고 있다.However, the amorphous or crystalline tungsten nitride layer has various process problems such as a particle problem caused by stress, a high resistance problem, and a low deposition rate.
본 발명은 상기한 문제점을 해결하기 위하여 텅스텐 나이트라이드층 증착을 단일 증착 챔버에서 비정질과 결정질 텅스텐 나이트라이드층을 2중 또는 3중으로 적층하여 안정성 확보와 동시에 증착속도 높이는 금속 배선 형성방법을 제공하는데 그 목적이 있다.The present invention provides a method for forming a metal wiring to increase the deposition rate and at the same time to ensure the stability by stacking the tungsten nitride layer deposition in a single deposition chamber in an amorphous and crystalline tungsten nitride layer in a double or triple to solve the above problems. There is a purpose.
도 1 내지 도 5 는 본 발명의 실시예에 의해 금속 배선 형성 단계를 도시한 단면도이다.1 to 5 are cross-sectional views illustrating metal wire forming steps in accordance with an embodiment of the present invention.
[도면의 주요 부분에 대한 부호 설명][Description of symbols on the main parts of the drawings]
1 : 도전층 또는 실리콘 기판 2 : 절연막1 conductive layer or silicon substrate 2 insulating film
3 : 타이타늄 또는 텅스텐층3: titanium or tungsten layer
4, 6 : 비정질 텅스텐 나이트라이드층4, 6: amorphous tungsten nitride layer
5 : 결정질 텅스텐 나이트라이드층5: crystalline tungsten nitride layer
7 : 구리막7: copper film
8 : 확산 방지 금속막8: diffusion diffusion metal film
상기목적을 달성하기 위한 본 발명은 반도체 소자 제조 공정중 금속 배선 형성 방법에 있어서,The present invention for achieving the above object is a method of forming a metal wiring in the semiconductor device manufacturing process
도전층 또는 실리콘 기판 상부에 절연막을 형성하는 단계와,Forming an insulating film on the conductive layer or the silicon substrate;
상기 절연막의 일정 부분을 식각하여 콘택홀을 형성하는 단계와,Etching a portion of the insulating film to form a contact hole;
타이타늄층을 증착하는 단계와,Depositing a titanium layer,
확산 방지 금속막으로 비정질 텅스텐 나이트라이드층과 결정질 텅스텐 나이트라이드층을 2중 또는 3중 적층 구조로 형성하는 단계와,Forming an amorphous tungsten nitride layer and a crystalline tungsten nitride layer in a double or triple stacked structure using a diffusion preventing metal film;
상기 확산 방지 금속막 상부에 구리막을 증착하는 단계와,Depositing a copper film on the diffusion barrier metal film;
화학적 기계적 연마에 의해 상기 구리막, 확산 방지 금속막 및 타이타늄막을 제거하여 금속 배선을 패턴닝하는 단계와,Patterning the metal wiring by removing the copper film, the diffusion barrier metal film, and the titanium film by chemical mechanical polishing;
상기 금속 배선의 표면에 상부 확산 방지 금속막을 증착하는 단계로 이루어진다.And depositing an upper diffusion preventing metal film on the surface of the metal wiring.
본 발명은 확산 방지 금속막인 텅스텐 나이트라이드층을 스퍼터링시 증착 속도와 응력이 높으며 저항이 낮은 비정질 텅스텐 나이트라이드층을 증착하고 동일 스퍼터링 챔버에서 아르곤에 대한 질소 유량을 증가시켜 증착 속도가 낮고 응력이 작고 저항이 높은 결정질 텅스텐 나이트라이드층을 증착하고 다시 질소 유량을 줄여 비정질 텅스텐 나이트라이드층을 증착하여 응력완화에 의한 파티클 악제/생산성 확보/저저항화를 이루어 공정상의 문제점을 없애는 기술이다.According to the present invention, when sputtering a tungsten nitride layer, which is a diffusion preventing metal film, the deposition rate and stress are high and the resistivity is deposited. It is a technology that eliminates process problems by depositing a small, high-resistance crystalline tungsten nitride layer and reducing the nitrogen flow rate to deposit an amorphous tungsten nitride layer to achieve particle degradation / productivity / low resistance due to stress relaxation.
상기의 본 발명은 비정질/결정질 텅스텐 나이트라이드층을 이용한 구리 배선에 관한 것으로 본 발명에 의하면 텅스텐 나이트라이드층 증착시 아르곤에 대한 질소 유량을 변화시켜 증착되는 텅스텐 나이트라이드층의 상을 2중 내지는 3중으로 증착하여 제반 문제를 해결하는 기술에 관한 것이다.The present invention relates to a copper wiring using an amorphous / crystalline tungsten nitride layer. According to the present invention, the phase of the tungsten nitride layer deposited by varying the nitrogen flow rate to argon when the tungsten nitride layer is deposited is double or three. The present invention relates to a technique for solving various problems by depositing in the middle.
상술한 목적 및 특징들, 장점은 첨부된 도면과 관련한 다음의 상세한 설명을 통하여 보다 분명해 질 것이다. 이하 첨부된 도면을 참조하여 본 발명의 실시예를 상세히 설명하면 다음과 같다.The above objects, features, and advantages will become more apparent from the following detailed description taken in conjunction with the accompanying drawings. Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도1 내지 도5는 본 발명의 실시예에 의해 금속 배선을 형성하는 단계를 도시한 단면도이다.1 to 5 are cross-sectional views showing steps of forming metal wirings in accordance with an embodiment of the present invention.
도1은 반도체 소자 제조 공정중 도전체 또는 실리콘 기판(1) 상부에 절연막(2)을 증착하고 절연막(2)의 예정된 부위를 식각하여 상기 도전층 또는 실리콘 기판(1)이 노출되는 콘택홀(10)을 형성한 후, 콘택홀(10)의 저부에 형성된 자연 산화막을 건식 혹은 습식 식각 방법으로 제거한 다음, 스퍼터링 장비에서 콘택 저항 개선을 위해 타이타늄층 혹은 텅스텐층(3)을 증착한 후, 그 상부면에 저 저항의 비정질 텅스텐 나이트라이드층(4)을 증착한 상태를 나타낸 단면도이다.1 is a contact hole in which an insulating layer 2 is deposited on a conductor or a silicon substrate 1 during a semiconductor device manufacturing process, and a predetermined portion of the insulating layer 2 is etched to expose the conductive layer or silicon substrate 1. 10), the natural oxide film formed on the bottom of the contact hole 10 is removed by a dry or wet etching method, and then a titanium layer or tungsten layer (3) is deposited on the sputtering equipment to improve contact resistance. It is sectional drawing which shows the state which deposited the low resistance amorphous tungsten nitride layer 4 on the upper surface.
도2는 상기 비정질 텅스텐 나이트라이드층(4)을 증착한 후 동일 스퍼터링 챔버에서 아르곤에 대한 질소 가스의 유량을 증가시켜 고저항의 결정질 텅스텐 나이트라이드층(5)을 예정된 두께의 일부만 증착한 상태를 나타낸 단면도이다. 이때 상기의 비정질/결정질 텅스텐 나이트라이드층의 응력은 서로 반대로 응력 완화에 의한 스퍼터링 챔버의 파티클을 억제할 수 있다.FIG. 2 shows a state in which only a portion of a predetermined thickness of the crystalline tungsten nitride layer 5 is deposited by increasing the flow rate of nitrogen gas to argon in the same sputtering chamber after depositing the amorphous tungsten nitride layer 4. It is sectional drawing shown. At this time, the stress of the amorphous / crystalline tungsten nitride layer can suppress the particles of the sputtering chamber due to stress relaxation on the contrary.
도3은 상기 결정질 텅스텐 나이트라이드층(5)을 증착한 후 다시 비정질 텅스텐 나이트라이드층(6)을 증착한 것을 도시한 단면도이다.3 is a cross-sectional view showing the deposition of the amorphous tungsten nitride layer 6 after the crystalline tungsten nitride layer 5 is deposited.
참고로, 상기 비정질 텅스텐 나이트라이드층(4), 결정질 텅스텐 나이트라이드층(5) 및 비정질 텅스텐 나이트라이드층(6)의 적층 구조는 후속 공정에서 형성되는 구리층의 확산 방지 금속막으로 이용되는 막이다.For reference, the laminated structure of the amorphous tungsten nitride layer 4, the crystalline tungsten nitride layer 5, and the amorphous tungsten nitride layer 6 is used as a diffusion preventing metal film of the copper layer formed in a subsequent process. to be.
도4는 상기 비정질 텅스텐 나이트라이드층(6)을 증착한 다음, 화학 기상 증착법 또는 물리 기상 증착법으로 구리층(7)을 증착한 상태를 나타낸 단면도이다.4 is a cross-sectional view showing a state in which the copper layer 7 is deposited by chemical vapor deposition or physical vapor deposition after depositing the amorphous tungsten nitride layer 6.
도5는 상기 구리층(7)을 증착한 후 화학적 기계적 연마(Chemical Mechanical Polishing)에 의해 상기 구리층(7), 텅스텐 나이트라이드층(6, 5, 4)와 타이타늄층 혹은 팅스텐층(3)을 제거하되 하부 절연막(2)의 상부 면이 노출되기 까지 제거하여 금속 배선 패턴닝 공정을 완료하고, 금속 배선의 표면에 상부 확산 방지 금속막(8)을 증착한 것을 도시한 단면도이다.FIG. 5 shows the copper layer 7, the tungsten nitride layers 6, 5, 4 and the titanium layer or the tinsten layer 3 by depositing the copper layer 7 by chemical mechanical polishing. ) Is removed but the upper surface of the lower insulating film 2 is exposed to complete the metal wiring patterning process, and the upper diffusion preventing metal film 8 is deposited on the surface of the metal wiring.
참고로, 상기 상부 확산 방지 금속막(8)은 하부 확산 방지금속을 동일 재료로 예를들어 비정질 또는 결정질 텅스텐 나이트라이드층으로 형성할 수 있다.For reference, the upper diffusion barrier metal film 8 may be formed of, for example, an amorphous or crystalline tungsten nitride layer of the lower diffusion barrier metal.
본 발명을 응용하여 확산 방지 금속막으로 이용되는 텅스텐 나이트라이드층을 비정질/결정질 텅스텐 나이트라이드 2중 적층 구조 혹은 결정질/비정질 텅스텐 나이트라이드 2중 적층 구조 혹은 결정질/비정질/결정질 텅스텐 나이트라이드 3중 적층 구조로 형성하여도 거의 유사한 효과를 얻을수 있다.The present invention is applied to the tungsten nitride layer used as the diffusion barrier metal film in an amorphous / crystalline tungsten nitride double stack structure or a crystalline / amorphous tungsten nitride double stack structure or a crystalline / amorphous / crystalline tungsten nitride triple stack. When formed into a structure, almost similar effects can be obtained.
본 발명에 의하면 확산 방지 금속막으로 이용되는 텅스텐 나이트라이드층을 비정질층과 결정질층 나이트라이드층을 2중 또는 3중 적층 구조로 형성함으로써 종래의 텅스텐 나이트라이드층 적용의 문제점인 응력에 의한 파티클 문제가 낮은 증착 속도에 의한 생산성 감소 문제 그리고 고저항화 문제를 해결할 수 가 있다.According to the present invention, by forming a tungsten nitride layer used as a diffusion preventing metal film in an amorphous layer and a crystalline layer nitride layer in a double or triple stacked structure, there is a problem of particles caused by stress, which is a problem of applying a conventional tungsten nitride layer. Solves the problem of reduced productivity due to low deposition rate and high resistance.
또한, 비정질 텅스텐 나이트라이드층을 도입함으로써 구리가 확산할 경로인 결정립계를 없애 산화막층으로의 확산을 막을 수 있고 결정질층을 그 사이에 증착함으로써 파티클 발생 및 증착된 박막의 들뜸을 방지할 수 있어 신뢰성 있는 구리 배선 공정을 할 수 있다.In addition, by introducing an amorphous tungsten nitride layer, it is possible to prevent the diffusion into the oxide layer by eliminating the grain boundary, which is a path for copper diffusion, and to prevent particle generation and lifting of the deposited thin film by depositing a crystalline layer therebetween. Copper wiring process.
아울러 본 발명의 바람직한 실시예들은 예시의 목적을 위해 개시된 것이며, 당업자라면 본 발명의 사상과 범위안에서 다양한 수정, 변경, 부가등이 가능할 것이며, 이러한 수정 변경 등은 이하의 특허 청구의 범위에 속하는 것으로 보아야 할 것이다.In addition, preferred embodiments of the present invention are disclosed for the purpose of illustration, those skilled in the art will be able to various modifications, changes, additions, etc. within the spirit and scope of the present invention, such modifications and modifications belong to the following claims You will have to look.
Claims (6)
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| KR1019960079954A KR100430684B1 (en) | 1996-12-31 | 1996-12-31 | Method of forming thermally stable metal line of semiconductor device using doubly or triply deposited amorphous and crystalline tungsten nitride layer |
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| KR1019960079954A KR100430684B1 (en) | 1996-12-31 | 1996-12-31 | Method of forming thermally stable metal line of semiconductor device using doubly or triply deposited amorphous and crystalline tungsten nitride layer |
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| KR100559028B1 (en) * | 1998-12-29 | 2006-06-15 | 주식회사 하이닉스반도체 | Copper wiring formation method of semiconductor device |
| KR100338102B1 (en) * | 1999-06-25 | 2002-05-24 | 박종섭 | Method of forming a Cu wiring in a semiconductor device |
| KR100301057B1 (en) * | 1999-07-07 | 2001-11-01 | 윤종용 | Semiconductor device having copper interconnection layer and manufacturing method thereof |
| KR100555514B1 (en) | 2003-08-22 | 2006-03-03 | 삼성전자주식회사 | Semiconductor memory device having tungsten line with low resistance and method for manufacturing the same |
| KR100642750B1 (en) | 2005-01-31 | 2006-11-10 | 삼성전자주식회사 | Semiconductor device and method for manufacturing the same |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JPH04267359A (en) * | 1991-02-21 | 1992-09-22 | Sony Corp | Formation of metal layer |
| JPH06326103A (en) * | 1992-08-27 | 1994-11-25 | Toshiba Corp | Electronic component and its manufacture |
| KR950015651A (en) * | 1993-11-11 | 1995-06-17 | 김주용 | Method of forming diffusion preventing metal layer of semiconductor device |
| KR960035843A (en) * | 1995-03-04 | 1996-10-28 | 김주용 | Metal wiring formation method of semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04267359A (en) * | 1991-02-21 | 1992-09-22 | Sony Corp | Formation of metal layer |
| JPH06326103A (en) * | 1992-08-27 | 1994-11-25 | Toshiba Corp | Electronic component and its manufacture |
| KR950015651A (en) * | 1993-11-11 | 1995-06-17 | 김주용 | Method of forming diffusion preventing metal layer of semiconductor device |
| KR960035843A (en) * | 1995-03-04 | 1996-10-28 | 김주용 | Metal wiring formation method of semiconductor device |
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