KR100574922B1 - Method of etching material layer using anti-reflective coating layer for semiconductor device - Google Patents

Abstract

The multilayer wiring structure of a semiconductor device and its manufacturing method are disclosed. In one aspect of the present invention, an interlayer insulating layer having a contact hole exposing the lower wiring layer is formed on the lower wiring layer, and an upper wiring layer is formed to fill the contact hole and be electrically connected to the lower wiring layer. In this case, a barrier spacer layer that selectively covers the sidewall of the contact hole and prevents material diffusion between the interlayer insulating layer and the upper wiring layer through the sidewall of the contact hole is formed by an ionized physical vapor deposition method.

Description

Multi-layered wiring structure of semiconductor device and manufacturing method thereof {Method of etching material layer using anti-reflective coating layer for semiconductor device}

1 is a cross-sectional view schematically illustrating a multilayer wiring structure of a conventional semiconductor device.

2 or 3 and 4 are cross-sectional views schematically illustrating a multilayer wiring structure and a method of manufacturing the semiconductor device according to the embodiment of the present invention.

<Description of Major Symbols in Drawing>

100; Semiconductor substrate, 200; Bottom insulation layer,

300; Lower wiring layer 400; Interlayer insulation layer,

410; Contact holes, 600; Barrier spacer layers,

700; Upper wiring layer.

TECHNICAL FIELD The present invention relates to a semiconductor device, and more particularly, to a multilayer wiring structure and a method of manufacturing the same.

BACKGROUND ART In accordance with the demand for high integration or high operation speed of semiconductor devices, a multilayer wiring structure involving an interconnection process between wiring layers has been introduced. In addition, a metal material having high conductivity, such as copper, is used as a material of the wiring layer.

Copper and the like have very high diffusivity in silicon oxide of a substrate or an interlayer insulating layer made of silicon. Therefore, in order to use a metal material such as copper as the wiring layer as described above, a process of preventing diffusion of copper or the like into the material layer containing such silicon is necessarily accompanied. For example, a process of introducing a barrier layer at an interface between the insulating layer of silicon oxide and a wiring layer such as copper is essential.

As such a barrier layer, tantalum (Ta) or tantalum nitride (TaN _X ) is mainly used. In particular, tantalum nitride exhibits excellent characteristics in that diffusion to copper is further suppressed as the content of nitrogen contained in the film is increased, and its use is promising.

1 schematically shows a multilayer wiring structure of a conventional semiconductor device.

Specifically, the lower wiring layer 30 insulated from the lower insulating layer 20 is formed on the semiconductor substrate 10. An interlayer insulating layer 40 having a contact hole 41 exposing the lower wiring layer 20 is formed on the lower wiring layer 20. In addition, an upper insulating layer 50 may be further formed on the interlayer insulating layer 40, and a trench for patterning the upper wiring layer 70 may be further formed on the upper insulating layer 50. . In addition, an etching stop layer 45 used in the etching process of forming the trench may be provided at an interface between the interlayer insulating layer 40 and the upper insulating layer 50.

In this case, the barrier layer 60 is formed under the upper wiring layer 70 that is filled with the contact hole 41 and electrically connected to the lower wiring layer 30. The barrier layer 60 may be formed by sputtering deposition of the tantalum nitride layer. The tantalum nitride layer formed as described above is formed to have a thicker thickness at the sidewall portion 67 of the contact hole 41 at the bottom portion 65 of the contact hole 41. This is largely due to the nature of the sputter deposition method.

On the other hand, the tantalum nitride layer must have a high nitrogen content in order to have a high diffusion inhibitory property as described above. To this end, the sputtering must be performed in a nitrogen mode. In other words, the sputtering should be performed in a mode of supplying nitrogen into the chamber of the sputter and using a target of tantalum.

However, the tantalum nitride layer increases the resistivity as the nitrogen content increases, resulting in an increase in sheet resistance. Such increase in surface resistance can cause problems such as lowering the operating speed of the semiconductor device and the like, and is preferably suppressed. Moreover, when the tantalum nitride layer used as the barrier layer 60 is formed by the sputtering method as described above, as shown in FIG. 1, it is difficult to avoid the thick formation of the bottom portion 65 of the contact hole 41. Therefore, since high contact resistance is involved, it is difficult to use a tantalum nitride layer containing high nitrogen and having excellent diffusion suppressing characteristics as the barrier layer 60.

 SUMMARY OF THE INVENTION An object of the present invention is to provide a multilayer wiring structure of a semiconductor device which can suppress an increase in contact resistance and excellently suppress diffusion of a material used as a wiring layer into an insulating layer or the like.

Another object of the present invention is to provide a method of manufacturing the multilayer wiring structure of the semiconductor device described above.

An aspect of the present invention for achieving the above technical problem, an interlayer insulating layer having a contact hole formed on the lower wiring layer and exposing the lower wiring layer, and the upper portion filled with the contact hole and electrically connected to the lower wiring layer A wiring layer, and a barrier spacer layer selectively formed at an interface between the sidewall of the contact hole and the upper wiring layer to prevent material diffusion between the interlayer insulating layer and the upper wiring layer through the sidewall of the contact hole. Provide structure.

The barrier spacer layer extends to an interface between the lower wiring layer exposed by the contact hole and the upper wiring layer, and the extension portion has a thickness thinner than a portion formed at an interface between the sidewall of the contact hole and the upper wiring layer.

The barrier spacer layer is made of any one selected from the group consisting of tantalum, titanium, tungsten or nitrides thereof, and the upper wiring layer is made of any one selected from the group consisting of copper, aluminum, or tungsten.

One aspect of the present invention for achieving the above technical problem is to form an interlayer insulating layer having a contact hole exposing the lower wiring layer on the lower wiring layer. Filling the contact hole to form an upper wiring layer electrically connected to the lower wiring layer. A barrier spacer layer is formed to selectively cover sidewalls of the contact holes to prevent material diffusion between the insulating layer and the upper wiring layer through the sidewalls of the contact holes.

The barrier spacer layer is formed by depositing tantalum, titanium, tungsten, or a nitride thereof on the sidewall of the contact hole and the exposed lower interconnection layer, and the deposition is performed by an ionization physical vapor deposition method. Accordingly, the deposited portion covering the lower interconnection layer is re-sputtered in-situ during the deposition process and redeposited on the sidewall of the contact hole to expose the lower interconnection layer or to cover the lower interconnection layer. The thickness is thinner than the thickness of the deposited portion covering the sidewall of the contact hole. At least 300 watts of substrate bias is applied to the rear surface of the semiconductor substrate during the deposition process.

According to the present invention, it is possible to realize a more stable diffusion barrier effect and, at the same time, to suppress an increase in contact resistance, thereby manufacturing a reliable semiconductor device.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, embodiments of the present invention may be modified in many different forms, and the scope of the present invention should not be construed as being limited by the embodiments described below. Embodiments of the present invention are provided to more completely explain the present invention to those skilled in the art. Accordingly, the shape and the like of the elements in the drawings are exaggerated to emphasize a more clear description, and the elements denoted by the same reference numerals in the drawings means the same elements. In addition, where a layer is described as being "on" another layer or semiconductor substrate, the layer may exist in direct contact with the other layer or semiconductor substrate, or a third layer therebetween. May be interposed.

In an embodiment of the present invention, the barrier layer is formed such that the barrier layer substantially exposes the bottom of the contact hole or the thickness of the portion covering the bottom of the contact hole is very small compared to the thickness covering the side wall of the contact hole. To this end, in the embodiment of the present invention, the barrier layer is formed by an ionized physical vapor deposition method. The multilayer wiring structure of the semiconductor device according to the embodiment of the present invention will be described in detail with reference to the manufacturing method thereof.

2 or 3 schematically illustrate forming a barrier spacer layer 600 selectively covering sidewalls of the contact hole 410.

In detail, the lower wiring layer 300 insulated from the lower insulating layer 200 is formed on the semiconductor substrate 100. The lower wiring layer 300 has conductive properties and is made of aluminum (Al), copper (Cu), tungsten, or the like. Or an alloy containing these metal elements.

Subsequently, the interlayer insulating layer 400 covering the lower wiring layer 300 is formed of an insulating material such as silicon oxide. Next, a part of the interlayer insulating layer 400 is selectively etched using a photolithography process to form a contact hole 410 that selectively exposes the surface of the lower lower wiring layer 300.

Before the contact hole 400 is formed, the upper insulating layer 500 is formed on the interlayer insulating layer 400. After the opening, the upper insulating layer 500 is patterned to form the trench 510 for patterning the upper wiring layer (not shown). An etch stop layer 450 used in the process of patterning the trench 510 may be introduced at an interface between the upper insulating layer 500 and the interlayer insulating layer 400.

After the contact hole 410 is formed as described above, the barrier spacer layer 600 is formed on the interlayer insulating layer 400 to suppress material diffusion. In this case, the barrier spacer layer 600 may be formed of tantalum, titanium, tungsten, or the like, or a nitride of such a material. It is preferably formed of tantalum nitride. At this time, tantalum nitride and the like is preferable to have a better diffusion suppression characteristics having a high nitrogen content.

The barrier spacer layer 600 is selectively formed to cover sidewalls of the contact hole 410. That is, as shown in FIG. 3, the barrier spacer layer 600 may substantially expose the bottom portion 415 of the contact hole 410 of the barrier spacer layer 600, and cover the sidewall of the contact hole 410. Optionally formed. In this case, the barrier spacer layer 600 may extend to cover the upper portion of the upper insulating layer 500, and may also extend to cover sidewalls of the trench 510.

Alternatively, as shown in FIG. 2, the thickness of the portion 670 covering the sidewalls of the contact hole 410 of the barrier spacer layer 600 is thicker than that of the portion 650 covering the bottom portion of the contact hole 410. The barrier spacer layer 600 may extend to form a thickness. That is, the barrier spacer layer 600 may be formed to be thinly extended from the thick portion of the barrier spacer layer 600 covering the sidewall of the contact hole 410 to the bottom portion of the contact hole 410.

The barrier spacer layer 600 may be implemented by using an ionized physical vapor deposition method. This will be described in more detail with an example of using tantalum nitride as the barrier spacer layer 600.

A sputtering process is performed while flowing a reactive nitrogen gas at a high flow rate into a chamber into which a target made of tantalum is introduced. At this time, the target is reacted with the introduced reactive nitrogen to be nitrided and stuffed. That is, the sputtering process is performed in nitrogen mode. At this time, the flow rate of the incoming reactive nitrogen is kept very high. This is to induce high nitrogen content in the tantalum nitride layer to be deposited.

In this case, the particles sputtered by general physical vapor deposition include a large number of neutral particles, but in the ionized physical vapor deposition used in the embodiment of the present invention, neutral particles included in particles sputtered by applying RF power or the like to a chamber wall surface, etc. Ionize them. That is, the content of tantalum ions included in the particle group to be sputtered and deposited on the semiconductor substrate 100 increases. In addition, by applying a high substrate bias to the rear surface of the semiconductor substrate 100, the ionized particles are accelerated onto the semiconductor substrate 100. In this case, a high power of about 300 W or more may be applied to the substrate bias.

The tantalum nitride layer thus deposited will have a sufficiently reduced deposition rate. This is largely due to the nature of the sputtering process in nitrogen mode. However, in the case of tantalum or tantalum nitride, the sputtering yield is relatively excellent, and thus, even at such a low deposition rate, the tantalum nitride layer may be sufficiently deposited on the semiconductor substrate 100, that is, on the entire surface where the contact hole 410 is formed. have.

As described above, when the tantalum nitride layer is continuously deposited and grown by the above-described deposition, the phenomenon in which the tantalum nitride layer is redeposited on the sidewall portion of the contact hole 410 occurs in the contact hole 410. This occurs because tantalum particles accelerated by the substrate bias and the like resputter the initially deposited tantalum nitride layer. In detail, when tantalum corresponds to heavy metal particles having a relatively high mass and is ionized as described above, it is accelerated by the substrate bias. Such accelerated particles have sufficient energy to impinge on the entire surface of the semiconductor substrate 100 and to resputter the vapor deposited tantalum nitride layer.

These resputtered particles do not escape to the outside of the contact hole 410 in the contact hole 410 and are mostly redeposited on the sidewall of the contact hole 410. In detail, redeposition does not occur efficiently by continuous resputtering at the bottom of the contact hole 410, and the particles that are resputtered do not escape to the outside of the contact hole 410. Redeposit on the sidewalls of 410. Accordingly, the deposited barrier spacer layer 600 has a portion 670 that selectively covers the sidewall of the contact hole 410 to have a thick thickness. In addition, the portion 650 covering the bottom portion 415 of the contact hole 410 in which resputtering is concentrated is formed in a very thin thickness as shown in FIG. 2 or as shown in FIG. 3. The bottom of the 410, that is, the surface of the lower wiring layer 300 is exposed to form a spacer.

The tantalum nitride layer used as the barrier spacer layer 600 formed as described above substantially exposes the lower wiring layer 300 constituting the bottom portion 415 of the contact hole 410, resulting in a relatively high resistivity of the tantalum nitride layer. The increase in contact resistance can be suppressed. In addition, since the surface of the interlayer insulating layer 400 made of silicon oxide or the like is selectively shielded, the barrier spacer layer 600 may sufficiently play a role of diffusion suppression. That is, it is possible to take full advantage of the excellent diffusion suppressing properties of tantalum nitride which is formed in the nitrogen mode and contains a high content of nitrogen. Accordingly, a more stable diffusion barrier effect can be obtained.

4 schematically illustrates the formation of the upper wiring layer 700.

In detail, the upper interconnection layer 700 filling the contact hole 410 is formed on the entire surface of the product in which the barrier spacer layer 600 is formed. In this case, the upper wiring layer 700 may be formed of aluminum, copper, tungsten, or an alloy thereof, but is preferably formed of copper or a copper alloy. The upper wiring layer 700 is patterned using the trench 510.

Since the interface between the upper wiring layer 700 and the interlayer insulating layer 400 is shielded by the barrier spacer layer 600, a material forming the upper wiring layer 700, for example, a copper element forms the interlayer insulating layer 400. Diffusion into the silicon oxide is suppressed.

In addition, as shown in FIG. 2, the extended portion 650 of the barrier spacer layer 600 extending to the bottom portion of the contact hole 410 is very large compared to the portion 670 covering the sidewall of the contact hole 410. It has a thin thickness. Therefore, an increase in electrical resistance between the upper wiring layer 700 and the lower wiring layer 300 can be suppressed as much as possible. In addition, as shown in FIG. 3, when the bottom portion 415 of the contact hole 410 is substantially exposed, substantially between the upper wiring layer 700 and the lower wiring layer 300 due to the introduction of the barrier spacer layer 600. There is no increase.

As mentioned above, although this invention was demonstrated in detail through the specific Example, this invention is not limited to this, It is clear that the deformation | transformation and improvement are possible by the person of ordinary skill in the art within the technical idea of this invention.

According to the present invention described above, it is possible to form a barrier spacer layer that selectively covers only the sidewalls of the contact holes using the ionization physical vapor deposition method, and the contact holes substantially expose the bottom portion. Accordingly, the nitrogen content of tantalum nitride or the like can be increased to realize excellent diffusion suppression characteristics of the barrier spacer layer and to suppress an increase in contact resistance between the upper wiring layer and the lower wiring layer.

Claims (6)

delete delete delete Forming an interlayer insulating layer having a contact hole exposing the lower wiring layer on the lower wiring layer; Filling the contact hole to form an upper wiring layer electrically connected to the lower wiring layer; And And selectively forming a barrier spacer layer on the sidewall of the contact hole to prevent material diffusion between the insulating layer and the upper wiring layer through the sidewall of the contact hole by an ionization physical vapor deposition method. Method for manufacturing a multilayer wiring structure. The method of claim 4, wherein the barrier spacer layer is Any one selected from the group consisting of tantalum, titanium, tungsten or nitrides thereof is deposited on the sidewalls of the contact hole and the exposed lower wiring layer. The deposited portion covering the lower wiring layer is re-sputtered in situ in the deposition process and redeposited on the sidewall of the contact hole so that the lower wiring layer is exposed or the thickness of the deposited portion covering the lower wiring layer covers the sidewall of the contact hole. A method for manufacturing a multilayer wiring structure of a semiconductor device, characterized in that it is formed thinner than the thickness of the deposited portion. The method of claim 4, wherein in the deposition process And a substrate bias of at least 300 watts is applied to a rear surface of the semiconductor substrate.

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