JPH04267359A - Formation of metal layer - Google Patents
Formation of metal layerInfo
- Publication number
- JPH04267359A JPH04267359A JP4733891A JP4733891A JPH04267359A JP H04267359 A JPH04267359 A JP H04267359A JP 4733891 A JP4733891 A JP 4733891A JP 4733891 A JP4733891 A JP 4733891A JP H04267359 A JPH04267359 A JP H04267359A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- tin layer
- amorphous
- contact hole
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 229910052751 metal Inorganic materials 0.000 title abstract description 14
- 239000002184 metal Substances 0.000 title abstract description 14
- 230000015572 biosynthetic process Effects 0.000 title description 6
- 239000000463 material Substances 0.000 claims abstract description 20
- 229910052782 aluminium Inorganic materials 0.000 claims abstract description 8
- 239000000126 substance Substances 0.000 claims abstract description 7
- 239000010936 titanium Substances 0.000 claims description 23
- 239000000758 substrate Substances 0.000 claims description 17
- 238000000034 method Methods 0.000 claims description 11
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 6
- 229910052719 titanium Inorganic materials 0.000 claims description 5
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 3
- 239000011248 coating agent Substances 0.000 claims 1
- 238000000576 coating method Methods 0.000 claims 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 abstract description 21
- 230000004888 barrier function Effects 0.000 abstract description 21
- 238000009792 diffusion process Methods 0.000 abstract description 6
- 229910052710 silicon Inorganic materials 0.000 abstract description 6
- 238000004544 sputter deposition Methods 0.000 abstract description 6
- 239000013078 crystal Substances 0.000 abstract description 4
- 238000009413 insulation Methods 0.000 abstract 1
- 238000005259 measurement Methods 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 55
- 239000010408 film Substances 0.000 description 14
- 239000007789 gas Substances 0.000 description 9
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 7
- 239000001301 oxygen Substances 0.000 description 7
- 229910052760 oxygen Inorganic materials 0.000 description 7
- 229910010282 TiON Inorganic materials 0.000 description 6
- 239000011229 interlayer Substances 0.000 description 5
- 238000005468 ion implantation Methods 0.000 description 5
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 4
- 239000000460 chlorine Substances 0.000 description 4
- 229910052801 chlorine Inorganic materials 0.000 description 4
- 239000012535 impurity Substances 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 3
- 238000005260 corrosion Methods 0.000 description 3
- 230000006866 deterioration Effects 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 229910015844 BCl3 Inorganic materials 0.000 description 2
- KZBUYRJDOAKODT-UHFFFAOYSA-N Chlorine Chemical compound ClCl KZBUYRJDOAKODT-UHFFFAOYSA-N 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 238000001556 precipitation Methods 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- FAQYAMRNWDIXMY-UHFFFAOYSA-N trichloroborane Chemical compound ClB(Cl)Cl FAQYAMRNWDIXMY-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 238000005275 alloying Methods 0.000 description 1
- 238000005280 amorphization Methods 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- -1 carbides Chemical class 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010828 elution Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000000415 inactivating effect Effects 0.000 description 1
- 230000002779 inactivation Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 150000001247 metal acetylides Chemical class 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 238000005546 reactive sputtering Methods 0.000 description 1
- 230000009257 reactivity Effects 0.000 description 1
- 238000005204 segregation Methods 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 229910052723 transition metal Inorganic materials 0.000 description 1
- 150000003623 transition metal compounds Chemical class 0.000 description 1
- 150000003624 transition metals Chemical class 0.000 description 1
- 239000011882 ultra-fine particle Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【0001】0001
【産業上の利用分野】本発明は、半導体装置の製造等に
適用される配線形成方法に関し、特にチタン(Ti)系
材料層からなるバリヤメタルを有するコンタクト部にお
いて、いわゆるアルミ・スパイクに対する耐性を向上さ
せる方法に関する。[Industrial Application Field] The present invention relates to a wiring forming method applied to the manufacture of semiconductor devices, etc., and particularly improves resistance to so-called aluminum spikes in contact areas having a barrier metal made of a titanium (Ti) material layer. Concerning how to do so.
【0002】0002
【従来の技術】近年のVLSI,ULSI等にみられる
ように、半導体装置のデザイン・ルールが高度に縮小さ
れるに伴って接合が一段と浅くなり、またコンタクトホ
ールが一段と微細化されてくると、拡散層へのアルミニ
ウム(Al)の溶出やコンタクトホール中における電極
配線材料からのシリコン(Si)の析出等により接合の
破壊や劣化、あるいはコンタクト抵抗の増大等の不良が
起こり易くなる。そのため、電極配線材料とSi基板と
の間の合金化反応やSiの析出を防止する目的で、両者
の間にバリヤメタルを設けることが一般化している。こ
のバリヤメタルは、通常、遷移金属またはその窒化物,
炭化物,酸窒化物,ホウ化物等の遷移金属化合物の他、
高融点金属シリサイド、合金等で形成される。また、そ
の構成も単層のみならず、複数の種類の膜が組み合わせ
られる場合も多い。BACKGROUND OF THE INVENTION As seen in recent VLSI, ULSI, etc., as the design rules of semiconductor devices are highly reduced, junctions become shallower and contact holes become smaller. Defects such as breakdown or deterioration of the junction or increase in contact resistance are likely to occur due to elution of aluminum (Al) into the diffusion layer and precipitation of silicon (Si) from the electrode wiring material in the contact hole. Therefore, in order to prevent the alloying reaction between the electrode wiring material and the Si substrate and the precipitation of Si, it has become common to provide a barrier metal between the two. This barrier metal is usually a transition metal or its nitride,
In addition to transition metal compounds such as carbides, oxynitrides, and borides,
Made of high melting point metal silicide, alloy, etc. Moreover, its structure is not limited to a single layer, but is often a combination of multiple types of films.
【0003】たとえば、基板側からAl系材料層側へ向
けて順にTi層とTiN層とが積層されてなる2層構造
のバリヤメタル(Ti/TiN系)はその代表例である
。Ti層は酸素に対して高い親和力を有するため不純物
拡散層の表面に形成されている自然酸化膜を還元する作
用があり、低抵抗のオーミック・コンタクトを安定に達
成する観点からは優れたコンタクト材料である。しかし
、単独ではバリアメタルとしての機能を十分に果たし得
ない。それは、Si基板とAl系材料層との間にTi層
が単独で介在されていても、SiとTiの反応,および
TiとAlの反応の両方が進行するために、Si基板へ
のAlの突き抜け、すなわちアルミ・スパイクの発生が
防止できないからである。一方のTiN層は、熱力学的
にSiに対して安定でありTi層よりはバリヤ性は高い
が、特にp型Siに対するコンタクト抵抗が高いという
問題がある。また、真空薄膜形成技術により成膜される
際の結晶粒径が200Å前後でありしかも柱状構造を有
しているため、熱処理を経るとAlが粒界を拡散し、や
はりアルミ・スパイクを十分に防止し切れない。また、
Si基板上へ直接に形成された場合には、膜中に不純物
として取り込まれた酸素が該Si基板との界面に偏析す
る傾向があるため、単独では常に低抵抗なオーミック・
コンタクトを形成することは困難である。そこで、Si
基板上にまずTi層を形成し、続いてTiN層を積層す
ることにより、両層の長所を活かしているわけである。For example, a typical example is a two-layer barrier metal (Ti/TiN type) in which a Ti layer and a TiN layer are laminated in order from the substrate side to the Al type material layer side. Since the Ti layer has a high affinity for oxygen, it has the effect of reducing the natural oxide film formed on the surface of the impurity diffusion layer, making it an excellent contact material from the perspective of stably achieving low-resistance ohmic contact. It is. However, when used alone, it cannot sufficiently function as a barrier metal. This is because even if a single Ti layer is interposed between the Si substrate and the Al-based material layer, both the reaction between Si and Ti and the reaction between Ti and Al proceed. This is because penetration, that is, the occurrence of aluminum spikes, cannot be prevented. On the other hand, the TiN layer is thermodynamically stable with respect to Si and has a higher barrier property than the Ti layer, but it has a problem in that it has particularly high contact resistance with respect to p-type Si. In addition, since the crystal grain size when deposited using vacuum thin film formation technology is around 200 Å and has a columnar structure, Al diffuses through the grain boundaries after heat treatment, resulting in sufficient aluminum spike formation. It cannot be prevented. Also,
When formed directly on a Si substrate, oxygen incorporated into the film as an impurity tends to segregate at the interface with the Si substrate.
It is difficult to make contacts. Therefore, Si
By first forming a Ti layer on a substrate and then laminating a TiN layer, the advantages of both layers are utilized.
【0004】また、バリヤ性をより一層向上させるため
の対策として、近年ではTiN層の成膜時に酸素を導入
してTiON層とした2層構造のバリヤメタル(Ti/
TiON系)も提案されている。これは、TiNの粒界
に酸素を偏析させることにより、Alの粒界拡散を防止
することを意図したものである。In addition, as a measure to further improve barrier properties, in recent years, a two-layer barrier metal (Ti/
TiON type) has also been proposed. This is intended to prevent Al from diffusing into the grain boundaries by segregating oxygen at the grain boundaries of TiN.
【0005】[0005]
【発明が解決しようとする課題】しかしながら、TiO
N層を用いた場合にはバリヤ性は向上するものの、次の
ような問題点が新たに生じてしまう。第一の問題点は、
酸素を含まないTiN層に比べてコンタクト抵抗が1桁
以上も増大してしまうことである。第二の問題点は、T
iN層を使用した場合と比べてアフタコロージョンが発
生し易くなることである。Al系材料層およびバリヤメ
タルのドライエッチング用ガスとしては通常BCl3
等の塩素系ガスが使用されるが、このガスがTiON層
中の酸素と反応してCl2 を発生させるからである。
アフタコロージョンにはこのような化学的な要因の他に
、構造的な要因もある。すなわち、TiON層は表面の
モホロジーが粗く、TiN層と比べてAl系材料層との
濡れ性に劣るので、Al系材料層との界面に残留塩素を
滞留させる場を提供し易いからである。第三の問題点は
、ステップ・カバレッジ(段差被覆性)の劣化である。
近年の高集積化された半導体装置においては、下層配線
と上層配線の接続を図るために層間絶縁膜に開口される
接続孔の開口径も微細化し、アスペクト比が1を越える
ようになってきている。しかし、TiON層は前述のよ
うに表面のモホロジーが粗く、Al系材料との濡れ性や
反応性に劣るため、スパッタリングによりAl系材料を
被着させても接続孔は均一に埋め込まれず、鬆(す)が
発生し易い。[Problem to be solved by the invention] However, TiO
Although barrier properties are improved when an N layer is used, the following new problems arise. The first problem is
The contact resistance increases by more than one order of magnitude compared to a TiN layer that does not contain oxygen. The second problem is that T
This is because after-corrosion is more likely to occur than when an iN layer is used. BCl3 is usually used as a dry etching gas for Al-based material layers and barrier metals.
A chlorine-based gas such as chlorine-based gas is used because this gas reacts with oxygen in the TiON layer to generate Cl2. In addition to these chemical factors, there are also structural factors that cause aftertacrosis. That is, the TiON layer has a rough surface morphology and has poor wettability with the Al-based material layer compared to the TiN layer, so it is easy to provide a place for residual chlorine to remain at the interface with the Al-based material layer. The third problem is the deterioration of step coverage. In recent highly integrated semiconductor devices, the opening diameter of the connection hole opened in the interlayer insulating film to connect the lower layer wiring and the upper layer wiring has become smaller, and the aspect ratio has come to exceed 1. There is. However, as mentioned above, the TiON layer has a rough surface morphology and poor wettability and reactivity with Al-based materials, so even if the Al-based material is deposited by sputtering, the connection holes are not filled uniformly, resulting in ) is likely to occur.
【0006】このように、従来の技術では低抵抗性,高
いバリヤ性,優れたステップ・カバレッジ等の要求を同
時に満足し得るコンタクト形成を行うことが困難である
。そこで本発明は、これらの要求を同時に満足し得る配
線形成方法を提供することを目的とする。[0006] As described above, with the conventional techniques, it is difficult to form a contact that can simultaneously satisfy the requirements of low resistance, high barrier properties, and excellent step coverage. Therefore, an object of the present invention is to provide a wiring forming method that can simultaneously satisfy these requirements.
【0007】[0007]
【課題を解決するための手段】本発明の配線形成方法は
、上述の目的を達成するために提案されるものである。
すなわち、本願の第1の発明にかかる配線形成方法は、
基板上の絶縁膜に開口された接続孔の少なくとも底部お
よび側壁部を非晶質化されたTi系材料層で被覆する工
程と、少なくとも前記接続孔を充填するごとくAl系材
料層を形成する工程とを有することを特徴とするもので
ある。[Means for Solving the Problems] A wiring forming method of the present invention is proposed to achieve the above-mentioned objects. That is, the wiring forming method according to the first invention of the present application is as follows:
A step of covering at least the bottom and sidewalls of a connection hole opened in an insulating film on a substrate with an amorphous Ti-based material layer, and a step of forming an Al-based material layer so as to fill at least the connection hole. It is characterized by having the following.
【0008】本願の第2の発明にかかる配線形成方法は
、前記Ti系材料層が不活性物質をイオン注入すること
により非晶質化されてなることを特徴とするものである
。A wiring forming method according to a second aspect of the present invention is characterized in that the Ti-based material layer is made amorphous by ion-implanting an inert substance.
【0009】[0009]
【作用】真空薄膜形成技術により成膜されるTi系材料
層は通常、粒径200Å程度の微細な柱状結晶が集合し
てなる多結晶組織を有しているが、そのバリヤ性を高め
るには不純物にとって速い拡散経路となる結晶粒界を不
活性化することが必須である。従来は、たとえば結晶粒
界に酸素を偏析させることにより不活性化を行ってきた
わけであるが、その結果得られる膜の問題点については
TiON層の場合を例として前述したとおりである。そ
こで本発明者は、酸素の偏析により結晶粒界を不活性化
するのではなく、多結晶組織を破壊して結晶粒界そのも
のを消滅させることを考え、本発明を提案するに至った
ものである。ここで、結晶粒界が完全に消滅されれば非
晶質(アモルファス)状態となるが、本発明では多結晶
組織を構成する単結晶が高度に微粒子化され、結晶粒界
が実質的に速い拡散経路となり得ない程度にまで微細化
されていれば目的を達する。したがって、本発明で言う
非晶質化とは、完全なアモルファス状態およびそれに近
い超微粒子状態を包含するものとする。いずれにしても
、アルミ・スパイクに対するバリヤ性が向上し、しかも
表面モホロジーの劣化やアフタコロージョンの助長等の
問題が派生しない。本願の第2の発明では、上記非晶質
化を達成する手段として、不活性物質のイオン注入を行
う。この方法によれば、イオン種,注入エネルギー,ド
ース量等の条件を適宜設定することにより、薄いTi系
材料層について制御性良く所望の非晶質化を行うことが
可能となる。[Operation] The Ti-based material layer formed by vacuum thin film formation technology usually has a polycrystalline structure consisting of a collection of fine columnar crystals with a grain size of about 200 Å, but in order to improve its barrier properties, It is essential to inactivate grain boundaries, which provide fast diffusion paths for impurities. Conventionally, inactivation has been carried out by, for example, segregating oxygen at grain boundaries, but the problems with the resulting film are as described above using the TiON layer as an example. Therefore, the present inventor proposed the present invention, considering the idea of destroying the polycrystalline structure and eliminating the grain boundaries themselves, rather than inactivating the grain boundaries through oxygen segregation. be. If the grain boundaries are completely eliminated, the state will be amorphous, but in the present invention, the single crystal that makes up the polycrystalline structure is highly fine-grained, and the grain boundaries are substantially fast. If the particles are made so fine that they cannot serve as a diffusion route, the goal will be achieved. Therefore, the term "amorphous" as used in the present invention includes a completely amorphous state and an ultrafine particle state close to the completely amorphous state. In any case, the barrier properties against aluminum spikes are improved, and problems such as deterioration of surface morphology and promotion of after-corrosion do not arise. In the second invention of the present application, ion implantation of an inert substance is performed as a means for achieving the above-mentioned amorphization. According to this method, by appropriately setting conditions such as ion species, implantation energy, dose amount, etc., it is possible to make a thin Ti-based material layer into a desired amorphous state with good controllability.
【0010】0010
【実施例】以下、本発明の好適な実施例について説明す
る。本実施例は、本願の第2の発明をMOSトランジス
タのソース/ドレイン領域におけるコンタクト形成に適
用し、TiN層にN2 をイオン注入することにより非
晶質化した例である。このプロセスを、図1(a)ない
し(c)を参照しながら説明する。[Embodiments] Preferred embodiments of the present invention will be described below. This embodiment is an example in which the second invention of the present application is applied to contact formation in the source/drain region of a MOS transistor, and the TiN layer is made amorphous by ion-implanting N2. This process will be explained with reference to FIGS. 1(a) to 1(c).
【0011】まず、図1(a)に示されるように、Si
基板1上にたとえばLOCOS法によりフィールド酸化
膜2を形成し、該フィールド酸化膜2により規定される
素子形成領域に酸化シリコン等からなるゲート酸化膜3
を介してDOPOS等からなるゲート電極4を形成した
。次に、上記ゲート電極4をマスクとしてソース/ドレ
イン領域5を形成するための1回目のイオン注入を行っ
た後、CVD法およびRIE等により常法にしたがって
酸化シリコン等からなるサイドウォール6を形成した。
この後、上記ゲート電極4およびサイドウォール6とを
マスクとして前記ソース/ドレイン領域5の一部におい
て不純物濃度を高めるための2回目のイオン注入を行い
、LDD構造を形成した。さらに、基体の全面にたとえ
ばCVDにより酸化シリコン等を堆積させて層間絶縁膜
7を形成し、続いて該層間絶縁膜7をパターニングして
ソース/ドレイン領域5に臨むコンタクト・ホール8を
開口した。続いてTi/TiN系の2層構造のバリヤメ
タルを形成した。まず、下層側のTi層9は、一例とし
てAr流量50SCCM,ガス圧0.47Pa(3.5
mTorr),DCスパッタ・パワー4kW,基板温度
300℃の条件でスパッタリングを行うことにより、約
300Åの厚さに形成した。また、上層側のTiN層1
0は、一例としてN2 流量50SCCM,ガス圧0.
47Pa(3.5mTorr),DCスパッタ・パワー
6kW,基板温度300℃の条件で反応性スパッタリン
グを行うことにより、約700Åの厚さに形成した。First, as shown in FIG. 1(a), Si
A field oxide film 2 is formed on the substrate 1 by, for example, the LOCOS method, and a gate oxide film 3 made of silicon oxide or the like is formed in the element formation region defined by the field oxide film 2.
A gate electrode 4 made of DOPOS or the like was formed through the wafer. Next, after performing a first ion implantation to form source/drain regions 5 using the gate electrode 4 as a mask, sidewalls 6 made of silicon oxide or the like are formed in a conventional manner by CVD, RIE, etc. did. Thereafter, a second ion implantation was performed to increase the impurity concentration in a part of the source/drain region 5 using the gate electrode 4 and sidewall 6 as a mask, thereby forming an LDD structure. Furthermore, an interlayer insulating film 7 was formed by depositing silicon oxide or the like on the entire surface of the substrate by, for example, CVD, and then the interlayer insulating film 7 was patterned to open a contact hole 8 facing the source/drain region 5. Subsequently, a Ti/TiN-based two-layer barrier metal was formed. First, the lower Ti layer 9 is formed with an Ar flow rate of 50 SCCM and a gas pressure of 0.47 Pa (3.5
The film was formed to a thickness of about 300 Å by performing sputtering under the following conditions: mTorr), DC sputter power of 4 kW, and substrate temperature of 300°C. In addition, the upper TiN layer 1
0 is an example of N2 flow rate of 50SCCM and gas pressure of 0.
It was formed to a thickness of about 700 Å by performing reactive sputtering under the conditions of 47 Pa (3.5 mTorr), DC sputter power of 6 kW, and substrate temperature of 300°C.
【0012】次に、一例として注入エネルギー50ke
V,ドース量5×1015atom/cm2 の条件に
てN2 のイオン注入を基体の全面に行い、図1(b)
に示されるように、上記TiN層9を非晶質化TiN層
9aに変化させた。Next, as an example, the implantation energy is 50ke.
N2 ions were implanted into the entire surface of the substrate under conditions of V and a dose of 5 x 1015 atoms/cm2, as shown in Figure 1(b).
As shown in FIG. 2, the TiN layer 9 was changed to an amorphous TiN layer 9a.
【0013】さらに、スパッタリングによりAl−1%
Si層を約4000Åの厚さに成膜した。スパッタリン
グ条件は、一例としてAr流量100SCCM,ガス圧
0.47Pa(3.5mTorr),DCスパッタ・パ
ワー22.7kW,基板温度200℃とした。このとき
、基体の全面はAl−1%Si層に被覆され、コンタク
ト・ホール8の内部も鬆を発生することなく均一に埋め
込まれた。最後に、BCl3 /Cl2 系等の塩素系
混合ガスを使用してドライエッチングを行うことにより
、上記Al−1%Si層,非晶質化TiN層10a,お
よびTi層9を同時にパターニングし、図1(c)に示
されるようにAl系配線パターン11を形成した。この
ドライエッチングの終了後には、2層構造のバリヤメタ
ルの上層側にTiON層を用いた場合ほど顕著なアフタ
コロージョンは観察されなかった。Furthermore, by sputtering, Al-1%
A Si layer was deposited to a thickness of about 4000 Å. The sputtering conditions were, for example, an Ar flow rate of 100 SCCM, a gas pressure of 0.47 Pa (3.5 mTorr), a DC sputtering power of 22.7 kW, and a substrate temperature of 200°C. At this time, the entire surface of the substrate was covered with the Al-1%Si layer, and the inside of the contact hole 8 was also filled uniformly without forming any cavities. Finally, the Al-1%Si layer, the amorphous TiN layer 10a, and the Ti layer 9 are simultaneously patterned by performing dry etching using a chlorine-based mixed gas such as BCl3/Cl2-based gas. 1(c), an Al-based wiring pattern 11 was formed. After completion of this dry etching, no after-corrosion was observed as remarkable as when a TiON layer was used as the upper layer of the barrier metal of the two-layer structure.
【0014】上述のようにして形成されたMOSトラン
ジスタにおける非晶質化TiN層10aのバリヤ性を確
認するため、所定の温度にて30分間保持したMOSト
ランジスタのゲート電極に−5.5Vの電圧を印加して
接合リーク電流を測定した。この結果、上記MOSトラ
ンジスタは600℃でアニールを行った後にも何ら接合
リーク電流の増大を示さなかった。このことは、600
℃においても非晶質化TiN層10aがAlと反応せず
に有効なバリヤメタルとして機能し、ソース/ドレイン
領域5へのAlの突き抜けが防止されていることを意味
している。In order to confirm the barrier properties of the amorphous TiN layer 10a in the MOS transistor formed as described above, a voltage of -5.5V was applied to the gate electrode of the MOS transistor which was maintained at a predetermined temperature for 30 minutes. was applied to measure the junction leakage current. As a result, the MOS transistor did not exhibit any increase in junction leakage current even after annealing at 600°C. This means that 600
This means that the amorphous TiN layer 10a functions as an effective barrier metal without reacting with Al even at temperatures as high as 0.degree. C., thereby preventing Al from penetrating into the source/drain regions 5.
【0015】ところで、本発明は上述の実施例に何ら限
定されるものではなく、たとえば上記TiN層9を非晶
質化するためのイオン注入は、基体の全面について行わ
ずにたとえば適当なマスクを介してコンタクト部の近傍
においてのみ行うようにしても良い。また、注入する不
活性物質もTiNの化学的性質に顕著な変化をもたらす
ものでなければ上述のN2 に限られるものではなく、
たとえばAr,H2 ,Ti等をイオン注入することも
できる。By the way, the present invention is not limited to the above-described embodiments; for example, the ion implantation to make the TiN layer 9 amorphous is not carried out over the entire surface of the substrate, but may be carried out using a suitable mask, for example. It is also possible to perform this only in the vicinity of the contact portion via the contact portion. Furthermore, the inert substance to be injected is not limited to the above-mentioned N2, as long as it does not cause a significant change in the chemical properties of TiN.
For example, ions of Ar, H2, Ti, etc. can also be implanted.
【0016】[0016]
【発明の効果】以上の説明からも明らかなように、本発
明を適用すれば低抵抗であり、かつバリヤ性,段差被覆
性に優れるコンタクト形成が可能となる。したがって、
本発明は微細なデザイン・ルールにもとづき高集積度お
よび高性能を要求される半導体装置の製造に極めて好適
である。As is clear from the above description, by applying the present invention, it is possible to form a contact with low resistance and excellent barrier properties and step coverage. therefore,
The present invention is extremely suitable for manufacturing semiconductor devices that require high integration and high performance based on fine design rules.
【図1】 本願の第2の発明をMOSトランジスタの
製造に適用した一例をその工程順にしたがって示す概略
断面図であり、(a)はコンタクト・ホールの形成され
た層間絶縁膜を被覆してTi層とTiN層からなる2層
構造のバリヤメタルが積層された状態、(b)はイオン
注入により上記TiN層が非晶質化された状態、(c)
はAl系配線パターンが形成された状態をそれぞれ示す
。FIG. 1 is a schematic cross-sectional view showing an example in which the second invention of the present application is applied to the manufacture of a MOS transistor according to the process order, in which (a) an interlayer insulating film in which a contact hole is formed is covered and a Ti (b) is a state in which the TiN layer has been made amorphous by ion implantation; (c)
1 and 2 respectively show a state in which an Al-based wiring pattern is formed.
1 ・・・Si基板
4 ・・・ゲート電極
5 ・・・ソース/ドレイン領域7 ・・
・層間絶縁膜
8 ・・・コンタクト・ホール
9 ・・・Ti層
10 ・・・TiN層
10a・・・非晶質化TiN層
11 ・・・Al系配線パターン1...Si substrate 4...Gate electrode 5...Source/drain region 7...
-Interlayer insulating film 8...Contact hole 9...Ti layer 10...TiN layer 10a...Amorphous TiN layer 11...Al-based wiring pattern
Claims (2)
少なくとも底部および側壁部を非晶質化されたチタン系
材料層で被覆する工程と、少なくとも前記接続孔を充填
するごとくアルミニウム系材料層を形成する工程とを有
することを特徴とする配線形成方法。1. Covering at least the bottom and sidewalls of a connection hole opened in an insulating film on a substrate with an amorphous titanium-based material layer, and coating an aluminum-based material so as to fill at least the connection hole. 1. A wiring forming method, comprising the step of forming a layer.
オン注入することにより非晶質化されてなることを特徴
とする請求項1記載の配線形成方法。2. The wiring forming method according to claim 1, wherein the titanium-based material layer is made amorphous by ion-implanting an inert substance.
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4733891A JP3252397B2 (en) | 1991-02-21 | 1991-02-21 | Wiring formation method |
KR1019920002340A KR100214036B1 (en) | 1991-02-19 | 1992-02-18 | Aluminum metallization method |
US08/283,255 US5397744A (en) | 1991-02-19 | 1994-07-29 | Aluminum metallization method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4733891A JP3252397B2 (en) | 1991-02-21 | 1991-02-21 | Wiring formation method |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH04267359A true JPH04267359A (en) | 1992-09-22 |
JP3252397B2 JP3252397B2 (en) | 2002-02-04 |
Family
ID=12772407
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP4733891A Expired - Fee Related JP3252397B2 (en) | 1991-02-19 | 1991-02-21 | Wiring formation method |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP3252397B2 (en) |
Cited By (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH09148328A (en) * | 1995-11-24 | 1997-06-06 | Nec Corp | Manufacture of semiconductor device |
JPH09172077A (en) * | 1995-12-20 | 1997-06-30 | Sony Corp | Semiconductor device and its manufacturing method |
US5998870A (en) * | 1994-06-10 | 1999-12-07 | Samsung Electronics Co., Ltd. | Wiring structure of semiconductor device and method for manufacturing the same |
US6475912B1 (en) | 1998-06-01 | 2002-11-05 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device and method and apparatus for fabricating the same while minimizing operating failures and optimizing yield |
KR100430684B1 (en) * | 1996-12-31 | 2004-07-30 | 주식회사 하이닉스반도체 | Method of forming thermally stable metal line of semiconductor device using doubly or triply deposited amorphous and crystalline tungsten nitride layer |
US6870263B1 (en) * | 1998-03-31 | 2005-03-22 | Infineon Technologies Ag | Device interconnection |
US7045399B2 (en) | 1992-12-09 | 2006-05-16 | Semiconductor Energy Laboratory Co., Ltd. | Electronic circuit |
JP2016213414A (en) * | 2015-05-13 | 2016-12-15 | 富士電機株式会社 | Semiconductor device and manufacturing method of the same |
US9587208B2 (en) | 2012-06-13 | 2017-03-07 | Mitsubishi Gas Chemical Company, Inc. | Cleaning liquid composition, method for cleaning semiconductor element, and method for manufacturing semiconductor element |
-
1991
- 1991-02-21 JP JP4733891A patent/JP3252397B2/en not_active Expired - Fee Related
Cited By (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7045399B2 (en) | 1992-12-09 | 2006-05-16 | Semiconductor Energy Laboratory Co., Ltd. | Electronic circuit |
US7547916B2 (en) | 1992-12-09 | 2009-06-16 | Semiconductor Energy Laboratory Co., Ltd. | Electronic circuit |
US7105898B2 (en) | 1992-12-09 | 2006-09-12 | Semiconductor Energy Laboratory Co., Ltd. | Electronic circuit |
US7061016B2 (en) | 1992-12-09 | 2006-06-13 | Semiconductor Energy Laboratory Co., Ltd. | Electronic circuit |
US5998870A (en) * | 1994-06-10 | 1999-12-07 | Samsung Electronics Co., Ltd. | Wiring structure of semiconductor device and method for manufacturing the same |
JPH09148328A (en) * | 1995-11-24 | 1997-06-06 | Nec Corp | Manufacture of semiconductor device |
JPH09172077A (en) * | 1995-12-20 | 1997-06-30 | Sony Corp | Semiconductor device and its manufacturing method |
KR100430684B1 (en) * | 1996-12-31 | 2004-07-30 | 주식회사 하이닉스반도체 | Method of forming thermally stable metal line of semiconductor device using doubly or triply deposited amorphous and crystalline tungsten nitride layer |
US6870263B1 (en) * | 1998-03-31 | 2005-03-22 | Infineon Technologies Ag | Device interconnection |
US6906420B2 (en) | 1998-06-01 | 2005-06-14 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device |
US6683381B2 (en) | 1998-06-01 | 2004-01-27 | Matsushita Electric Industrsial Co., Ltd. | Semiconductor device having a copper interconnect layer |
US6475912B1 (en) | 1998-06-01 | 2002-11-05 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device and method and apparatus for fabricating the same while minimizing operating failures and optimizing yield |
US9587208B2 (en) | 2012-06-13 | 2017-03-07 | Mitsubishi Gas Chemical Company, Inc. | Cleaning liquid composition, method for cleaning semiconductor element, and method for manufacturing semiconductor element |
JP2016213414A (en) * | 2015-05-13 | 2016-12-15 | 富士電機株式会社 | Semiconductor device and manufacturing method of the same |
Also Published As
Publication number | Publication date |
---|---|
JP3252397B2 (en) | 2002-02-04 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP3781666B2 (en) | Method for forming gate electrode and gate electrode structure | |
KR100214036B1 (en) | Aluminum metallization method | |
US5360996A (en) | Titanium nitride/titanium silicide multiple layer barrier with preferential (111) crystallographic orientation on titanium nitride surface | |
JP3358328B2 (en) | Method of forming high melting point metal film | |
US7271092B2 (en) | Boron incorporated diffusion barrier material | |
US5221853A (en) | MOSFET with a refractory metal film, a silicide film and a nitride film formed on and in contact with a source, drain and gate region | |
JPH10256256A (en) | Formation of copper metal wiring of semiconductor device | |
JPH08213343A (en) | Semiconductor device and manufacture thereof | |
US6879043B2 (en) | Electrode structure and method for fabricating the same | |
KR100755121B1 (en) | Method for forming electrode structure and method for fabricating semiconductor device | |
JPH04267359A (en) | Formation of metal layer | |
KR0161380B1 (en) | Transistor of semiconductor device and their manufacturing method | |
JP4347479B2 (en) | Field effect transistor | |
JPH06204170A (en) | Semiconductor device and its manufacture | |
US6087259A (en) | Method for forming bit lines of semiconductor devices | |
JPH05335330A (en) | Embedding-formation of connection hole | |
JP3066031B2 (en) | Semiconductor device | |
JPH0126172B2 (en) | ||
JP3067433B2 (en) | Method for manufacturing semiconductor device | |
JPH04196122A (en) | Manufacture of semiconductor device | |
JP3360835B2 (en) | Wiring formation method | |
JPH0795539B2 (en) | Integrated circuit and manufacturing method thereof | |
JPH07297380A (en) | Connection structure of wiring and manufacture thereof | |
JP3451634B2 (en) | Metal material deposition method | |
JPH09237769A (en) | Manufacture of semiconductor device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
LAPS | Cancellation because of no payment of annual fees |