JP3066031B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JP3066031B2 JP3066031B2 JP1185359A JP18535989A JP3066031B2 JP 3066031 B2 JP3066031 B2 JP 3066031B2 JP 1185359 A JP1185359 A JP 1185359A JP 18535989 A JP18535989 A JP 18535989A JP 3066031 B2 JP3066031 B2 JP 3066031B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- semiconductor device
- polycrystalline silicon
- present
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、半導体装置における配線接続に関する。The present invention relates to a wiring connection in a semiconductor device.
従来の半導体装置における配線接続構造は、シリコン
基板に形成された拡散層あるいは、多結晶シリコン層あ
るいは、アモルファスシリコン層上に、連続スパッター
法により形成されたTi、TiN、Al−Siの三層構造であっ
た。The wiring connection structure in a conventional semiconductor device has a three-layer structure of Ti, TiN, and Al-Si formed by a continuous sputtering method on a diffusion layer formed on a silicon substrate, a polycrystalline silicon layer, or an amorphous silicon layer. Met.
しかし、上述の従来技術では、TiNのピンホールが存
在し、Alのスパイクにより拡散層が破壊され、リークの
原因となった。又、多結晶シリコンとAlの接続では、多
結晶シリコンへのAlの侵入が起き、Gate膜不良を引き起
こす事があった。さらに、アモルファスシリコンを用い
た場合は、前述、拡散層より破壊が顕著に現われ絶縁性
が損われる場合が多くみられると言う問題を有する。However, in the above-described prior art, a pinhole of TiN was present, and the diffusion layer was destroyed by spikes of Al, causing a leak. In addition, in the connection between polycrystalline silicon and Al, intrusion of Al into the polycrystalline silicon occurs, which may cause a gate film defect. Further, when amorphous silicon is used, there is a problem that the breakdown is more remarkable than the diffusion layer and the insulating property is often deteriorated.
本発明は、このような問題を解決するもので、その目
的とするところは、配線接続における、Alのスパイクに
よるリークを防止し、バリア性の向上による安定した配
線接続を得ることが可能な半導体装置を提供するところ
にある。An object of the present invention is to solve such a problem. An object of the present invention is to prevent a leak due to Al spikes in a wiring connection and to obtain a stable wiring connection by improving a barrier property. Equipment.
本発明の半導体装置は、アモルファスシリコン層、不
純物を含有する多結晶シリコン層、あるいはシリコン基
板表面に設置された拡散層と、前記アモルファスシリコ
ン層、前記多結晶シリコン層あるいは前記拡散層上に設
置され、表面に酸素プラズマによって酸化処理された酸
化処理膜を有する金属チッ化膜層と、前記金属チッ化膜
層上に設置された金属層と、を有することを特徴とす
る。The semiconductor device of the present invention includes an amorphous silicon layer, a polycrystalline silicon layer containing impurities, or a diffusion layer provided on the surface of a silicon substrate, and the amorphous silicon layer, the polycrystalline silicon layer or the diffusion layer provided on the diffusion layer. And a metal nitride film layer having an oxidized film on its surface oxidized by oxygen plasma, and a metal layer provided on the metal nitride film layer.
また、前記金属層がAlを含む金属層であることを特徴
とする。Further, the invention is characterized in that the metal layer is a metal layer containing Al.
第１図は、本発明の実施例における半導体装置の断面
図を示す。第２図、第３図は、本発明の他の実施例にお
ける半導体装置の断面図を示す。FIG. 1 is a sectional view of a semiconductor device according to an embodiment of the present invention. 2 and 3 are cross-sectional views of a semiconductor device according to another embodiment of the present invention.
以下、本発明の実施例を詳細に説明する。 Hereinafter, embodiments of the present invention will be described in detail.
まず、シリコン基板101上に酸化膜102を形成し、その
後、高濃度に不純物拡散された多結晶シリコン層103を
形成し、該、多結晶シリコン層103上に気相成長法によ
り層間絶縁膜104を形成し、その後、多結晶シリコン層1
03上をフォトリソ技術及びエッチング技術によりシリコ
ン酸化膜を除去する。その後、多結晶シリコン層103上
の開孔部に、気相成長法によりアモルファスシリコン層
105を形成し、その後、スパッター法により、Ti層106、
TiN層107を連続スパッタする。その後、酸素プラズマ20
0W30秒程度でTiN層107の酸化処理108を行ない、TiN層の
ピンホールを低減させる。その後、スパッタ法によりAl
−Si109を形成し、フォトリソ技術及びエッチング技術
により所望のパターンに加工する。First, an oxide film 102 is formed on a silicon substrate 101, and then a polycrystalline silicon layer 103 in which impurities are diffused at a high concentration is formed, and an interlayer insulating film 104 is formed on the polycrystalline silicon layer 103 by a vapor growth method. To form a polycrystalline silicon layer 1
The silicon oxide film on 03 is removed by photolithography and etching. Then, an amorphous silicon layer is formed in the opening on the polycrystalline silicon layer 103 by a vapor phase growth method.
105, and then a Ti layer 106,
The TiN layer 107 is continuously sputtered. After that, oxygen plasma 20
Oxidation 108 of the TiN layer 107 is performed in about 30 seconds at 0W to reduce pinholes in the TiN layer. Then, the Al
-Form Si109 and process it into a desired pattern by photolithography and etching.
以上の工程を経て、本発明の実施例における半導体装
置の配線接続が完成する。上記、実施例のTiN層107上へ
の酸化処理は、酸素プラズマ処理について説明したが、
オゾン100％の雰囲気中にて10分程度処理し、シリコン
基板は100℃で30分程度放置することにより、上記、酸
素プラズマ処理と同様の効果が得られる。Through the above steps, the wiring connection of the semiconductor device in the embodiment of the present invention is completed. As described above, the oxidation treatment on the TiN layer 107 in the embodiment has been described with respect to the oxygen plasma treatment.
By treating in an atmosphere of 100% ozone for about 10 minutes and leaving the silicon substrate at 100 ° C. for about 30 minutes, the same effect as the above-described oxygen plasma treatment can be obtained.
第２図は、本発明の他の実施例における半導体装置の
断面図である。すなわち、シリコン基板201上にイオン
打込み法を用いてN+拡散層（不純物層）202を形成し、
その後、シリコン酸化膜を気相成長法により層間絶縁膜
203を形成し配線接続部分をフォトリソ技術及びエッチ
ング技術によりシリコン酸化膜を除去する。その後、Ti
層204、TiN層205、TiN層の酸化処理206、Al−Si層207の
形成方法は、第１図と同様である。FIG. 2 is a sectional view of a semiconductor device according to another embodiment of the present invention. That is, an N + diffusion layer (impurity layer) 202 is formed on a silicon substrate 201 by ion implantation,
After that, a silicon oxide film is formed on the interlayer insulating film by a vapor growth method.
203 is formed, and the silicon oxide film is removed from the wiring connection portion by photolithography and etching. Then Ti
The method of forming the layer 204, the TiN layer 205, the oxidation treatment 206 of the TiN layer, and the Al—Si layer 207 is the same as that in FIG.
第３図は、本発明のさらに他の実施例における半導体
装置の断面図である。シリコン基板301上に酸化膜302を
形成し、その後、高濃度に不純物拡散された多結晶シリ
コン層303を形成し、該、多結晶シリコン層303上に気相
成長法により層間絶縁膜304を形成し、配線接続部分を
フォトリソ技術及びエッチング法によりシリコン酸化膜
を除去する。その後、Ti層305、TiN層306、TiN層の酸化
処理307、Al−Si層308の形成方法は、第１図、第２図と
同様である。又、第１図、第２図、第３図ではTiN層で
説明したが、タングステン等でも構わない。FIG. 3 is a sectional view of a semiconductor device according to still another embodiment of the present invention. An oxide film 302 is formed on a silicon substrate 301, and then a polycrystalline silicon layer 303 with a high concentration of impurity diffusion is formed, and an interlayer insulating film 304 is formed on the polycrystalline silicon layer 303 by a vapor growth method. Then, the silicon oxide film is removed from the wiring connection portion by a photolithography technique and an etching method. After that, the method of forming the Ti layer 305, the TiN layer 306, the oxidation treatment 307 of the TiN layer, and the Al—Si layer 308 is the same as that shown in FIGS. Although the TiN layer has been described in FIGS. 1, 2 and 3, it may be made of tungsten or the like.
以上、本発明の半導体装置によれば、金属チッ化膜の
表面に酸素プラズマによって酸化処理された酸化処理膜
があるので、金属チッ化膜のピンホールが低減し、金属
層のスパイクによるアモルファスシリコン層、多結晶シ
リコン層、拡散層破壊を防止することができる。As described above, according to the semiconductor device of the present invention, since the surface of the metal nitride film has an oxidized film oxidized by oxygen plasma, pinholes in the metal nitride film are reduced, and the Layer, a polycrystalline silicon layer, and a diffusion layer can be prevented from being destroyed.
さらに、金属チッ化膜表面の酸化処理膜は酸素プラズ
マによるものなので、反応性の高い酸素ラジカルが酸化
処理の反応種となり、低温かつ短時間での酸化処理が可
能で、半導体装置にかかる熱的な負荷を回避することが
できる。Furthermore, since the oxidized film on the surface of the metal nitride film is formed by oxygen plasma, highly reactive oxygen radicals serve as a reactive species for the oxidizing process, and the oxidizing process can be performed at a low temperature and in a short time. Load can be avoided.
第１図は、本発明の半導体装置の一実施例を示す断面
図。第２図及び第３図は、本発明の半導体装置の他の実
施例を示す断面図。 101、201、301……シリコン基板 102、302……酸化膜 202……N+拡散層 103、303……多結晶シリコン層 104、203、304……層間絶縁膜 105……アモルファスシリコン層 106、204、305……Ti層 107、205、306……TiN層 108、206、307……酸化処理膜 109、207、308……Al−Si層FIG. 1 is a sectional view showing one embodiment of a semiconductor device of the present invention. 2 and 3 are cross-sectional views showing another embodiment of the semiconductor device of the present invention. 101, 201, 301 ... silicon substrate 102, 302 ... oxide film 202 ... N + diffusion layer 103, 303 ... polycrystalline silicon layer 104, 203, 304 ... interlayer insulating film 105 ... amorphous silicon layer 106, 204, 305: Ti layer 107, 205, 306: TiN layer 108, 206, 307: Oxidized film 109, 207, 308: Al-Si layer
───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 平１−144625（ＪＰ，Ａ) 特開 昭62−69643（ＪＰ，Ａ) 特開 昭63−213959（ＪＰ，Ａ) 特開 平１−235334（ＪＰ，Ａ) 特開 平１−304727（ＪＰ，Ａ) 特開 平２−43726（ＪＰ，Ａ) Ａｐｐｌ．Ｐｈｙｓ．Ｌｅｔｔ．47 （５），１ Ｓｅｐｔｅｍｂｅｒ 1985 ｐｐ471−473 ──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-1-144625 (JP, A) JP-A-62-69643 (JP, A) JP-A-63-213959 (JP, A) JP-A-1- 235334 (JP, A) JP-A-1-304727 (JP, A) JP-A-2-43726 (JP, A) Appl. Phys. Lett. 47 (5), 1 September, 1985, pp. 471-473
Claims (1)
る多結晶シリコン層、あるいはシリコン基板表面に設置
された拡散層と、 前記アモルファスシリコン層、前記多結晶シリコン層あ
るいは前記拡散層上に設置され、表面に酸素プラズマに
よって酸化処理された酸化処理膜を有する金属チッ化膜
層と、 前記金属チッ化膜層上に設置されたALを含む金属層と、 を有することを特徴とする半導体装置。1. An amorphous silicon layer, a polycrystalline silicon layer containing impurities, or a diffusion layer provided on a surface of a silicon substrate, and a diffusion layer provided on the amorphous silicon layer, the polycrystalline silicon layer, or the diffusion layer. A metal nitride film layer having an oxidized film oxidized by oxygen plasma; and a metal layer containing AL provided on the metal nitride film layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1185359A JP3066031B2 (en) | 1989-07-18 | 1989-07-18 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1185359A JP3066031B2 (en) | 1989-07-18 | 1989-07-18 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0350730A JPH0350730A (en) | 1991-03-05 |
| JP3066031B2 true JP3066031B2 (en) | 2000-07-17 |
Family
ID=16169414
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1185359A Expired - Lifetime JP3066031B2 (en) | 1989-07-18 | 1989-07-18 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3066031B2 (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0594969A (en) * | 1991-10-01 | 1993-04-16 | Sharp Corp | Manufacture of semiconductor device |
| JPH0594965A (en) * | 1991-10-01 | 1993-04-16 | Sharp Corp | Manufacture of semiconductor device |
| KR100274748B1 (en) * | 1996-12-30 | 2001-01-15 | 김영환 | Method for forming barrier metal film of semiconductor device |
| KR100318433B1 (en) * | 1999-12-28 | 2001-12-24 | 박종섭 | Method for forming local interconnection in ferroelectric memory device |
| KR100401498B1 (en) * | 2001-01-11 | 2003-10-17 | 주식회사 하이닉스반도체 | Method of forming barrier layers in semiconductor devices |
-
1989
- 1989-07-18 JP JP1185359A patent/JP3066031B2/en not_active Expired - Lifetime
Non-Patent Citations (1)
| Title |
|---|
| Ａｐｐｌ．Ｐｈｙｓ．Ｌｅｔｔ．４７（５），１ Ｓｅｐｔｅｍｂｅｒ １９８５ ｐｐ４７１−４７３ |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0350730A (en) | 1991-03-05 |
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