JPH0350730A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0350730A JPH0350730A JP18535989A JP18535989A JPH0350730A JP H0350730 A JPH0350730 A JP H0350730A JP 18535989 A JP18535989 A JP 18535989A JP 18535989 A JP18535989 A JP 18535989A JP H0350730 A JPH0350730 A JP H0350730A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- silicon
- polycrystalline silicon
- silicon layer
- tin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims description 13
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 18
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 11
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 11
- 239000010703 silicon Substances 0.000 claims abstract description 11
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 9
- 229910052751 metal Inorganic materials 0.000 claims abstract description 8
- 239000002184 metal Substances 0.000 claims abstract description 8
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 6
- 239000001301 oxygen Substances 0.000 claims abstract description 6
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 6
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 claims abstract description 4
- 239000007789 gas Substances 0.000 claims abstract description 3
- 150000004767 nitrides Chemical class 0.000 claims description 5
- 239000010410 layer Substances 0.000 abstract description 49
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 abstract description 11
- 238000000034 method Methods 0.000 abstract description 7
- 239000000758 substrate Substances 0.000 abstract description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 5
- 238000005530 etching Methods 0.000 abstract description 5
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 5
- 230000004888 barrier function Effects 0.000 abstract description 3
- 239000011229 interlayer Substances 0.000 abstract description 3
- 230000001590 oxidative effect Effects 0.000 abstract 2
- 229910018125 Al-Si Inorganic materials 0.000 abstract 1
- 229910018520 Al—Si Inorganic materials 0.000 abstract 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 abstract 1
- 229920005591 polysilicon Polymers 0.000 abstract 1
- 238000009792 diffusion process Methods 0.000 description 5
- 230000003647 oxidation Effects 0.000 description 4
- 238000007254 oxidation reaction Methods 0.000 description 4
- 238000001947 vapour-phase growth Methods 0.000 description 4
- 230000015556 catabolic process Effects 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 238000009832 plasma treatment Methods 0.000 description 2
- 230000007547 defect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 210000004709 eyebrow Anatomy 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】 〔産業上の利用分野１ 本発明は、半導体装置における配線接続に関する。[Detailed description of the invention] [Industrial application field 1 The present invention relates to wiring connections in semiconductor devices.
［従来の技術］
従来の半導体装置における配線接続構造は、シリコン基
板に形成された拡散層あるいは、多結晶シリコン層ある
いは、アモルファスシリコン層上に、連続スパッター法
により形成されたＴｉ、ＴｉＮ、Ａｌ−３ｉの三層構造
であった。[Prior Art] A wiring connection structure in a conventional semiconductor device is a Ti, TiN, Al- It had a 3i three-layer structure.
［発明が解決しようとする課題］
しかし、上述の従来技術では、ＴｉＮのピンホールが存
在し、ＡＩのスパイクにより拡散層が破壊され、リーク
の原因となった。又、多結晶シリコンとＡＩの接続では
、多結晶シリコンへのＡｌの侵入が起き、Ｇａｔｅ膜不
良を引き起こす事があった。さらに、アモルファスシリ
コンを用いた場合は、前述、拡散層より破壊が顕著に現
われ絶縁性が損われる場合が多くみられると言う問題を
有する。[Problems to be Solved by the Invention] However, in the above-mentioned conventional technology, there were pinholes in TiN, and the diffusion layer was destroyed by the spikes of AI, causing leakage. Furthermore, in the connection between polycrystalline silicon and AI, Al may invade the polycrystalline silicon, causing gate film defects. Furthermore, when amorphous silicon is used, there is a problem in that, as mentioned above, breakdown appears more prominently than in the diffusion layer, and insulation properties are often impaired.
本発明は、このような問題を解決するもので。The present invention is intended to solve such problems.
その目的とするところは、配線接続における、Ａｔのス
パイクによるリークを防止し、バリア性の向上による安
定した配線接続を得ることが可能な半導体装置を提供す
るところにある。The purpose is to provide a semiconductor device that can prevent leakage due to At spikes in wiring connections and obtain stable wiring connections by improving barrier properties.
［課題を解決するための手段］
本発明の半導体装置は、シリコンあ・るいは、多結晶シ
リコン層あるいは、アモルファスシリコン層を有し、該
、シリコンあるいは、多結晶シリコン層あるいは、アモ
ルファスシリコン層上には、酸素プラズマあるいは、オ
ゾンガスにより表面が酸化処理された金属チッ化膜層を
有し、該、金属チッ化膜層上にはＭｅｔａ１層があるこ
とを特徴とする。[Means for Solving the Problems] A semiconductor device of the present invention has a silicon, polycrystalline silicon layer, or amorphous silicon layer, and has a silicon, polycrystalline silicon layer, or amorphous silicon layer. The metal nitride film layer has a metal nitride film layer whose surface is oxidized by oxygen plasma or ozone gas, and a Meta1 layer is provided on the metal nitride film layer.
［実 施 例］
第１図は、本発明の実施例における半導体装置の断面図
を示す、第２図、第３図は、本発明の他の実施例におけ
る半導体装置の断面図を示す。[Embodiment] FIG. 1 shows a cross-sectional view of a semiconductor device according to an example of the present invention, and FIGS. 2 and 3 show cross-sectional views of a semiconductor device according to another example of the present invention.
以下、本発明の実施例を詳細に説明する。Examples of the present invention will be described in detail below.
まず、シリコン基板１０１上に酸化膜１０２を形成し、
その後、高濃度に不純物拡散された多結晶シリコン層１
０３を形成し、該、多結晶シリコン層１０３上に気相成
長法により眉間絶縁膜１０４を形成し、その後、多結晶
シリコン層１０３上をフォトリソ技術及びエツチング技
術によりシリコン酸化膜を除去する。その後、多結晶シ
リコン層１０３上の開孔部に、気相成長法によりアモル
ファスシリコン層１０５を形成し、その後、スパッター
法により、Ｔｉ層１０６、ＴｉＮ［１０７を連続スパッ
タする。その後、酸素プラズマ２００Ｗ３０秒程度でＴ
ｉＮＮ１０７の酸化処理１０８を行ない、ＴｉＮ層のピ
ンホールを低減させる。その後、スパッタ法によりＡｌ
−３ｉｌ。First, an oxide film 102 is formed on a silicon substrate 101,
After that, a polycrystalline silicon layer 1 in which impurities are diffused at a high concentration.
03 is formed, and a glabellar insulating film 104 is formed on the polycrystalline silicon layer 103 by vapor phase growth, and then the silicon oxide film is removed on the polycrystalline silicon layer 103 by photolithography and etching. Thereafter, an amorphous silicon layer 105 is formed in the opening on the polycrystalline silicon layer 103 by a vapor phase growth method, and then a Ti layer 106 and TiN[107] are successively sputtered by a sputtering method. After that, use oxygen plasma at 200W for about 30 seconds to
Oxidation treatment 108 of the iNN 107 is performed to reduce pinholes in the TiN layer. After that, Al
-3il.
９を形成し、）オドリソ技術及びエツチング技術により
所望のパターンに加工する。9) and processed into a desired pattern by lithography and etching techniques.
以上の工程を経て、本発明の実施例における半導体装置
の配線接続が完成する。上記、実施例のＴｉＮ層１０７
上への酸化処理は、酸素プラズマ処理について説明した
が、オゾン１００％の雰囲気中にて１０分程度処理し、
シリコン基板は１００℃で３０分程度放置することによ
り、上記、酸素プラズマ処理と同様の効果が得られる。Through the above steps, the wiring connection of the semiconductor device according to the embodiment of the present invention is completed. The TiN layer 107 of the above example
The above oxidation treatment was explained as oxygen plasma treatment, but the treatment was performed in an atmosphere of 100% ozone for about 10 minutes.
By leaving the silicon substrate at 100° C. for about 30 minutes, the same effect as the above oxygen plasma treatment can be obtained.
第２図は、本発明の他の実施例における半導体装置の断
面図である。すなわち、シリコン基板２０１上にイオン
打込み法を用いてＮ０拡散層２０２を形成し、その後、
シリコン酸化膜を気相成長法により眉間絶縁膜２０３を
形成し配線接続部分をフォトリソ技術及びエツチング技
術によりシリコン酸化膜を除去する。その後、Ｔｉ層２
０４、ＴｉＮ層２０５、ＴｉＮ層の酸化処理２０６、Ａ
ｌ−５ｉ層２０６の形成方法は、第１図と同様である。FIG. 2 is a sectional view of a semiconductor device according to another embodiment of the present invention. That is, an N0 diffusion layer 202 is formed on a silicon substrate 201 using an ion implantation method, and then,
An insulating film 203 between the eyebrows is formed using a silicon oxide film by vapor phase growth, and the silicon oxide film is removed from the wiring connection portion by photolithography and etching. After that, Ti layer 2
04, TiN layer 205, TiN layer oxidation treatment 206, A
The method of forming the l-5i layer 206 is the same as that shown in FIG.
第３図は、本発明のさらに他の実施例における半導体装
置の断面図である。シリコン基板３０１上に酸化膜３０
２を形成し、その後、高濃度に不純物拡散された多結晶
シリコン層３０３を形成し、該、多結晶シリコン層３０
３上に気相成長法により層間絶縁膜３０４を形成し、配
線接続部分をフォトリソ技術及びエツチング法によりシ
リコン酸化膜を除去する。その後、Ｔｉ層３０５、Ｔｉ
Ｎ層３０６、ＴｉＮ層の酸化処理３０７．Ａｌ−５ｉ層
３０８の形成方法は、第１図、第２図と同様である。又
、第１図、第２図、第３図ではＴｉＮ層で説明したが、
タングステン等でも構わない。FIG. 3 is a sectional view of a semiconductor device in still another embodiment of the present invention. Oxide film 30 on silicon substrate 301
2 is formed, and then a polycrystalline silicon layer 303 in which impurities are diffused at a high concentration is formed, and the polycrystalline silicon layer 30
An interlayer insulating film 304 is formed on the substrate 3 by vapor phase growth, and the silicon oxide film is removed from the wiring connection portion by photolithography and etching. After that, the Ti layer 305, the Ti
Oxidation treatment of N layer 306 and TiN layer 307. The method of forming the Al-5i layer 308 is the same as that shown in FIGS. 1 and 2. In addition, although the TiN layer was explained in FIGS. 1, 2, and 3,
Tungsten or the like may also be used.
［発明の効果］
以上、述べたように本発明によれば、ＴｉＮのピンホー
ルが低減し、配線接続時にＡ１のスパイクによる拡散層
破壊やアモルファスシリコン層破壊によるリークが防止
でき、バリア性の向上による安定した高品質な配線接続
が可能となる。[Effects of the Invention] As described above, according to the present invention, pinholes in TiN are reduced, leakage due to diffusion layer breakdown due to A1 spikes and amorphous silicon layer breakdown during wiring connection can be prevented, and barrier properties are improved. This enables stable, high-quality wiring connections.
第１図は、本発明の半導体装置の一実施例を示す断面図
、第２図及び第３図は、本発明の半導体装置の他の実施
例を示す断面図。
１０１．２０１．３０１・・シリコン基板１０２．３０
２・・・・・・酸化膜
２０２・・・・・・・・・・Ｎ４拡散層１０３．３０３
・・・・・・多結晶シリコン層１０４．２０３．３０４
・・層間絶縁膜１０５・・・・・・・・・・アモルファ
スシリコン層
１０６．２０４．３０５・・Ｔｉ層
１０７．２０５．３０６・・ＴｉＮ層
１０８．
２０６．
３０７ ・
・酸化処理膜
１０９．
２０７゜
３０８ ・
・Ａｌ−３ｉ層
以
上FIG. 1 is a sectional view showing one embodiment of the semiconductor device of the invention, and FIGS. 2 and 3 are sectional views showing other embodiments of the semiconductor device of the invention. 101.201.301...Silicon substrate 102.30
2...Oxide film 202...N4 diffusion layer 103.303
...Polycrystalline silicon layer 104.203.304
...Interlayer insulating film 105...Amorphous silicon layer 106.204.305...Ti layer 107.205.306...TiN layer 108. 206. 307 ・・Oxidized film 109. 207゜308 ・ ・Al-3i layer or more
Claims (1)
ファスシリコン層を有し、該シリコンあるいは、多結晶
シリコン層あるいは、アモルファスシリコン層上には、
酸素プラズマあるいはオゾンガスにより表面が酸化処理
された金属チッ化膜層を有し、該、金属チッ化膜層上に
は金属層がある構造を有する半導体装置。It has a silicon, polycrystalline silicon layer, or amorphous silicon layer, and on the silicon, polycrystalline silicon layer, or amorphous silicon layer,
A semiconductor device having a structure including a metal nitride film layer whose surface is oxidized by oxygen plasma or ozone gas, and a metal layer on the metal nitride film layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1185359A JP3066031B2 (en) | 1989-07-18 | 1989-07-18 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1185359A JP3066031B2 (en) | 1989-07-18 | 1989-07-18 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0350730A true JPH0350730A (en) | 1991-03-05 |
| JP3066031B2 JP3066031B2 (en) | 2000-07-17 |
Family
ID=16169414
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1185359A Expired - Lifetime JP3066031B2 (en) | 1989-07-18 | 1989-07-18 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3066031B2 (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0594969A (en) * | 1991-10-01 | 1993-04-16 | Sharp Corp | Manufacture of semiconductor device |
| JPH0594965A (en) * | 1991-10-01 | 1993-04-16 | Sharp Corp | Manufacture of semiconductor device |
| KR100274748B1 (en) * | 1996-12-30 | 2001-01-15 | 김영환 | Method for forming barrier metal film of semiconductor device |
| KR100318433B1 (en) * | 1999-12-28 | 2001-12-24 | 박종섭 | Method for forming local interconnection in ferroelectric memory device |
| KR100401498B1 (en) * | 2001-01-11 | 2003-10-17 | 주식회사 하이닉스반도체 | Method of forming barrier layers in semiconductor devices |
-
1989
- 1989-07-18 JP JP1185359A patent/JP3066031B2/en not_active Expired - Lifetime
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0594969A (en) * | 1991-10-01 | 1993-04-16 | Sharp Corp | Manufacture of semiconductor device |
| JPH0594965A (en) * | 1991-10-01 | 1993-04-16 | Sharp Corp | Manufacture of semiconductor device |
| KR100274748B1 (en) * | 1996-12-30 | 2001-01-15 | 김영환 | Method for forming barrier metal film of semiconductor device |
| KR100318433B1 (en) * | 1999-12-28 | 2001-12-24 | 박종섭 | Method for forming local interconnection in ferroelectric memory device |
| KR100401498B1 (en) * | 2001-01-11 | 2003-10-17 | 주식회사 하이닉스반도체 | Method of forming barrier layers in semiconductor devices |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3066031B2 (en) | 2000-07-17 |
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