JPS6057974A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To enable to thin film thickness of the first layer polycyrstalline silicon film, and to facilitate etching of the two layer film of a semiconductor device by a method wherein the polycrystalline silicon film is formed on a gate oxide film, a natural oxide film, etc. generated thereon are removed, and a metal film or a metal silicide film is formed thereon in the condition not reformed with the films thereof. CONSTITUTION:After field oxide films 2 and a gate oxide film 3 are formed on a silicon substrate 1, a doped polycrystalline silicon film 4' of 1,000Angstrom film thickness if formed, for example. A natural oxide film 7 generated at this time is removed, and at the same time, an MoSi2 film 5 of 2,000Angstrom thickness, for example, is deposited according to the sputtering method in succession without exporsing in an oxidizing atmosphere as not to be reformed with the natual oxide film. A gate pattern is formed by a photo resist, and the two layer film is etched using the gate pattern therof as a mask. After the resist is removed, heat treatment is performed to reduce resistance of the MoSi2 film 5. The polycrystalline silicon film 4' is converted into an N<+> type doped silicon film 4 accroding to activation of phosphorus by this process. Accordingly, the gate electrodes 4, 5 are formed. After then, a source and the drain 6 are formed according to ion implantation.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method for manufacturing a semiconductor device having a gate material having a first layer of polycrystalline silicon and a second layer of metal or metal silicide.

Conventional Structures and Problems Semiconductor devices are becoming increasingly denser, that is, more miniaturized, and various problems have become apparent. One of the problems with conventionally used polycrystalline silicon gates is that the resistance of polycrystalline silicon, which is the gate material, is high, so as gates become smaller, signals are delayed by wiring. This wiring delay has been improved by replacing polycrystalline silicon with a metal or metal silicide, which has a much lower resistance, or a two-layer structure of these and polycrystalline silicon as the gate material.

When replacing polycrystalline silicon with a low resistance material, it is desirable to maintain as much of the features or process compatibility of the polycrystalline silicon gate process as possible. 1000
“High-melting point metals such as MO and W, which have heat resistance of about °C and enable self-line diffusion of sources and drains, and metals with oxidation resistance and hydrofluoric acid, which have the above two features, High melting point metal silicide, which has features such as chemical resistance, is beginning to be used as a material to lower gate wiring resistance.However, high melting point metals and high melting point metal silicide cannot simply be replaced with polycrystalline silicon. Currently, high-melting point metals or high-melting point metal silicides have poor purity as raw materials and contain mobile ions such as Na ions that affect transistor operation, and these materials have a work function that is similar to that of polycrystalline silicon. This is because the transistor characteristics may change due to the difference in characteristics.In order to eliminate these drawbacks, a first layer of polycrystalline silicon and a second layer of high melting point metal or high melting point metal silicide have been adopted. If this two-layer structure is adopted, the presence of polycrystalline silicon in the first layer can prevent the diffusion of mobile ions such as alkali ions contained in the material of the second layer. In addition, since the transistor characteristics are defined by the first layer of polycrystalline silicon, they are no different from those of polycrystalline silicon gates, and processes other than gate formation may be the same as polycrystalline silicon gate processes.

An example of a conventional process for the above two-layer gate structure is shown in FIG. After forming a field oxide film 2 and a gate oxide film 3 on a silicon substrate 1, the N
+ Forming a diffused polycrystalline silicon layer 4 (Fig. 1a)
). The introduction of N-type impurities into polycrystalline silicon may be carried out simultaneously with the deposition of polycrystalline silicon, or N+ diffusion may be carried out after undoped polycrystalline silicon is deposited. This N+ doping into polycrystalline silicon is for stabilizing transistor characteristics. N
+ depositing a refractory metal or a refractory metal silicide 5 on the diffused polycrystalline silicon). For example, about 2
Mo512 having a molecular weight of 000 to 3000 is deposited by sputtering. Next, form a gate pattern with photoresist,
Etching the two-layer film (C). After forming the gate pattern, for example, when the second layer is MOSi2, 100
MoS was heat treated at 0''C for 30 minutes in a nitrogen atmosphere.
Lower the resistance of i2. After that, source/drain 6
Formation by ion implantation (d), formation of an interlayer insulating film, formation of an Al electrode, formation of a passivation film, etc. are the same as in a normal polycrystalline silicon gate process.

As mentioned above, a two-layer structure has superior features compared to the case where a high melting point metal or its silicide is used alone, but there are problems as described below. One of these is the deterioration of the breakdown voltage of the gate oxide film. Currently, the manufacture of semiconductor devices generally requires heat treatment at 900"C or higher, especially when using MoSi2, W as the gate material.
When using a high melting point metal silicide such as S12, heat treatment at about 1000°C is required to lower its resistance. If such heat treatment is applied after forming the gate material, the withstand voltage of the Goo-1 oxide film will deteriorate. It has been found that this breakdown voltage deterioration depends on the film thickness of the first layer polycrystalline silicon.

FIG. 2 shows the dependence of the withstand voltage of a 260 μm square MOS diode (gate oxide film thickness: 350 μm) on the polycrystalline silicon film thickness. From this figure, it can be seen that unless the thickness of the polycrystalline silicon film is about 1600 Å or more, the yield of the gate oxide film breakdown voltage decreases rapidly. Currently, miniaturization of semiconductor devices has become a problem, and not only lateral miniaturization but also vertical miniaturization or planarization is required. When using a two-layer structure as a gate, the second layer of high-melting point metal or high-melting point metal silicide must also have a certain film thickness to lower the resistance as the gate material, so the first layer of polycrystalline silicon It is also desirable to form the layer as thin as possible. However, due to problems with gate oxide film breakdown voltage, it has been
Polycrystalline silicon layers of 0.008 or higher have been used.

When such a thick silicon layer is used, there is a problem of etching the two-layer film. Using photoresist as a mask 2
The layers are dry etched at once, but CF4 and CCl
When a gas such as No. 4 is used, the etching rate of the N+ diffused polycrystalline silicon in the first layer is higher than that of the refractory metal or refractory metal silicide in the second layer. A side etch where the etching of the first layer progresses occurs inside the pattern edge of the layer, as shown in Figure 1 (
As shown in C), an undercut state occurs.

If this undercut occurs, there is a high possibility that it will not be possible to cover the step when forming an interlayer insulating film or AI wiring after etching, which will cause a decrease in the yield of semiconductor devices.

For this reason, there was a need to reduce the thickness of the first layer.

By the way, the present inventors have found that the above-mentioned gate oxide film breakdown voltage depends on the concentration of N-type impurities in polycrystalline silicon during heat treatment. It has been found that deterioration of the gate oxide film breakdown voltage can be prevented by reducing the N-type impurity concentration of the single layer polycrystalline silicon. The inventor believes that this is due to an interfacial reaction between polycrystalline silicon and the metal or metal silicide layer above it, and as shown in Figure 3, the presence of a natural oxide film or contamination on the surface of polycrystalline silicon. It is estimated that this is the cause of the breakdown voltage deterioration.

That is, as shown in FIG. 3(b), in the conventional method, the oxide film 7
Therefore, a local reaction occurs, and the stress generated at that time further accelerates the reaction, resulting in pressure deterioration. According to the method of the present invention, as shown in FIG. 3(a), since there is no oxide film 7, diffusion occurs on average throughout, and the above-mentioned non-uniformity does not occur.

It has also been found that in double-layer film etching, the thickness of polycrystalline silicon can be reduced, making undercuts less likely to occur.

Purpose of the Invention In view of the above problems, the present invention provides a low-resistance gate that does not cause deterioration in gate oxide film breakdown voltage even when the thickness of the first layer polycrystalline silicon film is reduced from 300 to 1500, and is easy to process. An object of the present invention is to provide a semiconductor device having wiring and a method for manufacturing the same.

Structure of the Invention The present invention involves a step of forming a first layer of polycrystalline silicon on a gate insulating film, removing a natural oxide film formed thereon, and forming a second layer of metal or metal silicide thereon. , the gate oxide film breakdown voltage deterioration due to subsequent heat treatment can be prevented, and the first layer polycrystalline silicon can be reduced from 300 to 15
It is possible to achieve a film thickness of 0.000 mm, and to perform good etching of a two-layer film. Note that before and after the step of forming the two-layer film, the polycrystalline silicon is converted to N+ by doping with a thin film by ion implantation, vapor phase diffusion, or solid phase diffusion, followed by thermal diffusion. It also makes it possible to obtain stable transistor characteristics similar to those of crystalline silicon gates.

DESCRIPTION OF THE EMBODIMENTS FIG. 4 shows a method according to an embodiment of the present invention. After forming field oxide film 2 and gate oxide film 3 on silicon substrate 1,
For example, doped polycrystalline silicon 4 with a film thickness of 1000
(a). At this time, the 1° native oxide film 7 is removed, and at the same time, to prevent the natural oxide film from being re-formed, for example, a 2,000-layer MoSi 2 film 5 is removed by a sputtering method without exposing it to an oxidizing atmosphere. Deposit 0)). A gate pattern is formed using photoresist, and the two-layer film is etched using the gate pattern as a mask (c). After removing the resist M o Si
For example, the heat treatment to lower the resistance of the two films 5 is performed at 1000
"'C, 300 film is carried out in a 3-element atmosphere. In this step, the polycrystalline silicon 4' becomes N+ doped silicon 4 by activation of phosphorus (d). In this way, a gate electrode consisting of 4 and 5 is created. Ru.

Thereafter, the source/drain 6 is formed by ion implantation, and the subsequent steps are similar to a normal polycrystalline silicon gate process.

By using this embodiment as described above, it is possible to prevent gate oxide film breakdown voltage from deteriorating even if the first layer polycrystalline silicon film thickness is 1500 Å or less. FIG. 5 shows the dependence of the gate oxide film breakdown voltage on the polycrystalline silicon film thickness when the same MOS diode as shown in FIG. 4 was fabricated using the process of this embodiment. It was found that even if the thickness of the polycrystalline silicon film was reduced to 300, the yield of withstand voltage was almost 100%. When the thickness of the polycrystalline silicon film is less than 300 Å, the transistor characteristics are no longer defined by the polycrystalline silicon, and there is no meaning. In addition, the etching rate of polycrystalline silicon is about half that of bare-doped polycrystalline silicon compared to that of N-diffused silicon;
Since the etching rate was about the same as that of No. 2, it was possible to form a two-layer film pattern that was less likely to cause undercapsulation and faithful to the mask pattern.

In addition, in the example, M o S 12 was used as the material of the second layer.
was used, but metals such as Mo-jW and WS 121
A metal silicide such as T I S 121 T a S 12 may be used, or a multilayer structure combining these may be used.

In addition, after the two-layer film is formed, doping can be carried out using ion implantation method or P
OCl3. A gas phase diffusion method using PH3 or the like or a solid phase diffusion method using silicon phosphide glass or the like may be used. The later doping method is advantageous because the native oxide formed in the first layer is very thin. The doping species is not limited to phosphorus, but may be an N-type impurity such as arsenic or a P-type impurity such as boron.

In the cleaning process, that is, the process of removing the natural oxide film 7 and contaminants, similar results were obtained even when reverse sputtering or H2 annealing (700''C or higher) was used.

FIG. 6 shows vT variation (ΔvT) in a test transistor with a channel length of 1.5 μm and a width of 5 μm. The BT test to test reliability was conducted with 150"C210■.

In the MO812 single layer without a polysilicon layer, there is a variation of more than 100 mV as shown by the solid line 11, which is much larger than the solid line 12 showing the conventional single polysilicon layer. In contrast, in the present invention, the polysilicon layer has 1,500 layers (dotted line 13) and 300 layers (dotted line 1).
In 4), although the latter caused a somewhat large variation in T, both were within the range of variation in the conventional polysilicon single layer 2. As described above, it has been proven that the present invention poses no problems in terms of reliability.

Effect 3 of the Invention As described above, the present invention forms polycrystalline silicon on a gate oxide film, removes the natural oxide film formed on it, and deposits metal or By forming metal silicide, it is possible to prevent the breakdown voltage of the gate oxide film from deteriorating due to heat treatment. As a result, the film thickness of the first layer of polycrystalline silicon was increased to 3.
In particular, it is possible to reduce the thickness from 0.00 to 160.08 mm, which has the effect of contributing to planarization of the semiconductor device without increasing the resistance value of the gate material. In addition, since the polycrystalline silicon can be very thin, undercuts are less likely to occur during etching of the two-layer film, and the effect of facilitating etching processing can be obtained. It was also confirmed that there were no problems with reliability.

[Brief explanation of the drawing]

Figures 1 (,) to (d) are cross-sectional views showing the conventional gate formation process, and Figure 2 is the MO fabricated using the conventional process.
A diagram showing the dependence of the gate oxide film breakdown voltage of an S diode on the polycrystalline silicon film thickness.
Figures (-) to (e) are cross-sectional views showing an example of the gate formation process according to the present invention, and Figure 5 is the dependence of the gate oxide film breakdown voltage on the polycrystalline silicon film thickness of the MOS diode manufactured by the process according to the present invention. FIG. 6 is a diagram showing an example of improvement in reliability, and FIG. 6 is a diagram showing the results of a reliability test. 1...Silicon substrate, 3...Gate oxidation, 4...Par°N+polycrystalline silicon layer, 4'...
- Undoped polycrystalline silicon layer, 6...Metal or metal silicide layer, 7... Natural oxide film or contamination. Name of agent: Patent attorney Toshio Nakao and one other person who is deaf
N ＼ To measurement ＼ -S Tomoe N ＼ N 3 ma c3 -ko () ζノ ++J ++J r1 P+S Figure 5 Polycrystalline wrinkled film thickness (Figure 6 □ Time C-□r)

Claims (3)

[Claims] (1) A step of forming a gate insulating film on a semiconductor substrate, a step of forming polycrystalline silicon as a first layer on the insulating film, and removing a natural oxide film and a contaminant layer formed on the surface of the first layer. A semiconductor device characterized by comprising a cleaning step and a step of forming a gate layer in which a single layer or multiple layers of metal or metal silicide are laminated as a second layer without exposing the cleaning step layer to an oxidizing atmosphere. manufacturing method. (2) The method for manufacturing a semiconductor device according to claim 1, wherein the cleaning step is performed using a scale using a reverse sputtering method. (3) The method for manufacturing a semiconductor device according to claim 1, wherein hydrogen annealing is used as the cleaning step. A method for manufacturing a semiconductor device.