JP3022629B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a composite LSI in which a bipolar transistor and a MOS transistor are formed on the same semiconductor substrate, and more particularly to reducing the number of manufacturing steps and improving the electrical characteristics and reliability of the transistor. And a method of manufacturing the same.

[0002]

2. Description of the Related Art In recent years, there have been many proposals regarding a semiconductor device having a Bi-CMOS structure in which a bipolar transistor and a complementary MOS transistor (CMOS transistor) are integrated, and particularly, the electrical characteristics and reliability of both transistors are deteriorated. An important issue is to reduce the number of processes and reduce costs.

FIG. 14 shows an example of a conventionally proposed semiconductor device having a Bi-CMOS structure. The method for manufacturing the semiconductor device shown in FIG. 14 is as follows. First, an N ⁺ buried layer 2, a P ⁺ buried layer 3, an N-type well layer 4, a P-type well layer 5,
An N ⁺ collector wall diffusion layer 7 and a P-type active base diffusion layer 8 are formed in the bipolar region of the P-type silicon substrate 1 on which the separation SiO ₂ film 6 is formed, and then an SiO ₂ film 9 is formed.
A gate oxide film is formed in a MOS region.

Next, after etching the SiO ₂ film 9 in the bipolar region to form an emitter window, a polycrystalline silicon film 11 (PolySi film) is deposited on the entire surface. After that, arsenic is ion-implanted and an N ⁺ emitter diffusion layer 13 is formed by heat treatment. Next, the PolySi film 11 is etched to
Forming an emitter electrode of the gate electrode and the bipolar transistor of the OS transistor, further sidewall SiO ₂ film
Form 12.

Next, a P ⁺ diffusion layer 14 as a source / drain of a P-channel MOS transistor, and an N ⁺ as a source / drain of an N-channel MOS transistor
After forming the diffusion layer 15, an interlayer insulating film 16 is formed. After that, an emitter contact window, a base contact window, a collector contact window, a source / drain contact window of a P-channel type MOS transistor, and a source / drain contact window of an N-channel type MOS transistor are formed in the interlayer insulating film 16 and then a metal is formed. wiring
17 is formed to obtain a semiconductor device having a structure as shown in FIG.

[0006]

However, in the semiconductor device having the structure as shown in FIG.
There are the following problems.

(1) After forming the gate oxide film 10 and before depositing the PolySi film 11 serving as a gate electrode, a step of forming an emitter window of the bipolar transistor is included.
Contamination and damage of the gate oxide film 10 of the S transistor occur, causing problems such as a breakdown voltage failure of the gate oxide film 10.

(2) After the emitter window is formed, Pol
Before the ySi film 11 is deposited, it is necessary to perform dip etching to remove a native oxide film on the emitter region.
However, in a semiconductor device having a structure such as 13 and a method of manufacturing the same, since the gate oxide film 10 is exposed on the surface during dip etching, when the gate oxide film 10 is formed as thin as about 10 nm, the gate is formed by dip etching. As the thickness of the oxide film decreases, a change in characteristics or poor characteristics due to pinholes becomes a problem.

Regarding the above problems, after a gate oxide film and a PolySi film serving as a gate electrode are successively formed, a MOS region is covered with a deposited film, an emitter window is formed, and the emitter electrode is formed after dip etching. Naru Pol
The problem can be solved by forming a ySi film, but this manufacturing method has a problem that the number of steps increases and the cost increases.

(3) Other cases where the emitter is formed by directly implanting arsenic or the like after the emitter window is formed,
When the amount of hydrogen atoms in the i film is large, or when the bonding state of the insulating film such as SiO ₂ is unstable, the insulating film such as SiO ₂ forming the emitter window and the emitter electrode such as the PolySi film are subjected to heat treatment. A reaction occurs near the interface due to the influence of the hydrogen atom, which causes a change in the composition, diffusion of oxygen atoms from the outside and generation of voids with the assist of hydrogen atoms, and the like, which causes a problem that electrical characteristics may be affected.

SUMMARY OF THE INVENTION In view of the above problems, the present invention has been made to solve the above problems and to provide a semiconductor device having a reduced number of steps, high speed characteristics and high reliability, and a method of manufacturing the same. It is the purpose.

[0012]

In order to achieve the above object, a semiconductor device according to the present invention comprises a MOS transistor on a semiconductor substrate.
Insulation by nitridation formed on gate oxide film of transistor
A first conductive film formed on the insulating film formed by nitriding;
Sandwiched between the conductive film and the second conductive film formed thereon
A naturally formed insulating film, the insulating film formed by nitriding and the
Impurity introduced into the second conductive film by forming a naturally formed insulating film
Barrier preventing penetration of said gate oxide film
It is what was constituted.

[0013] The method of manufacturing a semiconductor device according to the present invention comprises the steps of:
Step of forming gate oxide film in MOS region on substrate
Forming an insulating film by nitriding on the gate oxide film
Forming a first conductive film on the insulating film by nitriding
And preventing diffusion of impurities on the first conductive film.
Second conductive film with a naturally formed insulating film interposed therebetween
Forming the first and second conductive lines and the conductive lines.
Etching the naturally formed insulating film sandwiched between the
A step of forming a conductive film pattern to be a gate electrode.
It is a thing.

Further, the method of manufacturing a semiconductor device comprises the steps of forming a first insulating film having a desired thickness in a bipolar transistor region on a semiconductor substrate, and forming a gate insulating film in a MOS region on the semiconductor substrate. Forming a second insulating film; forming an insulating film by nitriding on the first insulating film and the second insulating film, respectively; and forming the first insulating film in an emitter region of the bipolar transistor. forming an emitter window by etching the insulating film by nitriding thereon, to remove the natural formation film and the spontaneous formation film formed on the surface washing on the insulating film by nitridation of the semiconductor substrate of the emitter window Forming a conductive film on the semiconductor substrate of the emitter window and on the insulating film by nitridation after removing the naturally formed film; and etching the conductive film to form an upper portion of the emitter window. And the conductive film pattern made larger emitter electrode than the emitter window, is obtained with a step of forming a conductive film pattern serving as a gate electrode in the MOS region.

Further, according to the manufacturing method of the present invention, a first insulating film having a desired thickness is formed in a bipolar transistor region on a semiconductor substrate, and a gate region is formed in a MOS region on the semiconductor substrate. Forming a second insulating film; forming an insulating film by nitriding on the first insulating film and the second insulating film, respectively; and forming the first insulating film in an emitter region of the bipolar transistor. forming an emitter window by etching the insulating film by nitriding thereon, to remove the natural formation film and the spontaneous formation film formed on the surface washing on the insulating film by nitridation of the semiconductor substrate of the emitter window a step, after removing the spontaneous formation layer, forming a first conductive film in the emitter window of the semiconductor substrate and the insulating film by nitriding, natural formation insulating film on the first conductive film Across Forming a second conductive film, and the first and second conductive film and the larger the emitter electrode than the emitter window the natural formation insulating film sandwiched therebetween a conductive film to the emitter window upper etching The method includes a step of forming a conductor film pattern and a conductor film pattern to be a gate electrode in the MOS region.

[0016]

The present invention operates as follows by the above-described configuration. (1) By forming a nitride insulating film continuously after the formation of the gate oxide film, the gate oxide film is not exposed to the surface during dip etching for removing the natural oxide film before the deposition of the PolySi film after the formation of the emitter window. The generation of pinholes in the oxide film can be prevented, and the gate oxide film can be made thinner in response to miniaturization of devices.

(2) By using a gate insulating film in which a nitride insulating film is formed on a gate oxide film, the nitride insulating film exhibits an effect of preventing impurities such as boron having a large diffusion coefficient from penetrating the gate oxide film. Thus, the reliability of the transistor characteristics can be improved. Further, a PolySi film serving as a gate electrode is divided into a plurality of pieces so as to sandwich a natural oxide film, so that a PolySi film / PolySi film is formed.
As in the case of the nitride insulating film, the natural oxide film at the interface of the Si film has an effect of preventing impurities from penetrating through the gate oxide film, and the reliability of transistor characteristics can be further improved.

(3) With the structure in which the nitride insulating film is formed continuously after the formation of the gate oxide film, the breakdown voltage of the gate oxide film due to contamination and damage of the gate oxide film in the step of forming the emitter window of the bipolar transistor PolyS as an emitter electrode without problems such as defects
i film and a PolySi film as a gate electrode can be simultaneously deposited.
The number of steps can be reduced without deteriorating the characteristics of both S transistors.

(4) By sandwiching a nitride insulating film between a deposited film such as SiO ₂ forming an emitter window of a bipolar transistor and a PolySi film serving as an emitter electrode, a reaction between both films is prevented. In addition, it is possible to prevent a change in composition, generation of voids and defects, and to stably improve electric characteristics.

[0020]

BRIEF DESCRIPTION OF THE DRAWINGS FIG.
Will be described. 1 to 8 show a first embodiment of the present invention.
Process of each manufacturing process of a Bi-CMOS semiconductor device
FIG. First, in FIG.⁺Buried layer 2, P
⁺On the P-type silicon substrate 1 on which the buried layer 3 is formed,
After forming an epitaxial layer having a thickness,
And a P-type well layer 5 are formed. Then, LO
Separated SiO by COS method_TwoAfter forming the film 6, LOC
Si used for OS method_ThreeN _FourRemove the membrane and bipolar tiger
N of transistor⁺Collector wall diffusion layer 7 and P-type active layer
The source diffusion layer 8 is formed.

Next, in FIG. 2, SiO ₂ film, for example 100 nm is deposited, a resist pattern 29 is removed the SiO ₂ film of the MOS region as a mask, the bipolar region Si
An O ₂ film 30 is formed. Furthermore, the same resist pattern 29
Is used as a mask to remove the underlying SiO ₂ film 27 of LOCOS of about 30 nm in the MOS region to expose the silicon substrate surface in the MOS region. At this time, a bipolar region SiO ₂ film 30 of about 100 nm and a base Si of LOCOS of about 30 nm are formed.
The O ₂ film 27 plays a role of electrically insulating the emitter region and the base region of the bipolar transistor from the emitter electrode. Here, for example, the bipolar region Si
Instead of forming the O ₂ film 30, the LOCOS base SiO ₂ film 27 having a thickness of about 30 nm alone can also serve to electrically insulate the emitter region and the base region from the emitter electrode.

Next, referring to FIG.
After the removal, a gate oxide film 31 of about 10 nm is formed. At this time, the bipolar region is a bipolar region SiO
It is covered with the _two films 30, and the silicon substrate surface is not directly oxidized. Further, for example, the bipolar region SiO ₂ film 30 is formed by CVD (Chemical Vapor Deposition).
In the case where the gate oxide is formed at a deposition temperature of about 800 ° C. by the T.I. method at 850 ° C. to 900 ° C., the CVD film can be densified. Next, the surfaces of the gate oxide film 31 and the bipolar region SiO ₂ film 30 are nitrided by, for example, lamp annealing at a temperature of 900 ° C. to 1100 ° C. for about 30 seconds in an ammonia gas atmosphere, thereby nitriding to a thickness of 2 to 5 nm. An insulating film 32 is formed. Here, particularly when the composition of the bipolar region SiO ₂ film 30 is silicon-rich or when many hydrogen atoms are present in the PolySi film serving as the emitter electrode, an insulating film such as SiO ₂ and a PolySi film serving as the emitter electrode are formed. The electrical characteristics may be degraded due to a change in composition due to the reaction between the electrodes and the generation of voids and defects. However, the densification of the bipolar region SiO ₂ film 30 and the bipolar region
The structure of the O ₂ film 30 is stabilized by nitriding the surface of the O ₂ film 30 to form a nitride insulating film 32. Note that, as a method for forming the nitride insulating film 32, a CVD method may be used instead.

Next, referring to FIG.
With the nitride insulating film 32 and the bipolar region SiO ₂
The emitter window is formed by etching the film 30 and the underlying SiO ₂ film 27 of LOCOS. Thereafter, the resist pattern 33 is removed. At this time, if the gate oxide film is exposed, contamination and damage occur, and problems such as a breakdown voltage failure of the gate oxide film occur. Since the nitride insulating film 32 is formed by nitriding, the influence on the gate oxide film when removing the resist pattern 33 can be suppressed.

Next, in FIG. 5, after dip etching for removing a naturally formed film of the emitter window, a PolySi film 34 serving as an emitter electrode and a gate electrode is formed, for example, by 33.
0 nm is formed. Here, since the nitride insulating film is formed continuously after the formation of the gate oxide film, the gate oxide film is not exposed to the surface at the time of dip etching. The reduction can be prevented, and the gate oxide film can be made thinner corresponding to the miniaturization of devices. Furthermore, the improvement in the dip-etch resistance of the gate insulating film allows the poly-Si film serving as a gate electrode and the poly-Si film serving as an emitter electrode requiring a dip etch immediately before deposition to stabilize the electrical characteristics of the bipolar transistor. Simultaneous formation becomes possible, and simplification of the process can be realized as compared with a manufacturing method in which simultaneous formation was conventionally difficult.

Next, referring to FIG.
Are used as masks to form emitter electrodes and MOS gate electrodes.
The pattern of the PolySi film 34 is formed. Next, the cash register
After removing the strike pattern 35, the emitter electrode and the gate
Impurities such as phosphorus in the PolySi film serving as an electrode
The material is ion-implanted, and a poly-Si film is formed by a subsequent heat treatment.
Of the resistance is reduced. Here, the emitter electrode and N channel
N-channel MOS gate electrode and P-channel MOS gate
To be introduced into the PolySi film that will be the
The type of the pure product may be changed as needed. For example, M
Impurities introduced into PolySi film to be OS gate electrode
A material with a large diffusion coefficient, such as boron, was used
In this case, as in the conventional case, SiO 2 is used as the gate insulating film. _TwoMembrane only
In the structure, boron penetrates through the gate insulating film
Degradation of transistor characteristics sometimes occurred, but gate
Insulating nitride film on oxide film prevents boron diffusion
Improves the resistance of the gate insulating film to degradation due to impurity diffusion
Let me.

Next, in FIG. 7, after depositing a SiO ₂ film over the entire surface of, for example, 250 nm, a 250 nm SiO ₂ film, a ₂ to 5 nm nitride insulating film 32 and a 10 nm Removing the gate oxide film 31;
The source / drain regions of the MOS transistor are exposed. Here, the order of the bipolar region SiO ₂ film 30 and 30nm of nitride insulating film 32 with about 100 nm of 2nm~5nm under the SiO ₂ film of 250 nm in front of the bipolar transistor region to perform anisotropic dry etching Although each insulating film of the LOCOS base SiO ₂ film 27 exists,
There is no particular problem even if the insulating film remains to some extent. By this step, PolyS which becomes an emitter electrode, an N-channel type MOS gate electrode and a P-channel type MOS gate electrode is formed.
On the side surface of the i film, a side wall SiO ₂ film 37 is formed with a width of 220 nm.

Next, in FIG. 8, N ^{+ is formed} by thermal diffusion of impurities from the PolySi film serving as an emitter electrode.
An emitter diffusion layer 36 is formed in the P-type active base diffusion layer 8. Next, boron is ion-implanted to form a P-channel type MO.
A source / drain P ⁺ diffusion layer 38 of the S transistor is formed, and arsenic is ion-implanted to form a source / drain N ⁺ diffusion layer 39 of the N-channel MOS transistor. Further, after the interlayer insulating film 40 is deposited on the entire surface, for example, 900
The surface is flattened by a heat treatment at 30 ° C. for 30 minutes. afterwards,
By forming each metal wiring 41, a semiconductor device having a structure as shown in FIG. 8 can be obtained.

FIGS. 9 to 13 show process cross-sectional views of respective manufacturing steps of a Bi-CMOS semiconductor device according to the second embodiment of the present invention. The first part of the manufacturing steps is shown in FIG. 1 of the first embodiment. 4 to FIG.

In the process of FIG. 4 shown in the first embodiment,
After forming the emitter window, FIG.
After the first dip etch to remove the naturally formed film
Si thin film which becomes part of the emitter electrode and gate electrode
51 is formed to have a thickness of, for example, 30 nm. Next, in FIG.
Arsenic, for example, at 70 keV, 2 × 10¹⁵/cm ^Two
Ion implantation through the Si thin film 51 under the conditions of⁺Emi
A diffusion layer 52 is formed in the P-type active base diffusion layer 8. Further
Next, a second dip edge for removing the naturally formed film
Which becomes part of the emitter electrode and the gate electrode after
The lySi thin film 53 is formed, for example, to a thickness of 300 nm. here,
A natural oxide film is formed between the Si thin film 51 and the PolySi thin film 53.
There is about 1 nm. Furthermore, the Si thin film 51 and Pol
Put ySi thin film 53 on emitter electrode and gate electrode
A resist pattern 54 for lining is formed.

As described above, by performing ion implantation through the Si thin film 51 to form the N ⁺ emitter diffusion layer 52, the influence of the natural oxide film existing at the interface between the Si substrate and the Si film by the CVD method such as the PolySi film. The formation of the N ⁺ emitter diffusion layer 52 is possible without receiving the light. As a result, it has become possible to manufacture a semiconductor device by a lower temperature process. Furthermore, since the nitride insulating film is formed continuously after the gate oxide film is formed, the gate oxide film is not exposed to the surface during the first dip etching, so that the dip etching causes pinholes in the gate oxide film and the gate oxide film thickness. Thus, the gate oxide film can be made thinner in response to the miniaturization of devices. Furthermore, the improvement in the dip-etch resistance of the gate insulating film allows the poly-Si film serving as a gate electrode and the poly-Si film serving as an emitter electrode requiring a dip etch immediately before deposition to stabilize the electrical characteristics of the bipolar transistor. Simultaneous formation becomes possible, and simplification of the process can be realized as compared with a manufacturing method in which simultaneous formation was conventionally difficult. Next, resist pattern
Using the mask 54 as a mask, a pattern of a PolySi film 53 to be an emitter electrode and a MOS gate electrode is formed.

Next, the resist pattern 54 is removed, and
In the PolySi film to be the emitter electrode and the gate electrode
For example, ion implantation of impurities such as phosphorus and subsequent heat treatment
This lowers the resistance of the PolySi film. here,
Emitter electrode, N-channel type MOS gate electrode and
PolySi film to be a P-channel MOS gate electrode
The type of impurity to be introduced into each is changed as necessary.
You may get. For example, Poly which becomes a MOS gate electrode
A diffusion agent such as boron as an impurity to be introduced into the Si film.
If a large number is used, the gate insulation will be
SiO as film _TwoIn a film-only structure, boron is
Through the gate insulating film, causing deterioration of transistor characteristics
However, the nitride insulating film on the gate oxide film and S
Spontaneous oxidation existing between i thin film 51 and PolySi thin film 53
The film blocks the diffusion of boron, preventing the diffusion of impurities.
Of the gate insulating film is improved.

Next, the SiO_TwoFor example, over the entire 250 nm film
And then anisotropic dry etching
0 nm SiO_TwoFilm and a 2-5 nm nitride insulating film 32
The gate oxide film 31 of about 10 nm is removed, and the MOS transistor is removed.
The source / drain region of the star is exposed. Here, different
Bipolar transistor before isotropic dry etching
250 nm SiO_Two2nm-5 below the membrane
nm nitride insulating film 32 and a bipolar region S of about 100 nm.
iO_TwoFilm 30 and LOCOS base SiO of about 30 nm_Twofilm
Although each insulating film of 27 remains, the insulating film of about 100 nm
There is no particular problem if present. This process allows the emitter
Pole and N-channel MOS gate electrode and P-channel
On the side of the PolySi film that will be the
Wall SiO _TwoA film 55 is formed with a width of 220 nm.

Next, boron is ion-implanted to form a source / drain P ⁺ diffusion layer of a P-channel type MOS transistor.
56 is formed, and arsenic is ion-implanted to form an N-channel MO.
The source / drain N ⁺ diffusion layer 57 of the S transistor is formed. Further, after the interlayer insulating film 40 is deposited on the entire surface, the surface is flattened by, for example, heat treatment at 900 ° C. for 30 minutes.
Thereafter, by forming each metal wiring 41, a semiconductor device having a structure as shown in FIG. 11 is obtained.

FIG. 12 is an enlarged view of the emitter electrode portion of the bipolar transistor according to the second embodiment, and FIG. 13 is an enlarged view of the gate electrode portion of the MOS transistor according to the second embodiment. .

In the first embodiment, the PolySi film 34 serving as an emitter electrode and a gate electrode is used. However, the present invention is not particularly limited to a PolySi film as long as it is another conductive film. In the second embodiment, the Si thin film 51 is used.
It may be an amorphous Si film or a PolySi film.

In the second embodiment, the Si thin film 51, which is to be a part of the emitter electrode and the gate electrode, is
Arsenic is ion-implanted into the emitter region through a Si thin film 51 to form an N ⁺ emitter diffusion layer 52. Further, after a second dip etch for removing the naturally formed film, the emitter electrode and the gate electrode are removed. PolyS to be a part
The i-film 53 is formed, for example, to a thickness of 300 nm.
It is preferable to use a conductor film such as a metal silicon film (tungsten silicide or molybdenum silicide) instead of 53 because the resistance of the electrode can be reduced.

[0037]

According to the present invention, the following effects can be obtained. (1) After the emitter window is formed, the gate oxide film is not exposed to the surface at the time of dip etching for removing the natural oxide film before depositing the PolySi film, so that the occurrence of pinholes in the gate oxide film can be prevented and further miniaturization of the device can be achieved. The corresponding gate oxide film can be made thinner.

(2) By using a gate insulating film in which a nitride insulating film is formed on a gate oxide film, the nitride insulating film exhibits an effect of preventing impurities such as boron having a large diffusion coefficient from penetrating the gate oxide film. As a result, the reliability of the transistor characteristics can be improved. Further, if a poly-Si film serving as a gate electrode is divided into a plurality of parts so as to sandwich a natural oxide film, the poly-Si film / PolySi film can be formed.
As in the case of the nitride insulating film, the natural oxide film at the film interface has an effect of preventing impurities from penetrating through the gate oxide film, and the reliability of transistor characteristics can be further improved.

(3) With the structure in which the nitride insulating film is formed continuously after the formation of the gate oxide film, the withstand voltage of the gate oxide film due to contamination or damage of the gate oxide film in the step of forming the emitter window of the bipolar transistor PolyS as an emitter electrode without problems such as defects
i film and a PolySi film as a gate electrode can be simultaneously deposited.
The number of steps could be reduced without deteriorating the characteristics of both S transistors.

(4) By sandwiching a nitride insulating thin film between an insulating film such as SiO ₂ forming an emitter window of a bipolar transistor and a PolySi film serving as an emitter electrode, a reaction between both films is prevented. In addition, it was possible to prevent a change in composition, generation of voids and defects, and to stably improve electric characteristics.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a first manufacturing process according to a first embodiment of the present invention.

FIG. 2 is a sectional view of a second manufacturing step in the first embodiment of the present invention.

FIG. 3 is a sectional view showing a third manufacturing step in the first embodiment of the present invention.

FIG. 4 is a sectional view showing a fourth manufacturing step in the first embodiment of the present invention.

FIG. 5 is a sectional view showing a fifth manufacturing step in the first embodiment of the present invention.

FIG. 6 is a sectional view showing a sixth manufacturing step in the first embodiment of the present invention.

FIG. 7 is a sectional view showing a seventh manufacturing step in the first embodiment of the present invention.

FIG. 8 is a sectional view of a final structure according to the first embodiment of the present invention.

FIG. 9 is a cross-sectional view showing a first manufacturing step in the second embodiment of the present invention.

FIG. 10 is a sectional view of a second manufacturing step in the second embodiment of the present invention.

FIG. 11 is a sectional view of a final structure according to the second embodiment of the present invention.

FIG. 12 is an enlarged view of a bipolar transistor of a final structure sectional view in a second example of the present invention.

FIG. 13 is an enlarged view of a MOS transistor having a final structure sectional view according to the second embodiment of the present invention.

FIG. 14 is a sectional view of a conventional structure.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 P-type silicon substrate 2 N ⁺ buried layer 3 P ⁺ buried layer 4 N-type well layer 5 P-type well layer 6 Separation SiO ₂ film 7 N ⁺ collector wall diffusion layer 8 P-type active base diffusion layer 27 LOCOS base SiO ₂ film 29 resist pattern (for patterning bipolar area SiO ₂ film) 30 bipolar area SiO ₂ film 31 gate oxide film 32 nitride film 33 resist pattern (for patterning bipolar emitter window) 34 PolySi film 35 resist pattern (for bipolar emitter electrode) , M
(For OS gate electrode patterning) 36 N ⁺ emitter diffusion layer 37 Side wall SiO ₂ film 38 P ⁺ diffusion layer (source / drain) 39 N ⁺ diffusion layer (source / drain) 40 interlayer insulating film 41 metal wiring 51 Si thin film 52 N ⁺ Emitter diffusion layer 53 PolySi film 54 resist pattern (bipolar emitter electrode, M
OS gate electrode patterning) 55 Side wall SiO ₂ film 56 P ⁺ diffusion layer (source / drain) 57 N ⁺ diffusion layer (source / drain) 58 Interlayer insulating film 59 Metal wiring

──────────────────────────────────────────────────続 き Continuing on the front page (51) Int.Cl. ⁷ Identification code FI H01L 29/43 29/78 (72) Inventor Hiroshi Shimomura 1006 Ojidoma, Kadoma City, Osaka Matsushita Electric Industrial Co., Ltd. (56) References JP-A-3-20073 (JP, A) JP-A 1-28667 (JP, A) JP-A-2-83934 (JP, A) JP-A-61-91961 (JP, A) (58) Survey Field (Int.Cl. ⁷ , DB name) H01L 21/8249 H01L 21/283 H01L 21/336 H01L 21/768 H01L 27/06 H01L 29/43 H01L 29/78

Claims (4)

(57) [Claims] 1. A gate oxide film in a MOS region on a semiconductor substrate.
An insulating film formed by nitriding formed thereon; a first conductive film formed on the insulating film formed by nitriding; and a naturally formed insulating film sandwiched between a second conductive film formed thereon. semiconductor device, and wherein the impurity of the spontaneous formation insulating film and the insulating film is introduced into the second conductive film by nitriding is constructed barrier that prevents penetrating the gate oxide film. 2. The method according to claim 1 , wherein a gate oxide is applied to a MOS region on the semiconductor substrate.
Forming a film and nitriding on the gate oxide film
Forming an insulating film; and forming an insulating film on the insulating film by nitriding.
Forming a first conductive film; and forming a conductive film on the first conductive film.
A naturally formed insulating film that can prevent diffusion of pure substances
Forming a second conductive film by using the first and second conductive films.
A conductive film and the naturally formed insulating film sandwiched between the conductive films;
The conductor film pattern that becomes the gate electrode by etching
Forming a semiconductor device.
Production method. 3. A step of forming a first insulating film having a desired thickness in a bipolar transistor region on a semiconductor substrate, and forming a second gate film in a MOS region on the semiconductor substrate.
Forming an insulating film by nitriding on the first insulating film and the second insulating film, respectively; and forming the first insulating film on the first and second insulating films in the emitter region of the bipolar transistor.
Forming an emitter window by etching the insulating film and the nitrided insulating film thereon, and forming a naturally formed film on the semiconductor film of the emitter window and cleaning the surface of the insulating film by nitriding Removing the spontaneously formed film, forming a conductive film on the semiconductor substrate of the emitter window and on the insulating film formed by nitriding, etching the conductive film, and removing the conductive film on the emitter window. A conductor film pattern to be an emitter electrode larger than the emitter window,
A method for manufacturing a semiconductor device, comprising a step of forming a conductive film pattern to be a gate electrode in a MOS region. 4. A step of forming a first insulating film having a desired thickness in a bipolar transistor region on a semiconductor substrate, and forming a second gate film in a MOS region on the semiconductor substrate.
Forming an insulating film by nitriding on the first insulating film and the second insulating film; and forming the first insulating film on an emitter region of a bipolar transistor and the first insulating film on the first insulating film. Etching the insulating film by nitriding to form an emitter window; removing the naturally formed film on the semiconductor substrate of the emitter window and the naturally formed film formed by surface cleaning on the insulating film by nitriding; Forming a first conductive film on the semiconductor substrate of the emitter window and on the insulating film formed by nitriding after removing the naturally formed film; and forming a second conductive film on the first conductive film with the naturally formed insulating film interposed therebetween. Forming a conductive film, and etching the first and second conductive films and a naturally-formed insulating film sandwiched between the conductive films to form an emitter electrode above the emitter window to be an emitter electrode larger than the emitter window Membrane pattern The method of manufacturing a semiconductor device characterized by comprising a step of forming a conductive film pattern serving as a gate electrode in the MOS region.