JPH11135780A - Mis type semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress diffusion of an impurity from polycrystalline silicon to a silicide and constitute a stable gate electrode, by a method wherein a silicon layer resides between a first silicon layer and a second silicon layer. SOLUTION: A gate oxide film 202 is formed by oxidizing initially and a first polycrystal silicon layer 215 containing, for example, phosphorous ions as a P type impurity are deposited thereon. Next, a second polycrystalline silicon layer 215 containing, for example, phosphorus ions as a P type impurity is deposited. Next, a tungsten silicide layer 205 is vapor-deposited and a silicon oxide layer 206 is deposited. Next, a first polycrystalline silicon layer 204, the tungsten silicide layer 205 and the silicon oxide layer 206 are etched to form a gate electrode layer 203. Further, a silicon oxide layer 207 is formed surrounding the gate electrode layer 203. Following that, after boron ions 212 are implanted and an interlayer silicon oxide film 213 is deposited, an aluminum layer 214 is vapor-deposited.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a MIS type semiconductor device and a method for manufacturing the same. In particular, the present invention relates to a semiconductor device having an improved gate electrode structure.

[0002]

2. Description of the Related Art Conventionally, a gate electrode having a polycide structure on a gate oxide film is known as a structure of a gate electrode and a wiring of a MIS type semiconductor device.

FIG. 4 schematically shows a method and a structure of a conventional MIS type semiconductor device after the gate oxidation.

A gate oxide film 102 is formed on an N-type silicon substrate 101 having a specific resistance of 10 to 20 Ωcm at a temperature of 1000 ° C. O _2.
After being formed to 20 nm in the atmosphere, the gate electrode layer 10 is formed.
For example, the first polycrystalline silicon layer 104 containing phosphorus ions of 10 ² cm ⁻³ is formed by CVD (Chemical
Vapor Deposition) method
After depositing a thickness of 00 nm, the tungsten silicide layer 10
5 is deposited to a thickness of 200 nm by a sputtering method, and a silicon oxide layer 106 is deposited to a thickness of 200 nm by a CVD method.

Then, desired patterning is performed by photolithography using a positive resist, and the first polysilicon layer 104, the tungsten silicide layer 105, and the silicon oxide layer 1 are formed by dry etching.
06 is etched to form the gate electrode layer 103. Dry etching uses CF ₄ gas, pressure 0.8
This is performed for 60 seconds at a power of 150 W in an mTorr atmosphere.

Further, oxidation is performed in a steam atmosphere at 900 ° C. for 30 minutes to form a silicon oxide layer 107 of about 100 nm around the gate electrode layer 103.

After that, the source and drain portions 111 of the MOS transistor are opened by photolithography using a positive resist, and then the ionized arsenic 11 is removed.
2 ions are implanted at 9 × 10 ¹⁵ cm ⁻² .

After that, an interlayer silicon oxide film 113 is deposited by, for example, a CVD method, and then a junction contact hole is opened by photolithography and dry etching, and a wiring metal, for example, an aluminum layer 114 is formed by a sputtering method. Then, the wiring metal is patterned by photolithography and dry etching.

The outline of the conventional method of manufacturing a MIS type semiconductor device has been described above.

[0010]

In the conventional semiconductor technology, when a so-called polycide electrode structure comprising a two-layer structure of polycrystalline silicon, a compound of a refractory metal and silicon is used as a gate electrode layer, the polycrystalline silicon and Since the knitting coefficient between silicides is about three times as large as that of silicide, impurities in the polycrystalline silicon are taken into silicide more in the heat step after the formation of the compound of the high melting point metal and silicon. As a result, the volume of the polycrystalline silicon is shrunk, and the thickness of the polycrystalline silicon is minimally reduced. In the patterning of the gate electrode layer by dry etching, etching remains in a thick portion, and the yield of the semiconductor device is reduced. Was causing it. In addition, in the gate electrode layer remaining in patterning, an abnormal appearance due to uneven film thickness is caused, and in a pattern defect inspection process performed as a defect inspection during a process, it appears as tens of thousands of defects, and the gate electrode is formed. It was an injury when performing the essential defect inspection later.

Therefore, the present invention is to solve such a problem, and an object of the present invention is to provide a technique for forming a stable gate electrode.

[0012]

[Means for Solving the Problems]

(Means 1) A conductor-insulating film-semiconductor substrate is mainly a main component of a semiconductor element, and a material constituted as the semiconductor is formed by removing impurity ions containing silicon as a main component at least in order from the insulating film. In a MIS semiconductor device composed of a first silicon layer containing silicon and a second silicon layer containing silicon as a main component and containing a high melting point metal, the first silicon layer and the second silicon layer Is characterized in that a silicon layer is interposed.

(Means 2) A conductor-insulating film-semiconductor substrate is mainly a main component of the semiconductor element, and the material constituted as the conductor is silicon as a main component at least in order from the insulating film. In a MIS semiconductor device comprising a first silicon layer containing impurity ions and a second silicon layer containing silicon as a main component and containing silicon as a high melting point metal, the first silicon layer and the second silicon layer The semiconductor device is characterized in that a silicon layer having a group III or group V impurity element of 10 ²⁰ cm ⁻³ or less is interposed between the two silicon layers.

(Means 3) In the MIS type semiconductor device according to the first aspect, the silicon layer between the first silicon layer and the second silicon layer is at least 20 nm or more.

(Means 4) In a method of manufacturing a MIS type semiconductor device, a step of forming a silicon oxide film on at least a silicon substrate and a first polycrystalline silicon layer containing a group III or V group impurity element Alternatively, a step of depositing a first amorphous silicon layer, a step of depositing a second polycrystalline silicon layer or a second amorphous silicon layer containing a group III or group V impurity element, and a step of depositing silicon containing a high melting point metal And a step of depositing silicon oxide or silicon nitride as an insulating layer on the third silicon layer.

(Means 5) In the method of manufacturing a MIS type semiconductor device, a step of forming a silicon oxide film on at least a silicon substrate, and a first polycrystalline silicon layer containing a group III or V group impurity element Alternatively, a step of depositing a first amorphous silicon layer, a step of depositing a second polycrystalline silicon layer or a second amorphous silicon layer, and a step of depositing a third silicon layer mainly containing silicon containing a refractory metal. A deposition step and a step of depositing silicon oxide or silicon nitride as an insulating layer on the third silicon layer.

(Means 6) In the method of manufacturing a MIS type semiconductor device, a step of forming a silicon oxide film on at least a silicon substrate and a first polycrystalline silicon layer containing a group III or V group impurity element Alternatively, a step of depositing a first amorphous silicon layer, a step of performing a heat treatment immediately after the formation of the first silicon layer, a step of depositing a third silicon layer containing silicon containing a high melting point metal as a main component, Silicon oxide or an insulating layer on the third silicon layer,
A step of depositing silicon nitride.

(7) In the MIS type semiconductor device according to the above (6), the temperature of the heat treatment is at least 870.
It is characterized by a temperature of at least ° C.

[0019]

In a gate electrode and a wiring structure having a polycide structure, a polycrystalline silicon layer containing a low-concentration impurity element or no impurity element is contained between a polycrystalline silicon layer and a silicon layer containing a refractory metal. By interposing a polycrystalline or amorphous silicon layer, diffusion of impurities from polycrystalline silicon to silicide can be suppressed.

[0020]

BEST MODE FOR CARRYING OUT THE INVENTION

(Embodiment 1) FIG. 1 shows an embodiment of a method of manufacturing a MIS type semiconductor device according to the present invention. In particular, a case of a P-type MOS transistor will be described step by step.

After an N-type well diffusion layer 210 is formed on a P-type silicon substrate 201, an active region 209 of the element is formed.
Then, an isolation region 208 of the element covered with a thick oxide film is formed. First, oxidation was performed for 40 minutes in dry oxidation at 1000 ° C. to form a gate oxide film 202 of 40 nm. On the gate oxide film 202, a first polycrystalline silicon layer 204 containing, for example, phosphorus ions of 8 × 10 ²⁰ cm ⁻³ as a P-type impurity element was deposited to a thickness of 400 nm by thermal decomposition of silane in an atmosphere of 620 ° C. .

Next, a second polycrystalline silicon layer 215 containing, for example, phosphorus ions of 1 × 10 ²⁰ cm ⁻³ as a P-type impurity element was deposited to a thickness of 50 nm by thermal decomposition of silane in a 620 ° C. atmosphere. Next, a tungsten silicide layer 205 is deposited to a thickness of 200 nm by a sputtering method, and a silicon oxide layer 206 is deposited to a thickness of 200 nm by a CVD method.
m.

Next, desired patterning is performed by photolithography using a positive resist, and the first polysilicon layer 204, the tungsten silicide layer 205, and the silicon oxide layer 2 are formed by dry etching.
06 is etched to form the gate electrode layer 203. Dry etching uses CF ₄ gas, pressure 0.8
This is performed for 60 seconds at a power of 150 W in an mTorr atmosphere.

Further, oxidation is performed for 30 minutes in a steam atmosphere at 900 ° C. to form a silicon oxide layer 207 of about 100 nm around the gate electrode layer 203.

Thereafter, the source and drain portions 211 of the MOS transistor are opened by photolithography using a positive resist.
2 ions are implanted at 9 × 10 ¹⁵ cm ⁻² .

After that, an interlayer silicon oxide film 213 is deposited by, for example, a CVD method, a junction contact hole is opened by photolithography and dry etching, and a wiring metal, for example, an aluminum layer 214 is formed by a sputtering method. Then, the wiring metal is patterned by photolithography and dry etching.

In the above method, description has been made for a P-type MOS transistor, but the same applies to an N-type MOS transistor.

(Embodiment 2) FIG. 2 shows a MIS according to the present invention.
Is an embodiment of a method of manufacturing a semiconductor device of the type P,
The case of an OS transistor will be described step by step.

After an N-type well diffusion layer 210 is formed on a P-type silicon substrate 201, an active region 209 of the element is formed.
Then, an isolation region 208 of the element covered with a thick oxide film is formed. First, oxidation was performed for 40 minutes in dry oxidation at 1000 ° C. to form a gate oxide film 202 of 40 nm. On the gate oxide film 202, a first polycrystalline silicon layer 204 containing, for example, phosphorus ions of 8 × 10 ²⁰ cm ⁻³ as a P-type impurity element was deposited to a thickness of 400 nm by thermal decomposition of silane in an atmosphere of 620 ° C. .

Next, the second polycrystalline silicon layer 215 is
40 nm was deposited by thermal decomposition of silane in an atmosphere at 0 ° C. Next, a 200 nm thick tungsten silicide layer 205 is deposited by a sputtering method, and a 200 nm thick silicon oxide layer 204 is deposited by a CVD method.

Then, desired patterning is performed by photolithography using a positive resist, and the first polycrystalline silicon layer 204, the tungsten silicide layer 205, and the silicon oxide layer 2 are formed by dry etching.
06 is etched to form the gate electrode layer 203. Dry etching uses CF ₄ gas, pressure 0.8
This is performed for 60 seconds at a power of 150 W in an mTorr atmosphere.

Further, oxidation is performed in a steam atmosphere at 900 ° C. for 30 minutes to form a silicon oxide layer 207 of about 100 nm around the gate electrode layer 203.

Thereafter, the source and drain portions 211 of the MOS transistor are opened by photolithography using a positive resist.
2 ions are implanted at 9 × 10 ¹⁵ cm ⁻² .

After that, an interlayer silicon oxide film 213 is deposited by, for example, a CVD method, a junction contact hole is opened by photolithography and dry etching, and a wiring metal, for example, an aluminum layer 214 is formed by a sputtering method. Then, the wiring metal is patterned by photolithography and dry etching.

In the above method, the description has been made of the P-type MOS transistor, but the same applies to the N-type MOS transistor.

(Embodiment 3) FIG. 3 shows a MIS according to the present invention.
Is an embodiment of a method of manufacturing a semiconductor device of the type P,
The case of an OS transistor will be described step by step.

After forming an N-type well diffusion layer 210 on a P-type silicon substrate 201, an active region 209 of the element is formed.
Then, an isolation region 208 of the element covered with a thick oxide film is formed. First, oxidation was performed for 40 minutes in dry oxidation at 1000 ° C. to form a gate oxide film 202 of 40 nm. On the gate oxide film 202, a first polycrystalline silicon layer 204 containing, for example, phosphorus ions of 8 × 10 ²⁰ cm ⁻³ as a P-type impurity element was deposited to a thickness of 400 nm by thermal decomposition of silane in an atmosphere of 620 ° C. .

Next, a heat treatment is performed at a temperature of 870 ° C. for 20 minutes in a dry atmosphere at a temperature of 870 ° C. in order to form a silicon layer 216 with a low impurity element concentration of 10 ²⁰ cm ^{−3 on} the first polysilicon layer 204. Was. Next, a tungsten silicide layer 205 is deposited to a thickness of 200 nm by sputtering, and a silicon oxide layer 206 is deposited to a thickness of 20 nm by CVD.
Deposit 0 nm.

Next, desired patterning is performed by photolithography using a positive resist, and the first polysilicon layer 204, the tungsten silicide layer 205, and the silicon oxide layer 2 are formed by dry etching.
06 is etched to form the gate electrode layer 203. Dry etching uses CF ₄ gas, pressure 0.8
This is performed for 60 seconds at a power of 150 W in an mTorr atmosphere.

Further, oxidation is performed in a steam atmosphere at 900 ° C. for 30 minutes to form a silicon oxide layer 207 of about 100 nm around the gate electrode layer 203.

Thereafter, the source and drain portions 211 of the MOS transistor are opened by photolithography using a positive resist.
2 ions are implanted at 9 × 10 ¹⁵ cm ⁻² .

After that, an interlayer silicon oxide film 213 is deposited by, for example, a CVD method, a junction contact hole is opened by photolithography and dry etching, and a wiring metal, for example, an aluminum layer 214 is formed by a sputtering method. Then, the wiring metal is patterned by photolithography and dry etching.

In the above method, description has been made for a P-type MOS transistor, but the same applies to an N-type MOS transistor.

[0044]

As described above, according to the present invention, the diffusion of impurity elements from polycrystalline silicon into the compound layer of refractory metal and silicon can be reduced, and the volume shrinkage of polycrystalline silicon can be prevented. In this patterning, etching residue due to dry etching can be eliminated, and defect detection after gate electrode formation can be eliminated. In addition, since polycrystalline or amorphous silicon containing no impurities such as oxygen and nitrogen is used as the barrier layer, the dry etching step of the gate electrode patterning can be easily performed by the same method as the conventional method. .

[Brief description of the drawings]

FIG. 1 is a process cross-sectional view of one embodiment of a method of manufacturing a MIS semiconductor device of the present invention.

FIG. 2 is a process sectional view of one embodiment of a method of manufacturing a MIS semiconductor device of the present invention.

FIG. 3 is a process sectional view of one embodiment of a method of manufacturing a MIS semiconductor device of the present invention.

FIG. 4 is a process cross-sectional view of one embodiment of a conventional MIS type semiconductor device manufacturing method.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 101 ... Silicon substrate 102 ... Gate oxide film 103 ... Gate electrode layer 104 ... 1st polycrystalline silicon layer 105 ... Silicon compound layer containing refractory metal 106 ... Silicon oxide film 107 ... Silicon oxide layer 108 ... Element isolation region 109 ... Element active region 110 Well diffusion layer 111 Source / drain region 112 Ionized arsenic 113 Interlayer silicon oxide film 114 Aluminum layer 201 Silicon substrate 202 Gate oxide film 203 Gate electrode layer 204 First polycrystalline silicon layer 205 ... silicon compound layer containing high melting point metal 206 ... silicon oxide film 207 ... silicon oxide layer 208 ... element isolation region 209 ... element active region 210 ... well diffusion layer 211 ... source / drain region 212 ... ionized boron 213 ... interlayer oxidation Shi Thin polycrystalline silicon region con film 214 ... aluminum layer 215: second polysilicon layer 216 ... impurity concentration

Claims (7)

[Claims] A semiconductor device mainly comprises a conductor-insulating film-semiconductor substrate, and a material constituted as the semiconductor is composed of silicon as a main component at least in order from the insulating film. In a MIS semiconductor device comprising a first silicon layer containing silicon and a second silicon layer containing silicon as a main component and containing a high melting point metal, the first silicon layer and the second silicon A MIS type semiconductor device, wherein a silicon layer is interposed between layers. 2. A conductor-insulating film-semiconductor substrate is a main component of a semiconductor element, and a material constituted as the conductor is composed of silicon as a main component at least in order from the insulating film. In a MIS semiconductor device composed of a first silicon layer containing ions and a second silicon layer containing silicon as a main component containing a high melting point metal, the first silicon layer and the second silicon layer At most one group III or group V impurity element exists between silicon layers.
A MIS-type semiconductor device, wherein a silicon layer containing 0 ²⁰ cm ⁻³ or less is interposed. 3. The MIS type semiconductor device according to claim 1, wherein a silicon layer between the first silicon layer and the second silicon layer has a thickness of at least 20 nm or more. . 4. A method of manufacturing a MIS type semiconductor device, comprising:
Forming a silicon oxide film on at least a silicon substrate; depositing a first polycrystalline silicon layer or a first amorphous silicon layer containing a group III or group V impurity element; Depositing a second polycrystalline silicon layer or a second amorphous silicon layer containing an impurity element, and depositing a third silicon layer mainly containing silicon containing a high melting point metal;
A method for manufacturing a MIS-type semiconductor device, comprising a step of depositing silicon oxide or silicon nitride as an insulating layer on the third silicon layer. 5. A method for manufacturing a MIS type semiconductor device, comprising:
A step of forming a silicon oxide film on at least a silicon substrate, a step of depositing a first polycrystalline silicon layer or a first amorphous silicon layer containing a group III or V group impurity element, and a step of depositing a second polycrystalline silicon layer Depositing a silicon layer or a second amorphous silicon layer, depositing a third silicon layer containing silicon containing a high melting point metal as a main component, and forming silicon oxide as an insulating layer on the third silicon layer. Alternatively, a method for manufacturing a MIS semiconductor device, comprising a step of depositing silicon nitride. 6. A method of manufacturing a MIS type semiconductor device, comprising:
A step of forming a silicon oxide film on at least a silicon substrate, a step of depositing a first polycrystalline silicon layer or a first amorphous silicon layer containing a group III or group V impurity element, and a step of depositing a first silicon layer A step of performing a heat treatment immediately after the formation, a step of depositing a third silicon layer containing silicon containing a high melting point metal as a main component, and depositing silicon oxide or silicon nitride as an insulating layer on the third silicon layer A method for manufacturing a MIS type semiconductor device, comprising: 7. A method for manufacturing a MIS semiconductor device according to claim 6, wherein the temperature of the heat treatment is at least 870 ° C. or higher.