JPH05267332A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To keep the contact resistance of a metal silicide film with an S/D region low by a method wherein impurities of an opposite conductivity type are introduced selectively into a semiconductor substrate, at the lower part of a sidewall insulating film, which is exposed by selectively removing the sidewall insulating film and the concentration of the impurities of the opposite conductivity type in a region adjacent to the metal silicide film is increased. CONSTITUTION:A first insulating film 28 which is composed of a silicon oxide film is formed by a CVD method; in addition, a resist film 29 is formed on the first insulating film 28 by means of a coating method. Then, the resist film 29 is etched back; the first insulating film 28 is exposed. In succession, the first insulating film 28 and a sidewall insulating film are etched and removed selectively; a silicon substrate 21 at the lower part of the sidewall insulating film is exposed. Then, a through oxide film 30 is formed by a thermal oxidation operation. Then, boron particles are ion-implanted selectively into the silicon substrate 21 via the through oxide film 30; the concentration of boron in S/D regions 26a, 26b adjacent to metal silicide films 27a, 27b is increased.

Description

Detailed Description of the Invention

(Table of Contents) -Industrial application field-Conventional technology (Figs. 4 and 5) -Problem to be solved by the invention (Fig. 6) -Means for solving the problem-Action-Example (Fig. 1 to 3) ・ Effects of the invention

[0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device including a MOS transistor having a metal source / drain structure.

[0003]

2. Description of the Related Art In recent years, as one means for improving the performance of semiconductor integrated circuit devices, there has been a demand for reduction of contact resistance and the like. Therefore, for example, in a MOS transistor, a metal silicide film is interposed between the source / drain region layer and the source / drain electrode. Note that such a structure is called a metal source / drain structure.

FIGS. 4A to 4C are sectional views for explaining a conventional method of manufacturing a MOS transistor having a metal source / drain structure. Figure 4 (a) shows
FIG. 2 is a cross-sectional view showing a state after forming the source / drain region layer and before forming a metal silicide film, in which reference numeral 1 is a silicon substrate of one conductivity type, 2 is a field insulating film of an element isolation region, 3 is a gate oxide film formed in the element region surrounded by the field insulating film 2 and 4 is a gate oxide film 3
The upper gate electrode is composed of a two-layer conductor film of a polysilicon film 4a and a tungsten silicide film 4b. 5
a and 5b are formed by introducing a low concentration impurity of opposite conductivity type using the gate electrode 4 as a mask and further introducing a high concentration impurity of opposite conductivity type by using the insulating film 6 on the sidewall as a mask. LDD formed on substrate 1
The source / drain region layers of the structure.

In such a state, first, titanium (Ti) is deposited on the surface of each of the source / drain region layers 5a and 5b by sputtering or the like, and heat treatment is performed to form metal silicide films 7a and 7b made of titanium silicide. Form. Here, the metal silicide film 7 inside the silicon substrate 1
The ends A of the a and 7b on the side of the gate electrode 4 and the tips in the depth direction thereof are formed so as to come to a position where the conductivity type impurity concentration of the source / drain region layers 5a and 5b is almost maximum (FIG. 6 ( a)), a good ohmic contact is obtained between the metal silicide films 7a and 7b and the source / drain region layers 5a and 5b, and the metal silicide films 7a and 7b serve to reduce the contact resistance.

Next, after forming an interlayer insulating film 8 on the entire surface, openings 9a and 9b are formed in the interlayer insulating film 8 on the source / drain region layers 5a and 5b, and the metal silicide film 7 is formed.
Display a and 7b.

Next, by selectively forming the barrier metal films 10a and 10b made of a Ti film / TiN film and the Al wiring layers 11a and 11b on the barrier metal films 10a and 10b so as to cover the openings 9a and 9b, The MOS transistor is completed.

[0008]

By the way, in order to miniaturize the pattern in order to increase the density, the dose amount is kept constant, the acceleration energy is lowered, and the ion implantation is performed to make the source / drain region layer 5c. , 5d may be formed shallowly (FIG. 5A). However, in this case, when the metal silicide films 7c and 7d are subsequently formed (FIG. 5B), the source / drain region layers 5c and 5d are formed.
Since the depth is shallow, the tips of the end portions B of the metal silicide films 7c and 7d on the gate electrode 4 side have source / drain region layers 5c and 5c.
The maximum concentration of the conductivity type impurity of d is exceeded and the concentration of the conductivity type impurity reaches a low concentration position (FIG. 6B). Therefore, FIGS. 4 (b) to 4 (c)
There is a problem that the contact resistance of the MOS transistor shown in FIG. 5C, which is formed in the same process as the above, rather increases.

The present invention has been made in view of the above problems of the prior art. Even when the source / drain region layer is formed shallow, the contact resistance between the metal silicide film and the source / drain region layer is low. An object is to provide a manufacturing method of a semiconductor device that can be held.

[0010]

Means for Solving the Problems The above-mentioned problems are solved by using a gate electrode on a gate insulating film on a semiconductor substrate of one conductivity type and the opposite conductivity type on the semiconductor substrate on both sides of the gate electrode using the gate electrode as a mask. A step of selectively forming a metal silicide film on the source / drain region layer exposed on the surface of the semiconductor substrate having the source / drain region layer formed by introducing impurities and the sidewall insulating film of the gate electrode And a step of sequentially forming a first insulating film and an etching resistant coating film, and after removing the surface layer of the etching resistant coating film by etch back to expose the first insulating film or the sidewall insulating film. A step of selectively removing the sidewall insulating film using the etching resistant coating film as a mask to expose the semiconductor substrate under the sidewall insulating film, and the etching resistant coating film And a step of selectively introducing impurities of opposite conductivity type into the semiconductor substrate below the sidewall insulating film using the gate electrode as a mask to increase the concentration of impurities of opposite conductivity type in a region adjacent to the metal silicide film; Removing the film, covering the source / drain region layer, the gate electrode, and the semiconductor substrate on both sides of the gate electrode doped with the opposite conductivity type impurity with a second insulating film; And forming a source / drain electrode by connecting to the metal silicide film after forming an opening in the second insulating film on the metal silicide film of the drain region layer. ..

[0011]

According to the method of manufacturing a semiconductor device of the present invention, the sidewall insulating film is selectively removed, and the remaining etching resistant mask and the gate electrode are used as a mask to selectively oppose the semiconductor substrate below the sidewall insulating film. By introducing the conductivity type impurity, the concentration of the opposite conductivity type impurity in the source / drain region layer in the region adjacent to the metal silicide film is increased.

Therefore, when the source / drain region layer is formed shallowly, that is, the tip of the end portion of the metal silicide film on the side of the gate electrode 4 exceeds the maximum position of the conductivity type impurity concentration of the source / drain region layer and becomes low. Even when the concentration comes to the position of concentration, the opposite conductivity type impurity concentration of the source / drain region layer can be increased at the end of the metal silicide film on the gate electrode 4 side and the tip in the depth direction. .. As a result, the contact resistance between the metal silicide film and the source / drain region layer can be kept low.

[0013]

Embodiments of the present invention will now be described with reference to the drawings. 1 (a) to 1 (d) and 2 (e) to
(G) is a sectional view illustrating a method of manufacturing a MOS transistor having a metal source / drain structure according to an embodiment of the present invention.

FIG. 1A is a sectional view showing a state after forming the source / drain region layer and before forming a metal silicide film. In FIG. 1, reference numeral 21 is an n-type (one conductivity type).
Is a silicon substrate (semiconductor substrate), 22 is a field insulating film made of a silicon oxide film having a film thickness of about 3500 Å formed by selective oxidation in the element isolation region, and 23 is formed in the element region surrounded by the field insulating film 22. A gate oxide film having a film thickness of about 80Å, 24 is a gate electrode on the gate oxide film 23, and a polysilicon film 24a having a film thickness of about 500Å and a film thickness of about 1500
The tungsten silicide film 24b of Å consists of two layers. 25 is a film thickness covering the gate electrode 24 of about 1200Å
Is a side wall insulating film. Reference numerals 26a and 26b denote p-type (opposite conductivity type) source / drain (S / D) region layers having an LDD structure formed by introducing boron into the silicon substrate 21 on both sides of the gate electrode 24. First, using the gate electrode 24 as a mask, the acceleration energy is 60 KeV,
BF under the conditions of a dose amount of 1 × 10 ¹³ cm ⁻² , and then with an acceleration energy of 20 KeV and a dose amount of 2 × 10 ¹⁵ cm ^{−2 using} the gate electrode 24 and the sidewall insulating film 25 as a mask.
It is introduced by ion implantation using ₂ ⁺ particles.

In such a state, first, as shown in FIG. 1B, a film thickness of about 3 is formed on each surface of the S / D region layers 26a and 26b.
Deposit 50 Å titanium (Ti) film by sputtering,
Heat treatment is performed at a temperature of 600 ° C. to form metal silicide films 27a and 27b made of titanium silicide. At this time, the tips in the depth direction of the end portions C of the metal silicide films 27a and 27b inside the silicon substrate 21 on the gate electrode 24 side are deeper than the maximum boron concentration positions of the S / D region layers 26a and 26b. It is located at a deep and low concentration position (indicated by a two-dot chain line in FIG. 3).

Next, a first insulating film 28 made of a silicon oxide film having a film thickness of about 500 Å is formed on the entire surface by a CVD method, and a resist film having a film thickness of about 1 μm (etching resistance A coating film) 29 is formed by a coating method (FIG. 1C).

Next, the resist film 29 is etched back by O ₂ gas to expose the first insulating film 28. continue,
The first insulating film 28 and the sidewall insulating film 26 are selectively etched and removed by CF ₄ / H ₂ gas to remove the sidewall insulating film 2
The lower silicon substrate 21 is exposed (FIG. 1D).

Then, a through oxide film 30 having a film thickness of about 50Å
Are formed by thermal oxidation. Next, boron (opposite conductivity type impurities) particles are selectively deposited on the silicon substrate 21 through the through oxide film 30 with an acceleration energy of 20 KeV and a dose of 1
The metal silicide film 27 is introduced by ion implantation using BF ₂ ⁺ particles under the condition of × 10 ^{13 to} 2 × 10 ¹⁵ cm ^-2.
The boron concentration of the S / D region layers 26a and 26b in the regions adjacent to a and 27b is increased (FIG. 2 (e)). FIG. 3 shows the boron concentration distribution in the vicinity of the tip in the depth direction of the end portion C inside the silicon substrate 21 on the gate electrode 24 side of the metal silicide films 27a and 27b at this time. As shown in FIG. 3, the tips of the metal silicide films 27a and 27b come into contact with the high boron concentration portions. As a result, the S / D region layer 26
The contact state between a and 26b is improved, and the contact resistance is reduced. The metal silicide films 27a, 27
It has the effect of increasing the concentration of the surface layer of the silicon substrate 21 between the metal silicide films 27a and 27b and the gate electrode 24, not only at the tip of the end C of b, but also at the side of the end C.

Next, on the S / D region layers 26a and 26b, the gate electrode 24, and the silicon substrate 21 on both sides of the gate electrode 24 into which boron is introduced, an SOG film (second insulating film) having a film thickness of about 3000 Å is formed. Interlayer insulating film (second insulating film)
31 is formed by a coating method. Then, the S / D region layer 26
Openings 32a and 32b penetrating the interlayer insulating film 31, the through oxide film 30 and the first insulating film 28 above a and 26b are formed to expose the metal silicide films 27a and 27b (FIG. 2).
(F)).

Next, the openings 32a and 32b are covered with titanium (Ti) so as to be connected to the metal silicide films 27a and 27b.
Film / barrier metal film made of titanium nitride (TiN) film 33
a, 33b and the Al wiring layer 34 on the barrier metal films 33a, 33b
By selectively forming a and 34b, a MOS transistor is completed (FIG. 2 (g)).

As described above, according to the embodiment of the present invention,
After selectively removing the sidewall insulating film 25, the sidewall insulating film 25 is removed.
Since boron is selectively introduced into the lower silicon substrate 21 to increase the boron concentration in the S / D region layers 26a and 26b in the regions adjacent to the metal silicide films 27a and 27b, the S / D region layers 26a and 26b. When the gate is formed shallow, that is, the tip of the end of the metal silicide films 27a and 27b on the gate electrode 24 side is S
Even when the boron concentration of the / D region layers 26a and 26b exceeds the maximum boron concentration and comes to a low concentration position, the metal silicide films 27a and 27b have their end portions on the gate electrode 24 side and the depth direction thereof. The boron concentration of the S / D region layers 26a and 26b at the tip can be increased. As a result, the contact resistance between the metal silicide films 27a and 27b and the S / D region layers 26a and 26b can be kept low.

Although the n-type silicon substrate 21 is used in the above embodiment, an n-type buried layer may be used. Further, instead of the n-type silicon substrate 21, a p-type silicon substrate or a p-type buried layer may be used. In this case, the S / D region layers 26a and 26b are n-type, and arsenic (As) or phosphorus (P) can be used as the opposite conductivity type impurities.

Although the titanium silicide films are used as the metal silicide films 27a and 27b in the above embodiment, tungsten or other silicide films may be used.

[0024]

As described above, according to the method of manufacturing a semiconductor device of the present invention, the side wall insulating film is selectively removed and exposed, and the semiconductor substrate below the side wall insulating film is selectively opposite in conductivity type. Introducing impurities, S in the region adjacent to the metal silicide film
The opposite conductivity type impurity concentration of the / D region layer is increased.

Therefore, the contact resistance between the metal silicide film and the S / D region layer is compensated for by compensating for the decrease in the impurity concentration of the opposite conductivity type at the junction with the metal silicide film due to the shallow formation of the S / D region layer. Can be kept low.

[Brief description of drawings]

FIG. 1 is a sectional view (No. 1) for explaining a method of manufacturing a MOS transistor having a metal source / drain structure according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view (No. 2) for explaining the method of manufacturing the MOS transistor having the metal source / drain structure according to the embodiment of the present invention.

FIG. 3 is a diagram for explaining compensation of conductivity type impurity concentration according to the embodiment of the present invention.

FIG. 4 is a cross-sectional view illustrating a method of manufacturing a MOS transistor having a conventional metal source / drain structure.

FIG. 5 is a cross-sectional view illustrating another method of manufacturing a MOS transistor having a metal source / drain structure of the related art.

FIG. 6 is a diagram illustrating a problem of a conventional example.

[Explanation of symbols]

 21 silicon substrate (semiconductor substrate), 22 field insulating film, 23 gate oxide film, 24 gate electrode, 24a polysilicon film, 24b tungsten silicide film, 25 sidewall insulating film, 26a, 26b S / D region layer, 27a, 27b metal Silicide film, 28 First insulating film, 29 Resist film (etching resistant coating film), 30 Through oxide film, 31 Interlayer insulating film, 32a, 32b openings, 33a, 33b Barrier metal film, 34a, 34b Al wiring layer .

Claims (1)

[Claims] 1. A gate electrode formed on a gate insulating film on a semiconductor substrate of one conductivity type, and formed by introducing impurities of opposite conductivity type into the semiconductor substrate on both sides of the gate electrode using the gate electrode as a mask. Selectively forming a metal silicide film on the source / drain region layer exposed on the surface of the semiconductor substrate having the source / drain region layer and the sidewall insulating film of the gate electrode, and a first insulating film. A step of sequentially forming an etching resistant coating film, and removing the surface layer of the etching resistant coating film by etching back to expose the first insulating film or the sidewall insulating film, and then forming the etching resistant coating film. Selectively removing the sidewall insulating film as a mask to expose the semiconductor substrate under the sidewall insulating film, and using the etching resistant coating film and the gate electrode as a mask Selectively introducing impurities of opposite conductivity type into the semiconductor substrate under the sidewall insulating film to increase the concentration of impurities of opposite conductivity type in a region adjacent to the metal silicide film, and after removing the etching resistant coating film. Covering the source / drain region layer, the gate electrode, and the semiconductor substrate on both sides of the gate electrode into which the opposite conductivity type impurity has been introduced with a second insulating film.