JPH10242077A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a semiconductor device capable of preventing nonuniform or excessive silicide. SOLUTION: This device is provided with an MOS field effect transistor 15 having a Ge containing layer 8 in the surface vicinity of a drain region 5, and an Al wiring 14 electrically connected with the drain region 5 through a connection hole 13a, in which the following are formed; a titanium silicide layer 9 formed to be in contact with the Ge containing layer 8, a Ti layer 10 which is deposited on a substrate 1 by silicide reaction with Si in a silicon substrate 1, in order to form a titanium silicide layer 9, a TiN layer 11 as a buffer layer, and a W plug 12. Thereby nonuniform or excessive silicide can be prevented at the time of formation, local aggregation of the titanium silicide layer 9 is not generated, a junction part of drain or source regions 5, 6 can be shallowed, and excellent electric characteristics can be obtained, when a transistor is micronized.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a titanium silicide layer and a method for manufacturing the same.

[0002]

2. Description of the Related Art In recent years, there has been a remarkable development in microfabrication technology due to the demand for higher integration in semiconductor devices. Specifically, ultrafine processing of 0.35 μm or less has been enabled. Along with such miniaturization of semiconductor devices, a new problem affecting device performance is an increase in contact resistance in fine connection holes used for electrical connection between a silicon substrate and an upper electrical element. Is coming.

In order to solve this problem, recently, a refractory metal film is formed on a silicon substrate, and then an appropriate heat treatment is applied to react Si in the silicon substrate with the refractory metal. There has been much research into siliciding high-melting metal films and applying the obtained low-resistance metal silicide films as contact materials between silicon substrates and upper electrical elements.

A method for manufacturing a semiconductor device having a metal silicide film formed by a conventional silicidation technique in a contact portion inside a fine connection hole will be described below.
Here, FIG. 9 is a fragmentary cross-sectional view showing a method for manufacturing the semiconductor device in the order of steps.

First, as shown in FIG. 9A, an element isolation film 3 formed on one main surface of a silicon substrate 1 is electrically separated from other element formation regions by, for example, an ion implantation method. An active region 20 exposed on the surface of the substrate 1 is formed, and an interlayer insulating film 13 having a connection hole 13a opened on the exposed surface of the active region 20 is formed on the substrate 1.

Next, as shown in FIG. 9B, the Ti film 10a and the TiN film 11a are successively formed in this order by, for example, a sputtering method in the active region 20 exposed at the bottom of the connection hole 13a. It is deposited on the substrate 1 including the surface.

Next, as shown in FIG. 9C, an annealing process is performed to cause the Ti in the Ti film 10a to react with the Si in the silicon substrate 1 so that the Ti film 10a and the silicon substrate 1 A titanium silicide film 90 is formed at the interface. Here, the titanium silicide film 90 is formed non-uniformly due to the influence of a natural oxide film existing on a part of the surface of the silicon substrate 1. Also, this non-uniform reaction is caused by the connection hole 1
It becomes more conspicuous as 3a becomes finer.

Next, as shown in FIG. 9D, for example, a blanket CVD (Chemical Vapor D)
The W film 12a is connected to the connection hole 1 by the deposition method.
3a is deposited on the substrate 1 including the inside.

[0009] Next, as shown in FIG.
a, the TiN film 11a and the Ti layer 10a are etched back, and the titanium silicide layer 9, the Ti layer 1
0, a TiN layer 11 as a barrier layer and a W plug 12 are formed.

[0010] Next, as shown in FIG.
4a is formed on the substrate 1 including the connection hole 13a where the W plug 12 is formed. Thereafter, the Al film 14a is patterned by using a photoengraving technique to obtain an Al film having a desired shape.
A semiconductor device is formed by forming wiring.

[0011]

However, in the semiconductor device formed as described above, the reaction between the silicon substrate 1 and the Ti film 10a does not occur due to the influence of a natural oxide film or the like existing on the surface of the silicon substrate 1. Become uniform, especially
In the minute connection hole 13a, the problem is conspicuous, and problems such as variation in contact resistance and increase in junction leakage current occur, and device characteristics deteriorate.

Further, such non-uniformity of the silicide interface,
Deterioration of flatness or the like causes electrical characteristics to deteriorate not only in the contact resistance in the fine connection hole but also in the silicide wiring and salicide processes.

The present invention has been made in view of the above points, and has as its object to obtain a semiconductor device capable of preventing non-uniform silicidation or excessive silicidation.

[0014]

A semiconductor device according to the present invention comprises: a silicon substrate having a Ge-containing layer near a surface;
The semiconductor device includes a conductor electrically connected to the silicon substrate, and a titanium silicide layer formed at an interface between the silicon substrate and the conductor.

Also, a G layer is formed on one main surface of the silicon substrate and is located near at least one surface of the source and drain regions.
a MOS field-effect transistor having an e-containing layer, a conductor electrically connected to the source or drain region having the Ge-containing layer, a source or drain region having the Ge-containing layer, and an interface between the conductors And a titanium silicide layer formed on the substrate.

Further, the semiconductor device is provided with a wiring formed on the semiconductor substrate, and the wiring includes a silicon layer having a Ge-containing layer near the surface and a titanium silicide layer formed on the silicon layer. It is assumed that.

According to a method of manufacturing a semiconductor device according to the present invention,
In a method for manufacturing a semiconductor device having a MOS field-effect transistor formed on one main surface of a silicon substrate,
Forming source and drain regions on the main surface of the silicon substrate; and ion-implanting Ge into at least one of the source and drain regions to form a Ge near the surface thereof.
Forming a Ti-containing layer, and depositing Ti on the source or drain region where the Ge-containing layer is formed;
Reacting the deposited Ti and Si in the source or drain region on which the Ge-containing layer is formed to form a titanium silicide layer on the source or drain region; and a main surface of the silicon substrate. Forming an interlayer insulating film having a connection hole opened in the titanium silicide layer thereon, and forming a conductive layer electrically connected to the source or drain region on which the Ge-containing layer is formed through the connection hole. And forming a body.

[0018] Further, the semiconductor device is formed on one main surface of a silicon substrate.
In a method of manufacturing a semiconductor device having a MOS field-effect transistor, a step of forming source and drain regions on a main surface of the silicon substrate; and forming at least one of the source and drain regions on the main surface of the silicon substrate. Forming an interlayer insulating film having a connection hole that opens, and implanting Ge using the connection hole as a mask to form a Ge-containing layer near the surface of the source or drain region where the connection hole opens, Depositing Ti on the source or drain region where the connection hole is opened, and reacting the deposited Ti and Si in the source or drain region where the Ge-containing layer is formed, thereby forming the source or drain. Forming a titanium silicide layer on the region and, via the connection hole, the source or drain region where the Ge-containing layer is formed. It is intended to include a step of forming a gas-connected electrical conductors.

In a method of manufacturing a semiconductor device having a wiring formed on a semiconductor substrate, a step of forming a silicon layer on the semiconductor substrate and a step of implanting Ge into the silicon layer by ion implantation are performed. Forming a Ge-containing layer near the surface, depositing Ti on the silicon layer, depositing Ti and S in the silicon layer.
i) reacting to form a titanium silicide layer on the silicon layer; and patterning the silicon layer and the titanium silicide layer to form a wiring.

Further, in the method of manufacturing a semiconductor device provided with wiring formed on a semiconductor substrate, a step of forming a wiring-shaped silicon layer on the semiconductor substrate, and ion-implanting Ge into the silicon layer, Forming a Ge-containing layer near the surface of the silicon layer;
And forming a wiring by reacting the deposited Ti and Si in the silicon layer to form a titanium silicide layer on the silicon layer.

[0021]

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiment 1 FIG. Hereinafter, a first embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a fragmentary cross-sectional view showing the structure of the semiconductor device according to the first embodiment of the present invention. In FIG. 1, 1 is a P-type silicon substrate, 2 is a P-type well formed on one main surface of the silicon substrate 1, and 3 is a LOC, for example, LOC on the main surface of the silicon substrate 1.
It is an element isolation film formed by using the OS method.

Reference numeral 15 denotes an N-channel type M formed in a region surrounded by the element isolation film 3 on the main surface of the silicon substrate 1.
The OS field-effect transistor 4 is the transistor 1
The gate electrode 5 is formed on the silicon substrate 1 via the gate insulating film 7 and forms a part of a word line.

Reference numeral 5 denotes an N-type drain region of the transistor 15, which is formed on the main surface of the silicon substrate 1 so as to be surrounded by the P-type well 2 and to be exposed on the surface of the substrate 1, and to be formed of Ge. Containing layer (Ge containing layer) 8
In the vicinity of the surface. Reference numeral 6 denotes an N-type source region of the transistor 15, which is formed on the main surface of the silicon substrate 1 so as to be surrounded by the P-type well 2 and to be exposed on the surface of the substrate 1, and to be below the gate electrode 4. , Is formed so as to face the drain region 5.

Reference numeral 13 denotes an interlayer insulating film formed on the silicon substrate 1 so as to cover the transistor 15 and made of, for example, a silicon oxide film such as a TEOS oxide film. Reference numeral 13a denotes an interlayer insulating film opening in the Ge-containing layer 8. 13 are connection holes.

Reference numeral 9 denotes a titanium silicide layer formed inside the connection hole 13a so as to contact the Ge-containing layer 8, and a Ti layer 10 formed inside the connection hole 13a.
It is formed by the reaction between Ti in the inside and Si in the silicon substrate 1. Reference numeral 12 denotes a W plug formed in the connection hole 13a, which is formed by the TiN layer 11 as a barrier layer so as to avoid direct contact with the substrate 1. Reference numeral 14 denotes an Al wiring 14 formed on the interlayer insulating film 13, and is electrically connected to the drain region 5 of the transistor 15 via the titanium silicide layer 9.

Next, a method of manufacturing the semiconductor device thus configured will be described with reference to FIGS. 2 and 3 are cross-sectional views of relevant parts showing a method of manufacturing a semiconductor device in this order.

First, as shown in FIG. 2A, an element isolation film 3 is formed on one main surface of, for example, a P-type silicon substrate 1 by using, for example, the LOCOS method, and ions such as BF ₂ or boron are formed. Implantation is performed to form a P-type well 2, and then a gate insulating film 7 is formed on the main surface of the substrate 1 by, for example, a thermal oxidation method, and a polycrystalline silicon film or a non-crystalline A conductive film made of a crystalline silicon film or the like is deposited using a CVD method, and is patterned into a desired shape using a normal photolithography technique, thereby forming a gate electrode 4 forming a part of a word line.

Subsequently, using the end of the gate electrode 4 or the side wall formed on the side wall thereof as a mask, for example, phosphorus or arsenic ions are implanted, and the N-type drain region 5 and the source region 6 are Formed on the main surface. After that, for example, TEO
An interlayer insulating film 13 made of an S oxide film is formed, and a connection hole 13a opening on the surface of the drain region 5 is formed in the interlayer insulating film 13 using a normal photolithography technique.

Next, as shown in FIG. 2B, using the connection hole 13a as a mask, for example, 30 to 200 keV
Energy of 10 ¹⁴ to 10 ¹⁶ / cm ² and Ge
Is implanted into the substrate 1 by an ion implantation method. Subsequently, a Ge implantation layer 8 having a depth of 100 nm or less is formed near the surface of the drain region 5 by performing a heat treatment. Here, the heat treatment is performed by SAC (Self Align Co.).
In the case of performing ntact) implantation, a heat treatment for SAC performed for that may be used instead.

Next, as shown in FIG. 2C, a Ti layer 10a is formed using a CVD method so as to be in contact with the Ge-containing layer 8 inside the connection hole 13a. Specifically, first, a natural oxide film formed on a part of the bottom of the connection hole 13a is removed by using a pretreatment technique such as a sputter etching method, and then the substrate 1 is vacuum-transferred or the like, The natural oxide film is transported to a film forming apparatus for CVD-Ti so as not to be formed again, and then, for example, titanium tetrachloride (Ti
Plasma CVD using Cl ₄ ) -hydrogen (H ₂ ) -based gas
The Ti layer 10a is formed by using the method.

Here, the silicon substrate 1 is formed by using the CVD method.
The Ti in the Ti layer 10a formed thereon immediately reacts with Si in the silicon substrate 1 and becomes the titanium silicide layer 9, unlike the case where the Ti is formed using a sputtering method or the like.

Next, as shown in FIG.
Using the VD method or the sputtering method, Ti
An N film 11a is deposited, and subsequently, for example, a blanket CV
A W film 12a is deposited on the entire surface of the substrate 1 by using the D method.

Next, as shown in FIG.
a, the TiN film 11a and the Ti layer 10a are etched back, and the titanium silicide layer 9, the Ti layer 1
0, a TiN layer 11 as a barrier layer and a W plug 12 are formed.

Next, as shown in FIG.
4a is deposited on the substrate 1 including on the connection holes 13a.

Then, using the photomechanical technology, the above Al
By patterning the film 14a and forming the Al wiring 14 into a desired shape, a semiconductor device having the structure shown in FIG. 1 is obtained.

Conventionally, when a Ti layer is formed by the CVD method, the reaction with the silicon substrate is violent, and silicidation proceeds immediately, and a titanium silicide layer having poor morphology is formed. In the first embodiment, Ge
The containing layer 8 is formed on the surface of the substrate 1 where the silicidation reaction takes place, and the Ge in the Ge containing layer 8 becomes the T in the Ti layer.
Since i and Si in the silicon substrate hardly react with each other, silicidation is suppressed, and a titanium silicide layer 9 having good morphology can be obtained. Therefore, better contact characteristics between the drain region 5 having the Ge-containing layer 8 and the Al wiring 14 can be obtained as compared with the related art.

Further, since local aggregation of the titanium silicide layer 9 does not occur, the depth at the junction of the drain region 5 can be reduced, and when the MOS field effect transistor 15 is miniaturized, In this case, good electrical characteristics can be obtained. Further, there is an effect that the yield of the semiconductor device can be improved.

Further, in the first embodiment, the case where the MOS field-effect transistor 15 is of the N-channel type has been described, but in the step shown in FIG. Alternatively, BF ₂ may be ion-implanted with phosphorus, arsenic, or the like instead of boron or BF ₂ ,
In this case, the source and drain regions and the well can be formed in a shape in which the N (and P) type region shown in FIG. 1 is changed to the P (and N) type.
It has the same effect as above.

In the first embodiment, Ge is used for suppressing the silicide reaction. However, another substance may be used as long as it can suppress the reaction between Ti and Si. In the above description, the Ge-containing layer 8 is formed using the ion implantation method. However, the Ge-containing layer 8 may be formed near the surface of the substrate 1 using diffusion. The same effect as described above is obtained.

Although the Ti layer 10a is formed by using the CVD method, it may be formed by using a sputtering method. In this case, heat treatment is performed after the formation of the Ti layer 10a or after the formation of the TiN layer 11a. By performing the application, the titanium silicide layer 9 can be obtained. Even in the titanium silicide layer 9 thus obtained, since no local aggregation occurs, the depth at the junction of the drain region 5 can be reduced, and the MOS field-effect transistor 15 Even in the case of miniaturization, there is an effect that good electrical characteristics can be obtained.

Further, in the first embodiment, the Al wiring 14 is electrically connected to the drain region 5, but may be connected to the source region 6 instead. This has the same effect as the first embodiment.

Although the W plug 12 is formed inside the connection hole 13a, another conductive material such as Al may be used instead, and the electrical connection between the Al wiring 14 and the substrate 1 may be made. It is not always necessary to embed the connection hole 13a as long as a proper connection can be achieved. In these cases, the same effects as in the first embodiment can be obtained.

In the first embodiment, the Ti layer 10a is formed by a plasma CVD method using a titanium tetrachloride (TiCl ₄ ) -hydrogen (H ₂ ) -based gas.
The method for forming the Ti layer 10a using the D method is not limited to this, and may be, for example, titanium tetrachloride (TiCl ₄ ).
A thermal CVD method using a silane (SiH ₄ ) -based gas may be used. In this case, the same effect as in the first embodiment is obtained.

In the first embodiment, Ge ions are implanted after opening the connection holes 13a. Instead, the drain and source regions 5 are formed in the step shown in FIG. , 6 may be formed and before the formation of the interlayer insulating film 13, the ion implantation may be performed. In this case, if the same implantation conditions are used for Ge, the subsequent heat treatment may substantially reduce the ion implantation. G at similar depth
An e-containing layer can be formed, and a titanium silicide layer 9 is formed by a reaction between the Ge-containing layer and the CVD-Ti layer 10a deposited inside the connection hole 13a. It has the same effect.

Here, the heat treatment performed after the ion implantation may be replaced by the heat treatment performed after the ion implantation for forming the drain and source regions 5 and 6. In this case, the same effect as described above can be obtained. Can be

Embodiment 2 Hereinafter, a second embodiment of the present invention will be described with reference to FIGS.
FIG. 4 is a fragmentary cross-sectional view showing a structure of a semiconductor device according to a second embodiment of the present invention. In FIG. 4, reference numeral 1 denotes a P-type silicon substrate, 2 denotes a P-type well formed on one main surface of the silicon substrate 1, and 3 denotes a P-type well on the main surface of the silicon substrate 1.
For example, it is an element isolation film formed by using the LOCOS method.

Reference numeral 16 denotes an N-channel MOS formed in a region surrounded by the element isolation film 3 on the main surface of the silicon substrate 1.
The field effect transistor 4 is a gate electrode of the transistor 16, is formed on the silicon substrate 1 via the gate insulating film 7, and forms a part of the word line 17. Here, the gate electrode 4 (word line 17)
Is a silicon film 4a made of, for example, polycrystalline silicon, and a Ge-containing layer 4 formed near the surface of the silicon film 4a.
b, and a titanium silicide layer 4c formed on the silicon layer 4a at a position in contact with the Ge-containing layer 4b.

Reference numerals 5 and 6 denote N-type drain and source regions of the transistor 16, both of which are surrounded on the main surface of the silicon substrate 1 by the P-type well 2 and exposed on the surface of the substrate 1. And G
An e-containing layer (Ge-containing layer) 8 is provided in the vicinity of the surface, and in addition, formed below the gate electrode 4 so as to face each other.

Reference numeral 9 denotes a titanium silicide layer formed on the Ge-containing layers 4b and 8 so as to be in contact with the respective layers, and 13 denotes a titanium silicide layer formed on the silicon substrate 1 so as to cover the transistor 16. For example, an interlayer insulating film 13a made of a silicon oxide film such as a TEOS oxide film, and 13a is a connection hole formed in the interlayer insulating film 13 opening in the titanium silicide layer 9 formed on the drain region 5.

Reference numeral 12 denotes a W plug formed in the connection hole 13a. The W plug 12 is formed by the TiN layer 11 as a barrier layer.
It is formed so as to avoid direct contact with. Also, 14
Is an Al wiring formed on the interlayer insulating film 13, and is electrically connected to the drain region 5 of the transistor 16 via the titanium silicide layer 9.

Next, a method of manufacturing the semiconductor device thus configured will be described with reference to FIGS. 5 and 6 are cross-sectional views of a main part showing a method of manufacturing a semiconductor device in this order in the order of steps.

[0052] First, as shown in FIG. 5 (a), for example, on one main surface of the P-type silicon substrate 1, for example using a LOCOS method to form an isolation layer 3, for example, BF ₂ or ions such as boron Implantation is performed to form a P-type well 2, and then a gate insulating film 7 is formed on the main surface of the substrate 1 by, for example, a thermal oxidation method, and a polycrystalline silicon film or a non-crystalline A silicon film made of a crystalline silicon film or the like is deposited using a CVD method, and is patterned into a desired shape using a normal photolithography technique, thereby forming a silicon gate electrode 4a forming a part of a word line.

Subsequently, using the end of the silicon gate electrode 4a or the side wall formed on the side wall thereof as a mask, for example, phosphorus or arsenic is ion-implanted, and the N-type drain region 5 and the source region 6 are made 1 is formed on the main surface.

Thereafter, for example, Ge is implanted at an energy of 30 to ²⁰⁰ keV and an implantation dose of 10 ¹⁴ to 10 ¹⁶ / cm ² ,
The substrate 1 is implanted by an ion implantation method. Subsequently, a heat treatment is applied to deposit the Ge implantation layer 8 to a depth of 100 nm or less, the drain and source regions 5 and 6 and the silicon gate electrode 4.
a. Here, the heat treatment may be replaced by a heat treatment for forming the regions 5 and 6 after the source and drain are implanted.

Next, as shown in FIG. 5B, a Ti layer 10a is deposited on the entire surface of the silicon substrate 1 by using a sputtering method.

Next, as shown in FIG. 5 (c), the deposited Ti layer 10a is annealed, and Ti in the Ti layer 10a and Si in the substrate 1 or the silicon gate electrode 4a are etched.
To form a titanium silicide layer 9 on the drain and source regions 5 and 6 and on the silicon gate electrode 4a. Here, at a position where there is no silicon layer below the Ti layer 10a, that is, on the isolation oxide film 3 or on the sidewall, the Ti layer 10a is not silicided, and the titanium silicide layer 9 is not formed.

Next, as shown in FIG. 6A, the unsilicided Ti film 10a is removed using, for example, a mixed solution of sulfuric acid and hydrogen peroxide, and the titanium silicide layer 9 is removed from the silicon substrate 4a. Leave on 5 and 6. Here, if necessary, heat treatment may be performed again.

Next, as shown in FIG. 6B, an interlayer insulating film 13 made of, for example, a TEOS oxide film is formed on the entire surface of the silicon substrate 1, and the drain region 5 is formed by using a normal photolithography technique. Connection hole 1 opening in upper titanium silicide film 9
3a, and a TiN film 11 is formed on the entire surface of the substrate 1 including the inside of the connection hole 13a by using the CVD method or the sputtering method.
a, and then using a blanket CVD method,
A W film 12a is deposited on the entire surface of the substrate 1. Where Ti
Instead of the N film 11a, a TiN / Ti laminated film may be deposited.

Next, as shown in FIG. 6C, the W film 12
a and the TiN film 11a are etched back to form a connection hole 13a.
Inside, a TiN layer 11 as a barrier layer and a W plug 12
Is formed, and an Al film 14a is deposited on the entire surface of the substrate 1 including on the connection holes 13a.

Thereafter, using the photomechanical technology, the above Al
By patterning the film 14a and forming the Al wiring 14 in a desired shape, a semiconductor device having the structure shown in FIG. 4 is obtained.

In the second embodiment, the Ge-containing layer 8
Is formed on the surface of the substrate 1 where a silicidation reaction occurs, and Ge does not easily react with Ti and Si. Therefore, silicidation is suppressed, and the titanium silicide layer 9 having good morphology can be obtained. Therefore, better contact characteristics between the drain region 5 having the Ge-containing layer 8 and the Al wiring 14 can be obtained as compared with the related art. Further, since local aggregation of the titanium silicide layer 9 does not occur, the depth at the junction of the drain region 5 can be reduced, and even when the MOS field-effect transistor 15 is miniaturized, Good electrical characteristics can be obtained.

In the second embodiment, since the Ge-containing layer 4b is formed near the surface of the silicon gate electrode 4a, the titanium silicide layer 4c having good flatness can be formed. Exposure margins and the like in the photolithography process in the upper layer of the word line 17 including the word lines can be easily secured.
Further, since local aggregation of the titanium silicide layer 4c does not occur, variation in the resistance value in the word line 17 can be suppressed, electric field concentration and the like can be prevented, and therefore, the reliability of the wiring 17 can be improved. Further, there is an effect that an increase in the resistance value of the wiring 17 as a whole can be suppressed.

In the above case, the case where the MOS field-effect transistor 15 is of the N-channel type has been described. In the step shown in FIG. 5A, instead of phosphorus, arsenic, etc., boron or BF is used. _2, phosphorus instead of boron or BF _2, even if arsenic was ion-implanted each well, in this case, changing the area of the N (and P) type shown in FIG. 4 to P (and N) type The source and drain regions and the well can be formed in different shapes, so that the same effect as described above can be obtained.

In the second embodiment, Ge is used for suppressing the silicide reaction. However, another substance may be used as long as it can suppress the reaction between Ti and Si. In the above description, the Ge-containing layer 8 is formed by using the ion implantation method. However, the Ge-containing layer 8 or 4b may be formed near the surface of the substrate 1 or the silicon gate electrode 4a by using diffusion. In this case, the same effect as in the second embodiment can be obtained.

Although the Ti layer 10a is formed by using the sputtering method, it may be formed by using the CVD method. In this case, the titanium silicide layer 9 can be obtained without performing heat treatment. Also in the titanium silicide layer 9 obtained in this way, since local aggregation does not occur, the same effect as in the second embodiment can be obtained.

Although the Al wiring 14 is electrically connected to the drain region 5, there is no change even if the Al wiring 14 is connected to the source region 6, and the same effect as in the second embodiment is obtained. Will be provided.

Although the W plug 12 is formed inside the connection hole 13a, another conductive material such as Al may be used instead. Alternatively, the electrical connection between the Al wiring 14 and the substrate 1 may be made. It is not always necessary to embed the connection hole 13a as long as a proper connection can be achieved. In these cases, the same effects as in the second embodiment can be obtained.

Embodiment 3 Hereinafter, a third embodiment of the present invention will be described with reference to FIGS. FIG.
FIG. 7 is a fragmentary cross-sectional view showing a structure of a semiconductor device according to Embodiment 3 of the present invention. In FIG. 7, reference numeral 100 denotes a semiconductor substrate main body made of, for example, a silicon substrate, and a semiconductor element formed thereon. A semiconductor substrate 19 is an interlayer insulating film made of, for example, a silicon oxide film formed on the semiconductor substrate 100, and 18 is a wiring formed on the interlayer insulating film 19, and the wiring 18 is made of, for example, a polycrystalline silicon film or It is made of an amorphous silicon film, and Ge is
The silicon film 180 having the containing layer 181 and the titanium silicide layer 182 formed thereon are laminated.

Next, a method of manufacturing the semiconductor device thus configured will be described with reference to FIG. FIG. 8 is a fragmentary cross-sectional view showing the method of manufacturing the semiconductor device according to the third embodiment in the order of steps.

First, as shown in FIG. 8A, for example, on a silicon oxide film 19 on a semiconductor substrate 1 having a semiconductor substrate body made of, for example, a silicon substrate and a semiconductor element formed thereon, The polycrystalline silicon film 180 is formed by using the CVD method, and then, for example, 30 to 2
Ge is implanted into the polycrystalline silicon film 180 by ion implantation at an energy of 00 keV and an implantation amount of 10 ¹⁴ to 10 ¹⁶ / cm ² . After that, by applying heat treatment,
A Ge implantation layer 181 having a depth of 100 nm or less is formed near the surface of the polycrystalline silicon film 180.

Next, as shown in FIG. 8B, a Ti layer 10a is formed on the Ge-containing layer 18 by using, for example, a sputtering method.
1 is formed on the polycrystalline silicon film 180.

Next, as shown in FIG. 8C, an annealing process is performed to cause the Ti in the Ti layer 10a to react with the Si in the polycrystalline silicon film 180, thereby forming a titanium silicide layer 182.
To form

Thereafter, the wiring 18 is formed by patterning the titanium silicide layer 182 and the polycrystalline silicon film 180 having a Ge-containing layer 181 in the vicinity of the surface by using photolithography. Is obtained.

In the third embodiment, since Ge does not easily react with Ti and Si, the presence of the Ge-containing layer 181 between the Ti layer 10a and the polycrystalline silicon film 180 allows the formation of the Ti layer 10a. Silicidation is suppressed, excessive silicidation and non-uniform silicidation do not occur, and aggregation of titanium silicide is prevented. Therefore, the titanium silicide layer 182 having good flatness can be formed, that is, the wiring 1
8 can be achieved, and it becomes easy to secure an exposure margin and the like in a photolithography process in a further upper layer of the wiring 18.

Further, since local aggregation of the titanium silicide layer 182 does not occur, variation in the resistance value in the wiring 18 can be suppressed, electric field concentration and the like can be prevented.
8 can be improved in reliability. Further, there is an effect that an increase in the resistance value of the wiring 18 as a whole can be suppressed.

In the third embodiment, Ge is used for suppressing the silicide reaction. However, another substance may be used as long as it can suppress the reaction between Ti and Si. In the above, the Ge-containing layer 18 is formed by ion implantation.
1 is formed, but the polycrystalline silicon film 1 is formed by diffusion.
A Ge-containing layer 181 may be formed near the surface of 80.
In this case, the same effect as in the third embodiment is obtained.

Although the Ti layer 10a is formed by using the sputtering method, it may be formed by using the CVD method. In this case, the titanium silicide layer 182 can be obtained without performing heat treatment. Even in the titanium silicide layer 182 obtained in this way, since local aggregation does not occur, the same effect as in the second embodiment can be obtained.

[0078]

The semiconductor device according to the present invention has a silicon substrate having a Ge-containing layer near the surface, a conductor electrically connected to the silicon substrate, and an interface between the silicon substrate and the conductor. Since it is provided with a titanium silicide layer that has been formed, uneven silicidation and excessive silicidation can be prevented during the formation thereof, and as a result, a titanium silicide layer with good flatness can be formed, and the silicon silicide layer can be formed. This has the effect that good contact characteristics between the substrate and the conductor can be obtained.

Further, a G layer is formed on one main surface of the silicon substrate and is located near at least one surface of the source and drain regions.
a MOS field-effect transistor having an e-containing layer, a conductor electrically connected to the source or drain region having the Ge-containing layer, a source or drain region having the Ge-containing layer, and an interface between the conductors Since the titanium silicide layer is formed at the time of formation, uneven silicidation and excessive silicidation can be prevented, and as a result, a titanium silicide layer having good flatness can be formed, Good contact characteristics between the source or drain region having the Ge-containing layer and the conductor can be obtained.
Also, since local aggregation of the titanium silicide layer does not occur,
The depth of the junction between the source and drain regions can be reduced, and good electrical characteristics can be obtained even when the MOS field-effect transistor is miniaturized.

In addition, the semiconductor device is provided with a wiring formed on a semiconductor substrate, and the wiring includes a silicon layer having a Ge-containing layer near the surface and a titanium silicide layer formed on the silicon layer. Therefore, at the time of its formation,
Non-uniform silicidation and excessive silicidation can be prevented, and as a result, a titanium silicide layer having good flatness can be formed, and an exposure margin and the like in a photolithography process on the upper layer of the wiring can be easily secured. In addition, since local aggregation of the titanium silicide layer does not occur, variation in the resistance value in the wiring can be suppressed, and electric field concentration and the like can be prevented.
The reliability of wiring can be improved. Further, there is an effect that an increase in the resistance value of the entire wiring can be suppressed.

A method for manufacturing a semiconductor device according to the present invention
In a method for manufacturing a semiconductor device having a MOS field-effect transistor formed on one main surface of a silicon substrate,
Forming source and drain regions on the main surface of the silicon substrate; and ion-implanting Ge into at least one of the source and drain regions to form a Ge near the surface thereof.
Forming a Ti-containing layer, and depositing Ti on the source or drain region where the Ge-containing layer is formed;
Reacting the deposited Ti and Si in the source or drain region on which the Ge-containing layer is formed to form a titanium silicide layer on the source or drain region; and a main surface of the silicon substrate. Forming an interlayer insulating film having a connection hole opened in the titanium silicide layer thereon, and forming a conductive layer electrically connected to the source or drain region on which the Ge-containing layer is formed through the connection hole. And a step of forming a body, whereby non-uniform silicidation and excessive silicidation can be prevented, as a result, a titanium silicide layer having good flatness can be formed, and the source or drain having the Ge-containing layer can be formed. Good contact characteristics between the region and the conductor can be obtained. In addition, since local aggregation of the titanium silicide layer does not occur, the depth of the junction between the source and drain regions can be reduced, and even when the MOS field-effect transistor is miniaturized, good results can be obtained. Electric characteristics can be obtained.

Further, the semiconductor device is formed on one main surface of the silicon substrate.
In a method of manufacturing a semiconductor device having a MOS field-effect transistor, a step of forming source and drain regions on a main surface of the silicon substrate; and forming at least one of the source and drain regions on the main surface of the silicon substrate. Forming an interlayer insulating film having a connection hole that opens, and implanting Ge using the connection hole as a mask to form a Ge-containing layer near the surface of the source or drain region where the connection hole opens, Depositing Ti on the source or drain region where the connection hole is opened, and reacting the deposited Ti and Si in the source or drain region where the Ge-containing layer is formed, thereby forming the source or drain. Forming a titanium silicide layer on the region and, via the connection hole, the source or drain region where the Ge-containing layer is formed. A step of forming an electrically connected conductor can be prevented, so that non-uniform silicidation or excessive silicidation can be prevented. As a result, a titanium silicide layer having good flatness can be formed. Good contact characteristics between the source or drain region having the containing layer and the conductor can be obtained. In addition, since local aggregation of the titanium silicide layer does not occur, the depth of the junction between the source and drain regions can be reduced, and even when the MOS field-effect transistor is miniaturized, good results can be obtained. Electric characteristics can be obtained.

In a method of manufacturing a semiconductor device having a wiring formed on a semiconductor substrate, a step of forming a silicon layer on the semiconductor substrate and a step of ion-implanting Ge into the silicon layer, Forming a Ge-containing layer near the surface, depositing Ti on the silicon layer, depositing Ti and S in the silicon layer.
reacting i to form a titanium silicide layer on the silicon layer; and patterning the silicon layer and the titanium silicide layer to form a wiring.
Non-uniform silicidation and excessive silicidation can be prevented, and as a result, a titanium silicide layer having good flatness can be formed, and an exposure margin and the like in a photolithography process on the upper layer of the wiring can be easily secured. In addition, since local aggregation of the titanium silicide layer does not occur, variation in the resistance value in the wiring can be suppressed, electric field concentration and the like can be prevented, and therefore, the reliability of the wiring can be improved. Further, there is an effect that an increase in the resistance value of the entire wiring can be suppressed.

In a method of manufacturing a semiconductor device having a wiring formed on a semiconductor substrate, a step of forming a wiring-shaped silicon layer on the semiconductor substrate, and Ge ion implantation into the silicon layer, Forming a Ge-containing layer near the surface of the silicon layer;
And forming a wiring by reacting the deposited Ti and Si in the silicon layer to form a titanium silicide layer on the silicon layer. Uniform silicidation or excessive silicidation can be prevented, and as a result, a titanium silicide layer having good flatness can be formed, and an exposure margin or the like in a photolithography process in the upper layer of the wiring can be easily secured. Further, since local aggregation of the titanium silicide layer does not occur, variation in the resistance value in the wiring can be suppressed, electric field concentration and the like can be prevented,
Therefore, the reliability of the wiring can be improved. Further, there is an effect that an increase in the resistance value of the entire wiring can be suppressed.

[Brief description of the drawings]

FIG. 1 is a fragmentary cross-sectional view showing a structure of a semiconductor device according to a first embodiment of the present invention;

FIG. 2 is a fragmentary cross-sectional view showing a method of manufacturing the semiconductor device in the first embodiment of the present invention in the order of steps;

FIG. 3 is a fragmentary cross-sectional view showing the method of manufacturing the semiconductor device in the first embodiment of the present invention in the order of steps.

FIG. 4 is a fragmentary cross-sectional view showing a structure of a semiconductor device according to a second embodiment of the present invention;

FIG. 5 is an essential part cross sectional view showing the manufacturing method of the semiconductor device in the second embodiment of the present invention in the order of steps;

FIG. 6 is an essential part cross sectional view showing the manufacturing method of the semiconductor device in the second embodiment of the present invention in the order of steps;

FIG. 7 is a fragmentary cross-sectional view showing a structure of a semiconductor device according to a third embodiment of the present invention;

FIG. 8 is an essential part cross sectional view showing the manufacturing method of the semiconductor device in the third embodiment of the present invention in the order of steps;

FIG. 9 is a fragmentary cross-sectional view showing a method of manufacturing a semiconductor device having a metal silicide film formed by a conventional silicidation technique in a contact portion in the order of steps of the method;

[Explanation of symbols]

1 silicon substrate, 4a silicon layer, 4b
Ge-containing layer, 4c titanium silicide layer, 5 drain region, 6 source region, 8 Ge-containing layer,
9 titanium silicide layer, 10a Ti, 13 interlayer insulating film, 13a connection hole, 14 conductor, 1
5, 16 MOS field-effect transistor, 17, 18
Wiring, 100 semiconductor substrate, 180 silicon layer, 181 Ge containing layer, 182 titanium silicide layer.

Claims (7)

[Claims] 1. A silicon substrate having a Ge-containing layer near the surface, a conductor electrically connected to the silicon substrate, and a titanium silicide layer formed at an interface between the silicon substrate and the conductor. Equipped semiconductor device. 2. A method according to claim 1, further comprising: forming a Ge on one main surface of the silicon substrate, and forming a Ge near a surface of at least one of the source and drain regions.
A MOS field-effect transistor having a Ge-containing layer, a conductor electrically connected to the source or drain region having the Ge-containing layer, a source or drain region having the Ge-containing layer, and an interface between the conductors. A semiconductor device comprising the formed titanium silicide layer. 3. A wiring provided on a semiconductor substrate, wherein the wiring includes a silicon layer having a Ge-containing layer near a surface, and a titanium silicide layer formed on the silicon layer. Semiconductor device. 4. A method according to claim 1, wherein the M is formed on one main surface of a silicon substrate.
In a method for manufacturing a semiconductor device having an OS field-effect transistor, a step of forming a source and a drain region on a main surface of the silicon substrate; and a step of ion-implanting Ge into at least one of the source and drain regions to form a surface thereof. Forming a Ge-containing layer in the vicinity; depositing Ti on the source or drain region on which the Ge-containing layer has been formed; and depositing Ti on the source or drain on which the Ge-containing layer has been formed. Reacting Si in the drain region to form a titanium silicide layer on the source or drain region; and inter-layer insulation having a connection hole opened in the titanium silicide layer on the main surface of the silicon substrate. Forming a film, and forming a conductor electrically connected to the source or drain region where the Ge-containing layer is formed through the connection hole. The method of manufacturing a semiconductor device including the step. 5. A method according to claim 1, wherein the M substrate is formed on one main surface of a silicon substrate.
In a method for manufacturing a semiconductor device having an OS field-effect transistor, a step of forming a source and a drain region on a main surface of the silicon substrate; and a step of forming at least one of the source and drain regions on the main surface of the silicon substrate. Forming an interlayer insulating film having a connection hole that opens; and ion-implanting Ge using the connection hole as a mask, and forming G near the surface of the source or drain region where the connection hole opens.
forming an e-containing layer; and forming Ti on the source or drain region where the connection hole is opened.
Depositing Ti, and reacting the deposited Ti and Si in the source or drain region where the Ge-containing layer is formed to form a titanium silicide layer on the source or drain region. Forming a conductor electrically connected to the source or drain region where the Ge-containing layer is formed through the connection hole. 6. A method for manufacturing a semiconductor device provided with wiring formed on a semiconductor substrate, comprising: forming a silicon layer on the semiconductor substrate; ion-implanting Ge into the silicon layer; Forming a Ge-containing layer near the surface; depositing Ti on the silicon layer; reacting the deposited Ti and Si in the silicon layer to form titanium silicide on the silicon layer. A method for manufacturing a semiconductor device, comprising: forming a layer; and patterning the silicon layer and the titanium silicide layer to form a wiring. 7. A method of manufacturing a semiconductor device having a wiring formed on a semiconductor substrate, comprising: forming a wiring-shaped silicon layer on the semiconductor substrate; and ion-implanting Ge into the silicon layer. Forming a Ge-containing layer near the surface of the silicon layer, depositing Ti on the silicon layer, reacting the deposited Ti and Si in the silicon layer, Forming a wiring by forming a titanium silicide layer.