JP3061027B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a MOS (Meta)
The present invention relates to a semiconductor device using an l-oxide-semiconductor (FET) type field effect transistor and a method of manufacturing the same.

[0002]

2. Description of the Related Art Conventionally, MOSFETs (field effect transistors) have used a structure in which a silicide film is formed on a gate electrode in order to reduce the resistance of the gate electrode. However, as the size of a device (element) has been reduced, the resistance of the gate electrode has been required to be lower. For this reason, adoption of a metal model having a lower resistance than the silicide film is being studied.

However, a metal film and a polycrystalline silicon film have
In the layered structure, a silicidation reaction occurs between the metal film and the polycrystalline silicon film during the heat treatment, making it impossible to maintain the effect of reducing the resistance by the metal film. Therefore, a laminated structure in which a barrier layer is formed between a metal film and a polysilicon film has been proposed. (JP-A-1-303759; 1)
995, IEEE-Transactions on Electron Devices,
Vol. 42, No. 5, pp. 915-922, May 31, 1995; 1993, Technical Digest of International Electron Devices Conference, pp. 325-328, 19
December 6, 1993; 1993, Technical Digest of International Electron Devices Conference, pp. 329-332, December 6, 1993)

[0004]

However, there is a disadvantage that the metal film is deteriorated by the heat treatment step or the substrate cleaning step after the gate electrode is formed, and the film is peeled off. In addition, there is a problem that the resistance value of the metal film increases due to the deterioration of the metal film.

The present invention has been made under such a background, and the heat treatment process and the substrate cleaning process after the formation of the gate electrode do not cause the metal film to be degraded, causing film peeling and increasing the resistance value of the metal film. It is an object to provide a semiconductor device and a method of manufacturing the semiconductor device. In particular, the present invention is effective for a MOS field effect transistor having a gate length of 0.25 μm or less in design rules.

[0006]

[0007]

[0008]

According to the first aspect of the present invention,
In a method of manufacturing a semiconductor device, an element isolation region forming step of forming an element isolation region for dividing an element formation region for forming an element on a semiconductor substrate in a plane direction, and forming a gate oxide film on a surface of the element formation region Forming an oxide film to be formed, forming a polycrystalline silicon layer on the surface of the gate oxide film, forming a barrier layer on the surface of the polycrystalline silicon layer, and forming an upper surface of the barrier layer. A metal film forming step of forming a metal film, and a gate electrode forming step of forming a gate electrode by etching a stacked structure including the gate oxide film, the polycrystalline silicon layer, the barrier layer and the metal film, An ion implantation step of ion-implanting nitrogen atoms into the gate electrode from a direction having a predetermined angle with respect to the upper surface of the gate electrode; And having a source and drain formation step for forming a source region and a drain region in the child formation region.

According to a second aspect of the present invention, in the method of manufacturing a semiconductor device, an element isolation region forming step of forming an element isolation region for partitioning an element formation region for forming an element on a semiconductor substrate in a plane direction; An oxide film forming step of forming a gate oxide film on the surface of the element formation region; a polycrystalline silicon forming step of forming a polycrystalline silicon layer on the gate oxide film surface; and forming a barrier layer on the surface of the polycrystalline silicon layer. Forming a barrier film, forming a metal film on the upper surface of the barrier layer, forming a silicon nitride film on the upper surface of the metal film by a chemical vapor deposition method, A gate electrode forming step of etching a film, the polycrystalline silicon layer, the barrier layer, the stacked structure including the metal film and the silicon nitride film to form a gate electrode; An ion implantation step of ion-implanting nitrogen atoms into the gate electrode from a direction having a predetermined angle with respect to the upper surface of the gate electrode, and a source / drain for forming a source region and a drain region in the element formation region in alignment with the gate electrode And a forming step.

According to a third aspect of the present invention, in the method of manufacturing a semiconductor device according to the first or second aspect, a metal nitride film is used as the barrier film. According to a fourth aspect of the present invention, in the method of manufacturing a semiconductor device according to the first or second aspect, a nitride insulating film is used as the barrier film.

[0011]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a sectional view showing a structure of a semiconductor device according to one embodiment of the present invention. In this figure, reference numeral 1 denotes a silicon substrate on which elements of a semiconductor circuit are formed. An element isolation film 2 separates the element formation region 42 from an element formation region (not shown).

Reference numeral 3 denotes a gate oxide film, which electrically insulates the semiconductor substrate 1 from the polycrystalline silicon 4. 51 is 2
A metal nitride film having a thickness of 10 to 10 nm prevents silicidation of the polycrystalline silicon 4 and the metal film 61 in the heat treatment step. Here, the metal nitride film 51 is formed of a titanium nitride film or a tantalum nitride film and has a thickness of 2 to 20 nm.

Reference numeral 91 denotes a metal nitride film which is formed on the metal film 61. Reference numeral 6 denotes a gate electrode side wall film, which is formed of a gate oxide film 3, polycrystalline silicon 4, a metal nitride film 51, a metal film 61 and a metal nitride film 91.
1 is formed on the side wall. Reference numeral 8 denotes a diffusion layer, which becomes a source region and a drain region.

Next, an application example according to an embodiment of the present invention will be described with reference to FIG. Here, the gate electrode 41 has a gate length of 0.25 μm. The gate electrode 41 is
A polycrystalline silicon film 4 having a thickness of 0 nm, a titanium nitride film 51 having a thickness of 4 nm, and a tungsten film 61 having a thickness of 50 nm
Are formed. Also, the tungsten film 6
Reference numeral 1 denotes a surface of a tungsten nitride film 91 having a thickness of 5 nm.
Covered with.

Here, the polycrystalline silicon film 4 is a polycrystalline silicon film formed by a CVD method. The titanium nitride film 51 as an intermediate layer is formed by a reactive sputtering method. Further, the upper tungsten film 61 is a film formed by a sputtering method, and has a surface portion formed as a tungsten nitride film 91 by ion implantation of nitrogen atoms.

Due to this laminated structure, a heat treatment temperature of 900 ° C.
In this case, the tungsten film 51 was protected by the tungsten nitride film 91 and was not oxidized. Further, silicidation at the interface between the tungsten film 61 and the polycrystalline silicon film 4 does not occur due to the titanium nitride film 51 as the intermediate layer. As a result, there is an effect that the low resistance of the tungsten film 61 can be maintained. Also, here, a similar result can be obtained by using a silicon nitride film instead of the tungsten nitride film.

Next, a manufacturing method according to an embodiment will be described with reference to FIG. FIG. 2 is a cross-sectional view of a semiconductor device illustrating a flow of a manufacturing process according to one embodiment. First, FIG.
1A, an element isolation region 2 is formed on a surface of a silicon semiconductor substrate 1 by an oxidation process. Then, a gate oxide film 3 is formed on the upper surface of the element formation region 21.
Further, a polycrystalline silicon film 4 is formed on the upper surface of the gate oxide film 3.
Is formed by CVD (chemical vapor deposition).

Then, a metal nitride film 51 having a thickness of 2 to 20 nm is deposited on the upper surface of the polycrystalline silicon film 4. Further, a tungsten film 61, which is a high melting point metal, is formed on the upper surface of the metal nitride film 51 by sputtering.
It is formed with a thickness of 0 to 100 nm.

Next, in FIG. 2B, a mask layer (not shown) used for patterning in a normal lithography step is formed. Then, in the etching step using this mask layer, the laminated polycrystalline silicon film 4, metal nitride film 51, and tungsten film 61 are processed by etching to form gate electrode 41. Then, nitrogen atoms are ion-implanted into the gate electrode 41 from an oblique direction, so that the surface portion of the tungsten film 61 having a thickness of 2 to 5 nm becomes the tungsten nitride film 91.

Next, in FIG. 2C, the gate electrode 4
A gate electrode sidewall film 6 is formed on one side surface. And
Gate electrode 41 and element formation region 2 of silicon substrate 1
Arsenic atoms or BF ₂ are ion-implanted into 1. Thereby, the diffusion layer 8 is formed. As a result, MOSF
ET is completed.

Next, an example of a process to which the manufacturing method of one embodiment is applied will be described with reference to FIG. First, in FIG. 2A, an element isolation region 2 is formed on the surface of a silicon semiconductor substrate 1 by LOCOS (Local Oxidation of).
(Silicon) method. Then, a gate oxide film 3 having a thickness of 5 nm is formed on the upper surface of the element formation region 21 by a thermal oxidation method. Further, a polycrystalline silicon film 4 having a thickness of 180 nm is formed on the upper surface of the gate oxide film 3 by a low pressure CVD method.

Then, a 4 nm-thick titanium nitride film 51 is deposited on the upper surface of the polycrystalline silicon film 4 by a reactive sputtering method. Further, on the upper surface of the titanium nitride film 51, a tungsten film 61 of a high melting point metal is formed with a thickness of 50 nm by a sputtering method.

Next, in FIG. 2B, a mask layer (not shown) used for patterning in a normal lithography step is formed. Then, in the etching process using this mask layer, the laminated polycrystalline silicon film 4, titanium nitride film 51 and tungsten film 61 are formed.
Is etched to form a gate electrode 41 having a gate length of 0.25 μm. Then, nitrogen ions are implanted into the gate electrode 41 obliquely at a dose of 1 × 10 ¹⁵ cm ⁻² , thereby forming the tungsten film 61.
The surface portion having a thickness of 5 nm is formed as a tungsten nitride film 91.

Next, in FIG. 2C, the gate electrode 4
An insulating film (SiO ₂ ) side wall 6 is formed on one side surface. Then, 3 × 10 ¹⁵ c is applied to the gate electrode 41 and the element formation region 21 of the silicon substrate 1 with the energy of 20 keV.
including BF ₂ dose of arsenic atom or a dose of 3 × 10 ¹⁵ cm ^-2 by the energy of 10keV of m ^-2 is ion-implanted. Then, the diffusion layer 8 is formed by the subsequent heat treatment. As a result, the MOSFET is completed.

As described above, one embodiment of the present invention has been described in detail with reference to the drawings. However, the specific configuration is not limited to this embodiment, and the configuration may be changed without departing from the gist of the present invention. The present invention is also included in the present invention. For example, FIG.
Having a sectional structure according to the second embodiment shown in FIG.
ET is also included in the present invention.

FIG. 3 is a sectional view showing the structure of the semiconductor device according to one embodiment of the present invention. In this figure, reference numeral 1 denotes a silicon substrate on which elements of a semiconductor circuit are formed. An element isolation film 20 separates the element formation region 22 from an element formation region (not shown).

Reference numeral 13 denotes a gate oxide film, and the semiconductor substrate 1
And polycrystalline silicon 4 are electrically insulated. Reference numeral 52 denotes a silicon nitride film which prevents silicidation of the polycrystalline silicon 4 and the molybdenum film 62 in a heat treatment step. Here, the molybdenum film 62 has a thickness of 2 to 10 nm.
Is covered with the molybdenum nitride film 92 and the silicon nitride film 10.

Here, the silicon nitride film 5 of the intermediate barrier layer
Reference numeral 2 denotes a thin film to which a leak current flows, and a thickness of about 1 to 10 nm which does not cause a silicidation reaction at an interface between the polycrystalline silicon 4 and the molybdenum film 62 due to the heat treatment. Reference numeral 17 denotes a gate electrode side wall film, which includes a gate oxide film 13, polycrystalline silicon 4, and a silicon nitride film 5.
2. It is formed on the side wall of the gate electrode formed of the molybdenum film 62 and the tungsten nitride film 91. Reference numeral 18 denotes a diffusion layer, which becomes a source region and a drain region.

Next, an application example according to the second embodiment of the present invention will be described with reference to FIG. Here, the gate electrode 41
Has a gate length of 0.12 μm. Gate electrode 42
Is formed with a laminated structure of a polycrystalline silicon film 4 having a thickness of 150 nm, a silicon nitride film 52 having a thickness of 2 nm, and a molybdenum film 62 having a thickness of 40 nm. The surface of the molybdenum film 62 is covered with the silicon nitride film 10 having a thickness of 10 nm.

Further, the side surfaces of the molybdenum film 62 are covered with a molybdenum nitride film 92. Here, the polycrystalline silicon film 4 is a polycrystalline silicon film formed by a CVD method. The silicon nitride film 52 as an intermediate layer is formed by nitriding the surface of the polycrystalline silicon film 4 by a rapid heat treatment method in an ammonia gas atmosphere. Further, the upper molybdenum film 62 is a film formed by a sputtering method.

Due to this laminated structure, a heat treatment temperature of 900 ° C.
Also, the molybdenum film 62 was protected by the silicon nitride film 10 and the molybdenum nitride film 92 and was not oxidized. Further, silicidation at the interface between the molybdenum film 62 and the polycrystalline silicon film 4 does not occur due to the silicon nitride film 52 as the intermediate layer. As a result, there is an effect that the low resistance of the molybdenum film 62 can be maintained. Here, the same result can be obtained by using a molybdenum nitride film instead of the silicon nitride film 10.

Next, a manufacturing method according to the second embodiment will be described with reference to FIG. FIG. 4 is a cross-sectional view of a semiconductor device illustrating a flow of a manufacturing process according to the second embodiment. First, in FIG. 4A, an element isolation region 20 is formed on the surface of the silicon semiconductor substrate 1. Then, a gate oxide film 13 is formed on the upper surface of the element formation region 22. Further, a polycrystalline silicon film 4 is formed on the gate oxide film 13 by CVD (chemical vapor deposition).

Then, a silicon nitride film 52 having a thickness of 1 to 10 nm is formed on the upper surface of the polycrystalline silicon film 4 at 0.degree.
It is deposited by a reactive sputtering method on the following substrate holder. Further, a high melting point metal film 62 is formed on the upper surface of the silicon nitride film 52 by sputtering.
It is formed with a thickness of 80 nm. The silicon nitride film 10 is formed on the high melting point metal film 62 to a thickness of 2 to 10 nm.

Next, in FIG. 4B, a mask layer (not shown) used for patterning in a normal lithography step is formed. Then, in the etching step using this mask layer, the laminated polycrystalline silicon film 4, silicon nitride film 52 and refractory metal film 62
Is processed by etching to form a gate electrode 42. Then, by ion-implanting nitrogen atoms into the gate electrode 42 from an oblique direction, a metal nitride film 92 having a thickness of 2 to 5 nm is formed on the side surface of the refractory metal film 62.

Next, referring to FIG.
The gate electrode side wall film 17 is formed on the side surface of the gate electrode 2. Then, arsenic atoms or BF ₂ is ion-implanted into the gate electrode 42 and the element formation region 22 of the silicon substrate 1. Thereby, the diffusion layer 18 is formed. As a result,
The MOSFET is completed.

Next, an example of a process to which the manufacturing method of the second embodiment is applied will be described with reference to FIG. First, in FIG. 4A, an element isolation region 20 is formed on the surface of the silicon semiconductor substrate 1 by a normal trench method. Then, a gate oxide film 13 having a thickness of 4 nm is formed on the upper surface of the element formation region 22 by a thermal oxidation method. Further, a polycrystalline silicon film 4 having a thickness of 180 nm is formed on the upper surface of the gate oxide film 13 by a low pressure CVD method.

Then, a silicon nitride film 52 having a thickness of 2 nm is deposited on the upper surface of the polycrystalline silicon film 4 by a reactive sputtering method. Further, the silicon nitride film 5
On the upper surface 2, a molybdenum film 62, which is a high melting point metal, is deposited by sputtering to a thickness of 50 nm by sputtering.

Next, in FIG. 4B, a mask layer (not shown) used for patterning in a normal lithography step is formed. Then, in the etching step using this mask layer, the laminated polycrystalline silicon film 4, silicon nitride film 52 and molybdenum film 62
Is etched to form a gate electrode 42 having a gate length of 0.2 μm. And this gate electrode 4
2 × 10 ¹⁵ cm ^{-2 of} nitrogen atoms from oblique direction at 30 degrees
By implanting ions at a dose amount of 5 nm, the 5 nm-thick side surface of the molybdenum film 62 becomes a molybdenum nitride film 92.

Next, referring to FIG.
An insulating film (SiO ₂ ) side wall 17 is formed on the side surface of the _second .
Then, arsenic atoms or BF ₂ is ion-implanted into the gate electrode 42 and the element formation region 22 of the silicon substrate 1. Then, the diffusion layer 18 is formed by the subsequent heat treatment. As a result, the MOSFET is completed.

Next, a manufacturing method of the third embodiment will be described with reference to FIG. FIG. 5 is a cross-sectional view of a semiconductor device illustrating a flow of a manufacturing process according to the third embodiment. First, in FIG. 5A, an element isolation region 20 is formed on the surface of the silicon semiconductor substrate 1. Then, a gate insulating film 83 is formed on the upper surface of the element formation region 28. Further, a polycrystalline silicon film 4 is formed on the upper surface of the gate insulating film 83 by CVD (chemical vapor deposition).

Then, a silicon nitride film 11 having a thickness of 1 to 10 nm is deposited on the upper surface of the polycrystalline silicon film 4 by a rapid heat treatment method. Further, on the upper surface of the silicon nitride film 11, a high melting point metal film 62 is formed with a thickness of 30 to 100 nm by a sputtering method.

Next, in FIG. 5B, a mask layer (not shown) used for patterning in a normal lithography process is formed. Then, in the etching step using this mask layer, the stacked polycrystalline silicon film 4, silicon nitride film 11, and high melting point metal film 62 are formed.
Is processed by etching to form a gate electrode 43. Then, by ion-implanting nitrogen atoms into the gate electrode 43 from an oblique direction, a metal nitride film 92 having a thickness of 2 to 5 nm is formed on the surface and side surfaces of the refractory metal film 62.

Next, in FIG. 5C, the gate electrode 4
The gate electrode side wall film 17 is formed on the side surface 3. Then, arsenic atoms or BF ₂ are ion-implanted into the gate electrode 43 and the element formation region 28 of the silicon substrate 1. Thereby, the diffusion layer 18 is formed. As a result,
The MOSFET is completed.

Next, an example of a process to which the manufacturing method of the third embodiment is applied will be described with reference to FIG. First, in FIG. 5A, an element isolation region 20 is formed on the surface of the silicon semiconductor substrate 1 by a normal trench method. Then, a gate oxynitride film 83 having a thickness of 3 nm is formed on the upper surface of the element formation region 28 by a thermal oxynitride method. Further, a polycrystalline silicon film 4 having a thickness of 150 nm is formed on the upper surface of the gate nitrided oxide film 83 by a low pressure CVD method.

Then, a silicon nitride film 11 having a thickness of 2 nm is deposited on the upper surface of the polycrystalline silicon film 4 by a rapid heat treatment in an ammonia gas atmosphere. further,
On the upper surface of the silicon nitride film 11, a molybdenum film 62, which is a refractory metal, is deposited to a thickness of 40 nm by a sputtering method.

Next, in FIG. 5B, a mask layer (not shown) used for patterning in a normal lithography process is formed. Then, in the etching step using this mask layer, the stacked polycrystalline silicon film 4, silicon nitride film 11, and molybdenum film 62 are formed.
Is etched to form a gate electrode 43 having a gate length of 0.12 μm. Then, 5 × 10 ¹⁴ cm of nitrogen atoms are applied to the gate electrode 43 from an oblique direction of 35 degrees.
^{By performing} ion implantation at a dose of ⁻² , the surface and side surfaces of the molybdenum film 62 having a thickness of 3 nm become the molybdenum nitride film 92.

Next, in FIG. 5C, the gate electrode 4
An insulating film (SiO ₂ ) side wall 17 is formed on the side surface of No. 3.
Then, arsenic atoms or BF ₂ are ion-implanted into the gate electrode 43 and the element formation region 28 of the silicon substrate 1. Then, the diffusion layer 18 is formed by the subsequent heat treatment. As a result, the MOSFET is completed.

Next, a manufacturing method according to the fourth embodiment will be described with reference to FIG. FIG. 6 is a cross-sectional view of a semiconductor device illustrating a flow of a manufacturing process according to the fourth embodiment. First, in FIG. 6A, an element isolation region 20 is formed on the surface of the silicon semiconductor substrate 1. Then, a gate insulating film 33 is formed on the upper surface of the element formation region 24. Further, a polycrystalline silicon film 4 is formed on the upper surface of the gate insulating film 33 by low-pressure CVD (chemical vapor deposition).

Then, a silicon nitride film 11 having a thickness of 1 to 10 nm is deposited on the upper surface of the polycrystalline silicon film 4 by a rapid heat treatment method. Further, on the upper surface of the silicon nitride film 11, a high melting point metal film 62 is formed with a thickness of 30 to 100 nm by a sputtering method. The silicon nitride film 10 has a CV on the high melting point metal film 62.
It is formed by Method D.

Next, in FIG. 6B, a mask layer (not shown) used for patterning in a normal lithography step is formed. Then, in the etching step using this mask layer, the stacked polycrystalline silicon film 4, silicon nitride film 11, and high melting point metal film 62 are formed.
Is processed by etching to form a gate electrode 44. Then, by ion-implanting nitrogen atoms into the gate electrode 44 from an oblique direction, a metal nitride film 92 having a thickness of 2 to 5 nm is formed on the surface and side surfaces of the refractory metal film 62.

Next, in FIG. 6C, the gate electrode 4
The gate electrode side wall film 17 is formed on the side surface of the gate electrode 4. Then, arsenic atoms or BF ₂ is ion-implanted into the gate electrode 44 and the element formation region 24 of the silicon substrate 1. Thereby, the diffusion layer 18 is formed. As a result,
The MOSFET is completed.

Next, an example of a process to which the manufacturing method of one embodiment is applied will be described with reference to FIG. First, in FIG. 6A, an element isolation region 20 is formed on the surface of the silicon semiconductor substrate 1.
Is formed by a normal trench method. Then, a gate oxynitride film 33 having a thickness of 3 nm is formed on the upper surface of the element formation region 24 by a thermal oxynitride method. Further, a polycrystalline silicon film 4 having a thickness of 150 nm is formed on the upper surface of the gate oxynitride film 33 by a low pressure CVD method.

Then, a silicon nitride film 11 having a thickness of 2 nm is deposited on the upper surface of the polycrystalline silicon film 4 by a rapid heat treatment in an ammonia gas atmosphere. further,
On the upper surface of the silicon nitride film 11, a molybdenum film 62, which is a refractory metal, is deposited to a thickness of 40 nm by a sputtering method. A silicon nitride film 10 is formed on the molybdenum film 62 by CVD.
Is formed with a thickness of 10 nm.

Next, in FIG. 6B, a mask layer (not shown) used for patterning in a normal lithography process is formed. Then, in the etching step using this mask layer, the stacked polycrystalline silicon film 4, silicon nitride film 11, and molybdenum film 62 are formed.
Is processed by etching to form a gate electrode 44 having a gate length of 0.1 μm. And this gate electrode 4
4 × 5 ¹⁴ cm ^{−2 of} nitrogen atoms from an oblique direction of 35 degrees
By implanting ions at a dose amount of 3 m, the side portion of the molybdenum film 62 having a thickness of 3 nm is formed into a molybdenum nitride film 92.

Next, in FIG. 6C, the gate electrode 4
An insulating film (SiO ₂ ) side wall 17 is formed on the side surface of the substrate 4.
Then, the gate electrode 44 and the element formation region 24 of the silicon substrate 1 are arsenic atoms at an energy of 7 keV and a dose of 2 × 10 ¹⁵ cm ⁻² or 2 × 1 at an energy of 4 keV.
BF ₂ or the like is ion-implanted at a dose of 0 ¹⁵ cm ⁻² . Then, the diffusion layer 18 is formed by the subsequent heat treatment. As a result, the MOSFET is completed.

As described above, the structure of the semiconductor device according to the present invention is based on the experimental results of the surface oxidation in the heat treatment of the metal film and the effect of preventing the surface oxidation by forming the nitride film on the metal film surface. Generally, a high-melting point metal film is oxidized in a heat treatment step or an oxidation step in a semiconductor manufacturing process, and the electrical resistivity increases. Therefore, after a metal film is deposited, a high-temperature heat treatment step is performed on a semiconductor device. I couldn't do that.

On the other hand, according to the present invention, by forming a metal nitride or silicon nitride film on the surface of the metal film, it is possible to prevent oxidation of the metal film during heat treatment, and to prevent film peeling and increase in electric resistance. . FIG. 7 shows the relationship between the thickness of the nitride film deposited on the surface and the change in the electrical resistivity after the heat treatment.

As can be seen from FIG. 7, when the thickness of the surface nitride film (metal nitride or silicon nitride film) is 2 nm or more, an increase in electric resistance does not occur. However, when the thickness of the surface nitride film is less than 2 nm, the electric resistance increases. Thus, by forming a surface nitride film of 2 nm or more on the metal surface, oxidation of the metal film of the gate electrode can be prevented, and a gate electrode having heat resistance can be formed.

[0059]

According to the present invention, an amorphous film is used as an intermediate barrier layer of a gate electrode, and a film for preventing oxidation of the metal film is formed on the upper surface of the metal film of the gate electrode. Heat treatment can be performed without oxidizing the surface of the film, crystal grains of the metal film can be enlarged, and the electrical conductivity of the metal film can be improved.

Further, according to the present invention, an amorphous insulating film or an amorphous conductor film is interposed between a silicon film forming a gate electrode and a metal film, so that a heat treatment between the silicon film and the metal film can be performed. Since silicidation can be prevented, there is an effect that heat treatment after forming a metal film can be performed without causing deterioration of the gate electrode such as film peeling and increase in metal resistance.

[Brief description of the drawings]

FIG. 1 is a longitudinal sectional view showing a configuration of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a longitudinal sectional view of the semiconductor device, illustrating a process of manufacturing the semiconductor device according to the embodiment of the present invention;

FIG. 3 is a longitudinal sectional view illustrating a configuration of a semiconductor device according to a second embodiment of the present invention.

FIG. 4 is a longitudinal sectional view of the semiconductor device, showing a manufacturing process of the semiconductor device according to the second embodiment of the present invention;

FIG. 5 is a vertical sectional view of the semiconductor device, showing a manufacturing process of the semiconductor device according to the third embodiment of the present invention.

FIG. 6 is a vertical sectional view of the semiconductor device, showing a manufacturing process of the semiconductor device according to the fourth embodiment of the present invention.

FIG. 7 is a diagram showing the relationship between the thickness of a nitride film deposited on the surface and the change in electrical resistivity after heat treatment.

[Explanation of symbols]

Reference Signs List 1 semiconductor substrate (silicon substrate) 2, 20 element isolation oxide film 3, 13, 23, 33 gate oxide film (gate insulating film) 4 polycrystalline silicon film 6, 17 gate electrode side wall film 8, 18 diffusion layer 10, 11, Reference Signs List 52 silicon nitride film 21, 22, 24, 28 element formation region 41, 42, 43, 44 gate electrode 51 metal nitride film (tungsten nitride film, titanium nitride film, tantalum nitride film) 61 tungsten film (high melting point metal film) 62 Molybdenum film (refractory metal film) 83 Gate nitrided oxide film (gate insulating film) 91 Tungsten nitride film (metal nitride film) 92 Molybdenum nitride film (metal nitride film)

Continuation of the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 29/78 H01L 21/28 301 H01L 21/3205 H01L 29/43

Claims (4)

(57) [Claims] An element isolation region forming a device isolation region for forming an element on a semiconductor substrate in a plane direction; and forming a gate oxide film on a surface of the element formation region. An oxide film forming step; a polycrystalline silicon forming step of forming a polycrystalline silicon layer on the surface of the gate oxide film; a barrier layer forming step of forming a barrier layer on the surface of the polycrystalline silicon layer; A metal film forming step of forming a film, and etching a gate oxide film, the polycrystalline silicon layer, a stacked structure including the barrier layer and the metal film,
A gate electrode forming step of forming a gate electrode, an ion implantation step of ion-implanting nitrogen atoms into the gate electrode from a direction having a predetermined angle with respect to the upper surface of the gate electrode, A source / drain forming step of forming a source region and a drain region. 2. An element isolation region forming step of forming an element isolation region for dividing an element formation region for forming an element on a semiconductor substrate in a plane direction, and forming a gate oxide film on a surface of the element formation region. An oxide film forming step; a polycrystalline silicon forming step of forming a polycrystalline silicon layer on the surface of the gate oxide film; a barrier layer forming step of forming a barrier layer on the surface of the polycrystalline silicon layer; A metal film forming step of forming a film, a nitride film forming step of forming a silicon nitride film on the upper surface of the metal film by a chemical vapor deposition method, the gate oxide film, the polycrystalline silicon layer, the barrier layer, A gate electrode forming step of forming a gate electrode by etching a laminated structure composed of a metal film and a silicon nitride film; And a source / drain forming step of forming a source region and a drain region in the element forming region in alignment with the gate electrode. Manufacturing method. 3. A method according to claim 1 or claim 2, wherein the use of metal nitride film as the barrier film. 4. A method according to claim 1 or claim 2, wherein the use of nitride insulating film as the barrier film.