JPS5814750B2 - Manufacturing method of semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for manufacturing a semiconductor device having a multilayer wiring structure including electrode wiring made of a high melting point metal silicide.

Conventionally, Al and polycrystalline silicon have been widely used for electrode wiring of semiconductor devices.

Al is most commonly used because it has a low resistivity and good contact with the silicon substrate, but its low melting point means that it can only be used after all high-temperature treatment steps have been completed.

Therefore, polycrystalline silicon is often used when making MOS devices using the self-alignment method or when making integrated circuits with multilayer wiring structures.

However, electrode wiring using polycrystalline silicon also has some drawbacks.

First, even if it is doped with a large amount of impurities, its resistivity is much higher than that of At, making it unsuitable for high-speed operation.

Second, when forming a two-layer silicon gate electrode such as in a CCD or MOS dynamic RAM, the surface of the first layer polycrystalline silicon gate electrode is thermally oxidized and covered with an oxide film, and then the second layer polycrystalline silicon gate electrode is covered with an oxide film. Although a silicon gate electrode is formed, a polycrystalline silicon oxide film has poor uniformity and insulation properties and is less reliable as an insulating film than that of single-crystal silicon.

Third, when constructing a polycrystalline silicon gate electrode and manufacturing a MOS transistor by the self-alignment method, polycrystalline silicon microcrystals grow to form large grains during the source and drain diffusion process, and are oxidized by thermal oxidation. When forming a film, agglomerates of crystal grains are also generated, and the insulation properties deteriorate along the agglomerates of crystal grains.

Fourth, when polycrystalline silicon in which phosphorus is diffused as an impurity is oxidized, phosphosilicate glass is formed.As is well known, this glass is highly hygroscopic, so it absorbs moisture and damages the device. Characteristics tend to deteriorate.

The present invention has been made in order to eliminate the various drawbacks mentioned above all at once, and provides a method for manufacturing a semiconductor device that realizes a multilayer wiring structure that enables high-speed operation of the device and guarantees stability and reliability of device characteristics. This is what we are trying to provide.

That is, in manufacturing a semiconductor device having at least one semiconductor element, the method of the present invention deposits a refractory metal silicide film on an insulating film provided on a semiconductor substrate and selectively etches it to form a first electrode. a step of forming wiring, a step of removing the exposed insulating film using the first electrode wiring as a mask to expose a part of the semiconductor substrate, and simultaneously removing the high melting point metal silicide electrode wiring and the exposed semiconductor substrate. The method is characterized by comprising a step of performing oxidation treatment, and a step of forming a second electrode wire so that at least two parts thereof overlap on the oxide film on the first electrode wire.

Examples of the high melting point metal silicide which is the first electrode wiring material in the present invention include silicides of high melting point metals such as Mo, w1Ta, and Nb. Sputtering method, vapor deposition method, vapor phase growth method, etc. are adopted.

As the selective etching method for the high melting point metal silicide film in the present invention, for example, photolithography using Freon gas plasma, a mixture of hydrogen fluoride and nitric acid, or the like as an etching means can be employed.

As the material constituting the second electrode wiring in the present invention, the above-mentioned high melting point metal silicide or other materials such as aluminum, molybdenum, tungsten, polycrystalline silicon, etc. can be used.

According to the method of the present invention, by using a high melting point metal silicide as the first electrode wiring material, the specific resistance of the formed first electrode wiring can be changed from the conventional polycrystalline silicon containing high concentration impurities. Since it is significantly smaller than that of the electrode wiring, it is possible to obtain a semiconductor device in which the signal propagation speed of the first electrode wiring is fast and capable of high-speed operation.

On the other hand, when forming the second electrode wiring on the first electrode wiring, the process is performed through an oxide film generated by oxidizing the first electrode wiring made of high melting point metal silicide.
Compared to the conventional case where an oxide film produced by oxidizing a polycrystalline silicon film is interposed, a highly reliable semiconductor device with excellent uniformity and insulation properties can be obtained.

In other words, the oxide film obtained by oxidizing the high melting point metal silicide film has almost the same composition as the silicon oxide film (Sin2), and the crystal grain agglomerates of the high melting point metal silicide film are much larger than that of polycrystalline silicon. It is small in size, does not undergo significant crystal grain agglomeration growth during thermal processing as in the case of polycrystalline silicon, and has extremely low hygroscopicity, so it exhibits excellent insulating properties.

Further, in the method of the present invention, when forming an oxide film on the first electrode wiring, the insulating film on the exposed substrate is removed using the electrode wiring as a mask to expose a part of the substrate, and then the high melting point metal is removed. Since the silicide electrode wiring and the exposed part of the semiconductor substrate are oxidized at the same time, when the second electrode wiring is formed afterwards, the silicide electrode wiring and the exposed part of the semiconductor substrate are oxidized. Oxide films whose film thicknesses maintain a constant relationship can be interposed between them, and as a result, the threshold voltage (vtn), etc., which are electrical characteristics affected by the film thicknesses of these oxide films, can be controlled to a predetermined state.

Next, an example in which the present invention is applied to a two-phase drive type CCD having two layers of transfer gate electrodes will be described with reference to FIGS. 1a to 1d.

EXAMPLE First, as shown in FIG. 1a, the surface of a P-type Si substrate 1 is oxidized to form a silicon oxide film 2 with a thickness of IOOOA.
A film with a thickness of 300 mm is deposited on this silicon oxide film 2 by sputtering.
After depositing the MoSi2 film of 0^, this MoSi
After selectively etching and patterning the two films by photolithography using Freon gas plasma as an etching means and forming the first layer gate electrode 3, the exposed portion of the silicon oxide film 2 is etched with NH4F using the gate electrode 3 as a mask. By etching away with a solution, an exposed portion 4 was formed in a part of the P-type Si substrate 1 as shown in FIG. 1b.

Next, the first
As shown in Figure C, the surface of the first layer gate electrode 3 has a thickness of 45 mm.
After forming a silicon oxide film 6 of the same thickness on the 0A MoSi2 oxide film 5 and the exposed portion 4 of the P-type Si substrate 1, a MoSi2 film as a second layer gate electrode material is again deposited and patterned. A second layer gate electrode 7 was provided so that both side portions of the second layer gate electrode 7 partially overlapped with the first layer gate electrode 3 (as shown in FIG. 1d).

After this, although not shown, the Tr
After forming a CVD oxide film, a contact hole is formed, an Al film is deposited and patterned, and wiring and inputs are formed to connect an adjacent pair of first and second layer gate electrodes. A CCD was fabricated by wiring the output electrodes.

When we investigated the specific resistance of the first layer gate electrode 3 and the second layer gate electrode I in the obtained CCD, we found that both of them were about 1 x 10-4 ohm 1 cm, which is different from the conventional multilayer film containing high concentration impurities. It was found that the gate electrode is about one order of magnitude smaller than a gate electrode made of crystalline silicon, and the signal propagation speed of the gate electrode is increased, enabling high-speed operation.

In addition, when the opposing area of the first layer gate electrode 3 and the second layer gate electrode 7 was set to 0.0028 d, and a withstand voltage test was conducted between the first and second layer gate electrodes 3 and 7, the second layer gate electrode 3 and the second layer gate electrode 7 were tested.
The results shown in the figure were obtained.

As is clear from this figure, the breakdown voltage is 35 to 45
The average dielectric breakdown strength at the center value is 9 x 10
The voltage was very good at 6V/cm.

Moreover, the leakage current is about 10-14A, and the first layer
It has been demonstrated that the oxide film 5 between the second layer gate electrodes 3 and 7 is an excellent insulating film.

As detailed above, according to the present invention, devices such as CCD, VIO S dynamic RAM, etc., which have realized a multilayer wiring structure that enables high-speed operation of the device and guarantees stability and reliability of device characteristics, can be used. It has remarkable effects such as being able to manufacture semiconductor devices such as semiconductor devices.

[Brief explanation of the drawing]

Figures 1a to d are cross-sectional views showing the manufacturing process of an embodiment in which the present invention is applied to a CCD, and Figure 2 is a first layer and second layer gate electrode of the COD obtained by the steps of Figures 1a to d. FIG. DESCRIPTION OF SYMBOLS 1... P-type Si substrate, 3... First layer gate electrode, 5
. . . MoSi2 oxide film, 6 . . . silicon oxide film, 7 . . . second layer gate electrode.

Claims (1)

[Claims] 1. In manufacturing a semiconductor device having at least one semiconductor element, a step of depositing a high melting point metal silicide film on an insulating film provided on a semiconductor substrate and selectively etching it to form a first electrode wiring. a step of removing the exposed insulating film using the first electrode wiring as a mask to expose a part of the semiconductor substrate; and a step of simultaneously oxidizing the high melting point metal silicide electrode wiring and the exposed semiconductor substrate. ,
A method of manufacturing a semiconductor device, comprising the step of forming a second electrode wiring so as to at least partially overlap the oxide film on the first electrode wiring.