JPH01120051A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH01120051A JPH01120051A JP27762187A JP27762187A JPH01120051A JP H01120051 A JPH01120051 A JP H01120051A JP 27762187 A JP27762187 A JP 27762187A JP 27762187 A JP27762187 A JP 27762187A JP H01120051 A JPH01120051 A JP H01120051A
- Authority
- JP
- Japan
- Prior art keywords
- refractory metal
- polysilicon
- film
- oxide film
- low
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 17
- 229910044991 metal oxide Inorganic materials 0.000 claims abstract description 8
- 150000004706 metal oxides Chemical class 0.000 claims abstract description 8
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 8
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 8
- 239000003870 refractory metal Substances 0.000 claims abstract 8
- 230000008018 melting Effects 0.000 claims description 9
- 238000002844 melting Methods 0.000 claims description 9
- 229910052751 metal Inorganic materials 0.000 claims description 4
- 239000002184 metal Substances 0.000 claims description 4
- 229920005591 polysilicon Polymers 0.000 abstract description 16
- 238000000034 method Methods 0.000 abstract description 6
- 238000004544 sputter deposition Methods 0.000 abstract description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 3
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 3
- 239000000758 substrate Substances 0.000 abstract description 3
- 238000009792 diffusion process Methods 0.000 abstract description 2
- 230000003647 oxidation Effects 0.000 abstract description 2
- 238000007254 oxidation reaction Methods 0.000 abstract description 2
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 abstract 2
- 230000002542 deteriorative effect Effects 0.000 abstract 1
- 239000005365 phosphate glass Substances 0.000 abstract 1
- 239000003990 capacitor Substances 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 3
- 229910052721 tungsten Inorganic materials 0.000 description 3
- 239000010937 tungsten Substances 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- QXYJCZRRLLQGCR-UHFFFAOYSA-N dioxomolybdenum Chemical compound O=[Mo]=O QXYJCZRRLLQGCR-UHFFFAOYSA-N 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 229910020968 MoSi2 Inorganic materials 0.000 description 1
- 229910008479 TiSi2 Inorganic materials 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- DFJQEGUNXWZVAH-UHFFFAOYSA-N bis($l^{2}-silanylidene)titanium Chemical compound [Si]=[Ti]=[Si] DFJQEGUNXWZVAH-UHFFFAOYSA-N 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は高速、高密度集積回路に使われる半導体装置に
関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to semiconductor devices used in high speed, high density integrated circuits.
従来の技術
従来のポリサイド構造を持つＭＯＳキャパシターに於て
ポリサイドの構造はポリシリコンの上に直接シワサイド
を形成しておりポリシリコンの厚さが２０００オングス
トロ一ム以上の厚さであった。BACKGROUND OF THE INVENTION In a conventional MOS capacitor having a polycide structure, the polycide structure has a wrinkled side formed directly on polysilicon, and the thickness of the polysilicon is 2000 angstroms or more.
発明が解決しようとする問題点
従来の技術に於てポリシリコンの厚みが２０００オング
ストロ一ム以上あるためポリサイド全体の厚みを一定に
保つには低抵抗であるシリサイドの厚みが制限される。Problems to be Solved by the Invention In the prior art, since the thickness of polysilicon is 2000 angstroms or more, the thickness of silicide, which has a low resistance, is limited in order to maintain a constant thickness of the entire polycide.
また、ポリシリコンを薄くした場合にはキャパシターと
しての耐圧特性が劣化する。Furthermore, when polysilicon is made thinner, the withstand voltage characteristics as a capacitor deteriorate.
問題点を解決するための手段
上記問題点１に解決するために本発明は、電気伝導性高
融点金属酸化膜上に高融点金属シリサイドもしくは高融
点金属膜全形成、した構造を有するもので、たとえばポ
リシリコンとシリサイドの間に電気伝導性のある高融点
金属酸化膜を挾むことによりポリシリコンの厚みを薄く
してもキャパシターとしての耐圧特性の劣化がないよう
にしたものである。Means for Solving the Problems In order to solve the above problem 1, the present invention has a structure in which a high melting point metal silicide or a high melting point metal film is entirely formed on an electrically conductive high melting point metal oxide film. For example, by sandwiching an electrically conductive high melting point metal oxide film between polysilicon and silicide, the breakdown voltage characteristics of the capacitor will not deteriorate even if the thickness of the polysilicon is reduced.
作用
高融点金属の酸化膜のうちＷＯ□１Ｍ００□などは電気
伝導性をもつ。その比抵抗は２，９Ｘ１０’。Function Among the oxide films of high melting point metals, WO□1M00□ and the like have electrical conductivity. Its specific resistance is 2.9X10'.
２ Ｘ １０−’ ｏｈｍ−ｃｍとＮ＋ポリシリコンと
同程度に低い。また、ＴｌＯ２は半導体性の電気伝導性
を持つ。化学的等量組成ＴｉＯ□ではそのバンドギャッ
プが約３ｘｖもあるため室温では絶縁体に近いがすこし
酸素が足りないような組成、即ち、Ｔｉ０１．９２程度
になると導体に近い電気伝導性を持つことが知られてい
る（ Ｉ Ｘ １０’−１−１ｏＨＭ−ｃｍ）。2 x 10-' ohm-cm, which is as low as N+ polysilicon. Furthermore, TlO2 has semiconducting electrical conductivity. The chemically equivalent composition TiO□ has a band gap of about 3xv, so it is close to an insulator at room temperature, but when it has a composition that is slightly lacking in oxygen, that is, about Ti01.92, it has electrical conductivity close to that of a conductor. is known (I x 10'-1-1oHM-cm).
また、キャパシターの耐圧特性を良好なものにするため
にはポリシリコンはシリサイドと反応してはいけない。Further, in order to improve the breakdown voltage characteristics of the capacitor, polysilicon must not react with silicide.
反応を止めるためにはポリシリコンとシリサイドの間に
化学的に安定物質を挾むことが有効である。金属の酸化
物はそれぞれがほとんど化学的に安定な物質である。た
とえば常温にｂけるＷＯ□、 ＭｏＯ２，Ｔｉｅ、、の
標準生成エンタルピーはそれぞｆＬ −６８，１、６５
、１１０ｋＯ＆ｌ／ｇ１１ａｔｍ）テｆｂ５、ｗｓｉ２
． ＭｏＳｉ２． ＴｉＳｉ２ （Ｄ ソへぞれの標準
生成エンタルピー−７，５、−９，３、−１０，７ｋＱ
ｔＬｌ ／ ｇ−１ｉｎに比べていずれも小さくまたＴ
ｉＯ７に至ってはＳｉＯ□の標準生成エンタルピー＝１
０３ｋｃａ ｅ／ ｇ−ａ ｉｎよりも小さいため非常
圧安定である。こうした電気伝導性のある高融点金属酸
化換金用いることによりきわめて安定なポリサイドキャ
パシターを形成することができる。In order to stop the reaction, it is effective to sandwich a chemically stable substance between polysilicon and silicide. Most metal oxides are chemically stable substances. For example, the standard enthalpies of formation of WO□, MoO2, Tie, at room temperature are fL -68,1, 65, respectively.
, 110kO&l/g11atm)te fb5, wsi2
．． MoSi2. Standard enthalpy of formation of TiSi2 (D) -7,5, -9,3, -10,7kQ
Both are smaller than tLl/g-1in and T
For iO7, the standard enthalpy of formation of SiO□ = 1
Since it is smaller than 0.03 kca e/g-a in, it is extremely stable. By using such an electrically conductive high melting point metal oxide, an extremely stable polycide capacitor can be formed.
本発明により低抵抗なゲート電極が特性の劣化なく形成
できるため超高速な集積回路を形成することができる。According to the present invention, a low-resistance gate electrode can be formed without deterioration of characteristics, so that an ultra-high-speed integrated circuit can be formed.
実施例 第１〜３図に本発明の一実施例を示す。Example An embodiment of the present invention is shown in FIGS. 1-3.
半導体シリコン基板１上に誘電体膜、例えば熱酸化法に
よって１ｏｏオングストロームのシリコン酸化膜２を形
成する。次に減圧気相成長法によってポリシリコン３を
１０００オングストローム形成する。次に拡散法により
ｐｏｃ１３中で９００度の熱処理を加えることによりポ
リシリコン３にＰ（リン）を拡散する。この時表面に形
成されるリンガラスは部系溶液で除去する。この上にス
パッタ法により電気伝導性高融点金属酸化膜、例えばｗ
ｏ２２形成する。このときの厚さは２００オングストロ
ームである。この上に同じくスパッタ法によってタング
ステン（Ｗ） ５ （ｉ−２０ｏＯオングストロームの
厚さで形成する（第１図）。次にレジストパターンθを
形成する（第２図）。そして次にレジストパターン６′
！ｉｌ−マスクとして５Ｆ６ｉ含むガス中でＲＩＫ（リ
アクティブ イオン エツチング）を行うことにより選
択的にタングステン５、ＷＯ２４、ポリシリコン３をエ
ツチングする（第３図）。以上の工程によって低抵抗な
電極を持つＭＯＳキャパシターが形成される。A dielectric film, for example, a silicon oxide film 2 having a thickness of 10 angstroms is formed on a semiconductor silicon substrate 1 by a thermal oxidation method. Next, polysilicon 3 having a thickness of 1000 angstroms is formed by low pressure vapor deposition. Next, P (phosphorus) is diffused into the polysilicon 3 by heat treatment at 900 degrees in the POC 13 using a diffusion method. At this time, the phosphorus glass formed on the surface is removed with a special solution. On top of this, an electrically conductive high melting point metal oxide film is formed by sputtering, e.g.
Form o22. The thickness at this time is 200 angstroms. On top of this, tungsten (W) 5 (i-20oO angstroms thick) is formed by the same sputtering method (Fig. 1). Next, a resist pattern θ is formed (Fig. 2). Then, a resist pattern 6' is formed.
! Tungsten 5, WO 24, and polysilicon 3 are selectively etched by performing RIK (reactive ion etching) in a gas containing 5F6i as an il-mask (FIG. 3). Through the above steps, a MOS capacitor having low resistance electrodes is formed.
発明の効果
本発明により低抵抗なゲート電極を有するＭＯ５構造の
半導体装置を形成することが出来る念め、従来の集積回
路の演算速度をさらに上げることができる。Effects of the Invention According to the present invention, it is possible to form a semiconductor device having an MO5 structure having a gate electrode with low resistance, so that the operation speed of a conventional integrated circuit can be further increased.
図
第１Ｖ〜第３図は本発明の一実施例の配線パターン形成
工程断面図である。
１・・・・・・シリコン基板、２・・・・・・シリコン
酸化膜。
３・・・・・・ポリシリコン、４・・・・・・ＷＯ２，
５・・・・・・タングステン。
代理人の氏名 弁理士 中 尾 敏 男 ほか１名第１
図
第２図
第３図1V to 3 are cross-sectional views of a wiring pattern forming process according to an embodiment of the present invention. 1...Silicon substrate, 2...Silicon oxide film. 3...Polysilicon, 4...WO2,
5...Tungsten. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 2 Figure 3
Claims (2)
サイドもしくは高融点金属膜を形成した配線を有するこ
とを特徴とする半導体装置。(1) A semiconductor device characterized by having wiring in which a refractory metal silicide or a refractory metal film is formed on an electrically conductive refractory metal oxide film.
性高融点酸化膜を形成した三層構造の電極を有すること
を特徴とする半導体装置。(2) A semiconductor device characterized by having an electrode having a three-layer structure in which an electrically conductive high melting point oxide film is formed between a polycrystalline silicon film and a high melting point metal film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62277621A JP2677996B2 (en) | 1987-11-02 | 1987-11-02 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62277621A JP2677996B2 (en) | 1987-11-02 | 1987-11-02 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01120051A true JPH01120051A (en) | 1989-05-12 |
| JP2677996B2 JP2677996B2 (en) | 1997-11-17 |
Family
ID=17585971
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62277621A Expired - Fee Related JP2677996B2 (en) | 1987-11-02 | 1987-11-02 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2677996B2 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH036821A (en) * | 1989-06-05 | 1991-01-14 | Matsushita Electron Corp | Manufacture of semiconductor device |
| US5183531A (en) * | 1989-08-11 | 1993-02-02 | Sanyo Electric Co., Ltd. | Dry etching method |
| KR20010059854A (en) * | 1999-12-30 | 2001-07-06 | 박종섭 | Semiconductor device and method for forming the same |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61255050A (en) * | 1985-05-08 | 1986-11-12 | Nec Corp | Semiconductor integrated circuit device |
| JPS61265856A (en) * | 1985-05-20 | 1986-11-25 | Nippon Telegr & Teleph Corp <Ntt> | Capacitor |
-
1987
- 1987-11-02 JP JP62277621A patent/JP2677996B2/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61255050A (en) * | 1985-05-08 | 1986-11-12 | Nec Corp | Semiconductor integrated circuit device |
| JPS61265856A (en) * | 1985-05-20 | 1986-11-25 | Nippon Telegr & Teleph Corp <Ntt> | Capacitor |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH036821A (en) * | 1989-06-05 | 1991-01-14 | Matsushita Electron Corp | Manufacture of semiconductor device |
| US5183531A (en) * | 1989-08-11 | 1993-02-02 | Sanyo Electric Co., Ltd. | Dry etching method |
| KR20010059854A (en) * | 1999-12-30 | 2001-07-06 | 박종섭 | Semiconductor device and method for forming the same |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2677996B2 (en) | 1997-11-17 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |