JP3416205B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and its manufacturing method, and more particularly to a semiconductor device having a capacitor composed of a lower electrode, an interlayer insulating film and an upper electrode, and its manufacturing method.

[0002]

2. Description of the Related Art Due to the remarkable miniaturization of semiconductor devices in recent years, the cross-sectional area of wiring used in semiconductor devices has been reduced,
The resistance value of the wiring is increasing in inverse proportion to it. Therefore, for example, in the silicon gate MOS transistor technology, there has been a problem that signal transmission is delayed due to the resistance of the silicon gate and wiring.

In order to solve such a problem, a high melting point metal is deposited or a metal silicide is deposited on the polycrystalline silicon layer to reduce the resistance of the wiring.

On the other hand, in miniaturized MOS analog circuits, capacitors are frequently used, and it is desired that the voltage-capacitance characteristics have good linearity. In order to form such a capacitor, it is advantageous in terms of performance or manufacturing cost to manufacture it by the following method.

That is, after forming an active region for forming a transistor, a polycrystalline silicon layer is deposited on the entire surface, impurities are introduced, and a conductive layer is formed. This conductive layer is MOS
It becomes the gate electrode of the transistor and the lower electrode of the capacitor. Next, a silicon oxide film as an insulating dielectric is formed on the conductive layer by a thermal oxidation method or a CVD (Chemica) method.
l Vapor Deposition) method.

Further, a polycrystalline silicon layer is deposited, impurities are introduced, and a conductive layer is formed. This conductive layer is lithographically etched to form the upper electrode of the capacitor, and then the conductive layer is lithographically etched again to the lower electrode of the capacitor, the gate electrode,
Form the wiring.

[0007]

However, in the case of realizing a miniaturized MOS analog circuit, if the above-mentioned metal silicide or the like is used for the wiring or the gate electrode in order to reduce the resistance of the wiring, the above-mentioned problem occurs. In the manufacturing method, metal silicide or the like is exposed on the surface of the gate electrode or the lower electrode of the capacitor. Therefore, there is a problem that the interlayer insulating film formed on the lower electrode of the capacitor comes into contact with the metal silicide, and the interlayer insulating film is contaminated, and the withstand voltage and accuracy are deteriorated. On the other hand, there is also a method of using a relatively thick film that has a high dielectric constant such as silicon nitride and is advantageous for contamination and dielectric strength, but in these films, the dielectric constant changes depending on the voltage, and good capacitance-voltage characteristics are obtained. Can't get Therefore, a silicon oxide film which is less contaminated is desired as a dielectric of a high precision capacitor in an LSI.

Therefore, an object of the present invention is to solve the above-mentioned problems and to provide a capacitor having a high linearity of capacity-voltage characteristics, a high withstand voltage, and a high reliability while reducing the resistance of wiring. A semiconductor device and a manufacturing method thereof are provided.

[0009]

[0010]

In order to solve the problems] to achieve such a purpose
Therefore, the semiconductor device of the present invention includes a semiconductor substrate and the semiconductor substrate.
Metal silicide layer or high melting point provided on the conductor substrate
On the metal layer and the metal silicide layer or the refractory metal layer
And a polycrystalline silicon layer provided on the lower electrode,
Use the insulating layer provided on the polycrystalline silicon layer as a dielectric
Capacitive element and the metal silicide layer or the high melting point gold
It is arranged on the polycrystalline silicon layer without directly contacting the metal layer.
And an Al wiring layer to be wired .

[0011] In the method of the present invention,
A metal silicide layer or a refractory metal layer is formed on the semiconductor substrate.
The step of forming the metal silicide layer or the high melting point
Forming a polycrystalline silicon layer on the point metal layer, and
Metal silicide layer or refractory metal layer and polycrystal
Using the silicon layer as the lower electrode of the capacitive element,
Form an insulating layer that will be the dielectric of the capacitive element on the recon layer
And the metal silicide layer or the high melting point gold
The insulating layer is etched so that the metal layer is not exposed.
Forming an opening, and forming an Al wiring layer in the opening.
The metal silicide layer or the refractory metal layer
To the polycrystalline silicon layer without direct contact with
l Wiring layer is included.

[0012]

According to the present invention, since the lower electrode is formed of the metal silicide layer or the refractory metal layer, the resistance of the lower electrode and the wiring can be sufficiently lowered, and the interlayer insulating film of the capacitor can be made of metal. Since it does not come into contact with the silicide, it becomes an interlayer insulating film with good characteristics. further,
Interlayer insulation on a polycrystalline silicon layer to form openings
Metal silicide layer or high melting point even if the layer is etched
Wiring to the lower electrode without exposing the metal layer
The wiring layer also directly contacts the metal silicide layer or the refractory metal layer.
Since it does not touch, it can prevent metal contamination.
It

[0013]

The present invention will be described in detail below with reference to the drawings.

FIG. 1 is a schematic sectional view showing a semiconductor device of the present invention.

1 is a semiconductor substrate, 2 is a field oxide film,
3, 4 and 5 are conductive layers forming the lower electrode, 3 is a polycrystalline silicon layer, 4 is a metal silicide layer, and 5 is a polycrystalline silicon layer. Further, 6 is an interlayer insulating film, and 7 is a polycrystalline silicon layer forming an upper electrode.

As the semiconductor substrate 1, for example, an n-type (100) silicon single crystal substrate is used, and a field oxide film 2 is formed on the semiconductor substrate 1 by, for example, thermal oxidation, and on the field oxide film 2. Polycrystalline silicon layer 3,
A lower electrode composed of the metal silicide layer 4 and the polycrystalline silicon layer 5 is formed.

Since the interlayer insulating film 6 is formed on this lower electrode and the polycrystalline silicon layer 5 is formed on the uppermost layer of the lower electrode, the interlayer insulating film 6 does not directly contact the metal silicide layer 4. Therefore, the interlayer insulating film 6 is not contaminated, and the withstand voltage and accuracy are not deteriorated. A refractory metal layer may be formed instead of the metal silicide layer 4.

FIG. 2 is a process chart showing the method for manufacturing a semiconductor device of the present invention.

First, as shown in FIG. 2A, n-type (1
00) A field oxide film 2 is formed on the silicon single crystal substrate 1 by, for example, thermal oxidation, and then the polycrystalline silicon layer 3 is 1000 Å, the metal silicide layer 4 is 1500 Å, and the polycrystalline silicon layer is formed on the field oxide film 2. 5 to 100
Form to a thickness of 0Å. Polycrystalline silicon layers 3 and 5
Is, for example, low pressure CVD (Chemical Vapor).
Deposition method using SiH ₄ (monosilane) as a reaction gas at a temperature of 630 ° C. and a pressure of 50 P.
It is formed in the atmosphere of a.

Here, a deposition rate of about 1000 ° C. is required for epitaxial growth using monosilane, but a temperature of 600 ° C. to 700 ° C. is used for a polycrystalline silicon layer. Therefore, in the case of forming the polycrystalline silicon layer, the process temperature can be lowered.

The polycrystalline silicon layers 3 and 5 are made conductive by adding phosphorus oxychloride (POCl ₃ ) to SiH ₄ .

POCl ₃ is a liquid at room temperature, and N ₂ or O ₂ is introduced into the furnace as a carrier gas by a bubbler. According to this method, a large amount of high-concentration doping, which cannot be mass-produced by ion implantation, can be performed in a short time. In polycrystalline silicon, the diffusion coefficient of phosphorus is extremely large, so that it is uniform in the depth direction and has a high concentration (1 × 1).
0 ²¹ / cm ³ ) of phosphorus-doped polycrystalline silicon is obtained.
Although the controllability of phosphorus concentration is poor, it is 5 × 10 ²⁰
At a concentration of / cm ³ or more, the carrier concentration does not increase due to the saturated solubility, and the variation in resistance is relatively small. In addition, the highly doped polycrystalline silicon is
It also has a gettering effect on mobile ions that are not preferable for the stability of S. The mobile ions are introduced into the MOS transistor as a contaminant element, for example, sodium during the formation of electrodes and the like, the step of the photo process, and the like. This movable ion is not preferable because it is ionized under high temperature and high electric field to change the threshold voltage of the MOS transistor. Further, phosphorus heavily doped on the back surface of the wafer has a gettering effect of heavy metals. Further, impurities may be doped by ion implantation. According to this method, it is possible to dope at a low cost and with good controllability.

The metal silicide layer can be formed by the following method.

1) A metal is directly deposited on silicon or polysilicon by a sputtering method or a vapor deposition method.

2) Simultaneous sputtering of metal and silicon from independent targets. In the formation of metal silicide by this co-sputtering, the composition of metal and silicon can be arbitrarily changed, and a high-purity target can be used.
A film containing few impurities such as O can be obtained. This method is particularly effective for forming metal silicide.

3) Simultaneous vapor deposition of each element by electron beam or resistance heating. The electron beam co-evaporation method uses a high-purity source and is performed in a high vacuum, so that a film with less contamination can be obtained.

4) Chemical vapor deposition (CVD) is used to grow a metal on a polysilicon or silicon substrate, or to grow metal and silicon simultaneously.

Other methods for forming metal silicide include:
There are also a method of performing reactive sputtering using a Mo target in a SiH ₄ / Ar atmosphere and a method of heat-treating Mo in a SiH ₄ atmosphere.

Silicide formed by the above method and which is of interest to LSI is a group IV-A, VA, VI-A of the periodic table, that is, a refractory metal silicide and a group VIII silicide.

TiSi ₂ , VSi which is a metal silicide
₂ , CoSi ₂ , NiSi, ZrSi, NbSi ₂ , P
_{dSi 2, HfSi 2, TaSi 2} , WSi 2, PtS
The resistivity of i ₂ is several tens of μΩ · cm.

Ti, Z instead of the metal silicide layer 4
A refractory metal such as r, Hf, V, Nb, Ta, Cr, Mo or W may be used.

Ti, Zr, Hf, V, which are refractory metals,
The resistivity of Nb and Ta is several tens of μΩ · c in case of bulk crystal.
m, and the resistivity in the case of Cr, Mo, W is several μΩ · c
m.

Polycrystalline silicon, which has been used for a long time, has a specific resistance of about 10 ⁻³ Ωcm even if the maximum amount of impurities is added, and the layer resistance at a film thickness of 3000 to 5000 Å which is easy to use as an electrode is 20. With ~ 30Ω / □, it started to be one of the causes of wiring delay with the miniaturization of devices.

However, in comparison with the resistivity of polycrystalline silicon, in the case of metal silicide, 1/10 to 1/2
It is 0, which is about 1/100 in the case of a refractory metal, and the resistivity is extremely small.

Then, as shown in FIG. 2B, an interlayer insulating film 6 is formed on the lower electrode to a thickness of 350 Å, for example. The interlayer insulating film 6 may be formed by, for example, dry oxidation of 1000 Å, or may be formed by a CVD method by thermal decomposition of TEOS (tetraethoxy orthosilicate ester). At this time, only the polycrystalline silicon is exposed in the lower electrode, and a good oxide film can be formed. Next, a polycrystalline silicon layer 7 serving as an upper electrode is formed to a thickness of 2000 liters, and phosphorus or the like is diffused so as to have conductivity.

Next, as shown in FIGS. 2C and 2D, the upper electrode is etched and the lower electrode is etched to form a capacitor.

Finally, the interlayer insulating film 8 is formed, appropriate portions of the upper electrode and the lower electrode are opened, and aluminum or the like is formed by the sputtering method to form the wiring layer 9 (FIG. 2).
(E)). At this time, even if etching is performed to form the opening, the metal silicide layer is not exposed, and the wiring layer 9 that is wired to the lower electrode does not directly contact the metal silicide layer. Can be prevented.

Al is generally used as the material of the wiring layer 9. In addition to 100% Al wiring, Al-Si, Al-C
A to which u or another atom such as Al-Cu-Si is added
The l wiring is also used to suppress the generation of Al spikes and electromigration.

The miniaturization of devices tends to increase the current density of Al wiring. Therefore, electromigration is a serious problem. One solution to prevent this is to use MoSi ₂ or TiSi on the Al wiring.
There is also a method of coating ₂ . Electromigration in Al wiring from the evaluation of the activation energy, it is known to move through the grain boundary, MoSi ₂
By coating Al on Al and heat treating
It is considered that the electromigration is occupied by ₂ and TiSi ₂ , and the movement of Al atoms is not in the Al grain boundaries but in the Al bulk, so that the electromigration is alleviated.

When the wiring pattern is determined by the fine processing technique, a passivation film is deposited on the entire surface in order to protect the semiconductor device. For this, a phosphorus glass film such as PSG is used. Since the thermal expansion coefficient of the PSG film is almost the same as that of Al, there is no concern about cracks and the like and it is an excellent passivation material. Also, plasma CVD
Silicon nitride formed by the method is also used as a passivation film because of its high strength and high moisture resistance.

FIG. 3 is a schematic sectional view showing another embodiment of the present invention.

The same components as those in FIG. 1 are designated by the same reference numerals, and the description thereof will be omitted here.

In FIG. 3, 10 is a gate oxide film, and 11
Reference numerals 12 and 12 respectively denote a source region and a drain region of the MOS transistor, and 13 denotes a gate electrode.

The gate electrode 13 is a three-layer conductive layer formed simultaneously with the lower electrode of the capacitor. Therefore, the resistance of the gate electrode and the wiring portion can be reduced, and the interlayer insulating film 6 of the capacitor does not come into direct contact with the metal silicide layer 4, so that the capacitor can be made highly reliable.

FIG. 4 is a process chart showing the method for manufacturing the above-mentioned semiconductor device.

First, as shown in FIG. 4A, n-type (10
0) A field oxide film 2 is formed on a semiconductor substrate 1 made of silicon single crystal by, for example, thermal oxidation to form a MOS.
A gate oxide film 10 is formed in a region where a transistor is formed.
Form to a thickness of 50Å. Next, the field oxide film 2
And a polycrystalline silicon layer 3 formed on the gate oxide film 10.
The thickness of 00Å, the metal silicide layer 4 is formed to a thickness of 1500Å, and the polycrystalline silicon layer 5 is formed to a thickness of 1000Å. The polycrystalline silicon layers 3 and 5 and the metal silicide layer 4 are formed by, for example, the low pressure CVD method in the same manner as the above-mentioned method, and the polycrystalline silicon layers 3 and 5 are made of phosphorus oxychloride (POCl ₃ ) or the like. Diffuses phosphorus and makes it conductive.

Next, as shown in FIG. 4B, an interlayer insulating film 6 is formed on the lower electrode to a thickness of 350 Å, a polycrystalline silicon layer 7 to be an upper electrode is formed to a thickness of 2000 Å, and phosphorus is formed. Diffuses to make it conductive.

Next, as shown in FIG. 4C, the polycrystalline silicon layer 7 is etched leaving a portion to be an upper electrode, and becomes a lower electrode and a gate electrode as shown in FIG. 4D. The polycrystalline silicon layer 3, the metal silicide layer 4, and the polycrystalline silicon layer 5 are etched leaving a portion to form a capacitor and a gate electrode, and then arsenic is diffused to form source and drain regions 11 and 12. And MOS
By forming a transistor, the semiconductor device shown in FIG. 4E can be obtained.

[0049]

As described above, according to the present invention,
Since the lower electrode is formed of the metal silicide layer or the refractory metal layer, the resistance of the lower electrode and the wiring can be sufficiently reduced, and the interlayer insulating film of the capacitor is not brought into contact with the metal silicide, so that the characteristics are excellent. It becomes an interlayer insulating film. In addition, multiple holes are needed to form the opening.
Even if the interlayer insulating layer on the crystalline silicon layer is etched, gold
Do not expose the metal silicide layer or refractory metal layer.
In addition, the wiring layer that is wired to the lower electrode is also directly connected to the metal
Since it does not contact the id layer or the refractory metal layer,
Metal contamination can be prevented.

Therefore, it is possible to provide a highly reliable semiconductor device having a good linearity of the capacity-voltage characteristic, a high withstand voltage and a high reliability.

Further, according to this example, since the interlayer insulating film does not directly contact the metal silicide film or the refractory metal layer, the dielectric strength and accuracy are not deteriorated. Furthermore, in this example, since the metal silicide or the refractory metal having an extremely low resistance is used as the lower electrode, the scaling ratio can be kept small, the linearity of the capacity-voltage characteristic becomes good, and the reliability is high. A semiconductor device can be realized.

[Brief description of drawings]

FIG. 1 is a schematic cross-sectional view showing a semiconductor device of the present invention.

FIG. 2 is a process drawing showing the method for manufacturing a semiconductor device of the present invention.

FIG. 3 is a schematic cross-sectional view showing another semiconductor device of the present invention.

FIG. 4 is a process drawing showing the manufacturing method of the semiconductor device shown in FIG.

[Explanation of symbols]

1 Semiconductor substrate 2 field oxide film 3,5,7 Polycrystalline silicon layer 4 Metal silicide layer 6 Interlayer insulation film 8 Interlayer insulation film 9 wiring layers

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ identification code FI H01L 27/06 (58) Fields surveyed (Int.Cl. ⁷ , DB name) H01L 27/04 H01L 21/822 H01L 21/28 301 H01L 21/8234 H01L 27/06

Claims (2)

(57) [Claims] 1. A semiconductor substrate and a metal silicide layer or a metal layer provided on the semiconductor substrate.
Melting point metal layer and the metal silicide layer or the high melting point metal
A polycrystalline silicon layer provided on the layer as a lower electrode,
The insulating layer provided on the polycrystalline silicon layer is referred to as a dielectric.
To directly contact the capacitive element and the metal silicide layer or the refractory metal layer.
Al wired to the polycrystalline silicon layer without touching
A semiconductor device comprising: a wiring layer. 2. A metal silicide layer or a semiconductor silicide layer on a semiconductor substrate.
A step of forming a refractory metal layer, and a step of forming multiple layers on the metal silicide layer or the refractory metal layer.
A step of forming a crystalline silicon layer, and the step of forming the metal silicide layer or the refractory metal layer and the polycrystalline silicon layer.
Using the crystalline silicon layer as the lower electrode of the capacitive element,
An insulating layer that serves as the dielectric of the capacitive element is formed on the crystalline silicon layer.
The step of forming and exposing the metal silicide layer or the refractory metal layer
So that the insulating layer is etched to form openings
And a step of forming an Al wiring layer in the opening ,
Before directly contacting the metal layer or the refractory metal layer
And a step of wiring the Al wiring layer on the polycrystalline silicon layer,
A method of manufacturing a semiconductor device, comprising: