JP3222501B2 - Semiconductor device and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to forming a contact with a semiconductor device having a shallow impurity region.

[0002]

2. Description of the Related Art In recent years, a large-scale integrated circuit (IC) formed by integrating a large number of transistors, resistors, and the like into an important part of a computer or communication device so as to form an electric circuit and integrating them on one chip. LSI) is frequently used. This LSI
Improving the performance of a single device is important for improving the performance of the entire device. Since this can be achieved by, for example, increasing the degree of integration of the LSI, it is necessary to miniaturize a basic element of the LSI, for example, a field effect transistor (FET). Therefore, as the gate of the FET is shortened,
The drain region is also required to be shallow, and a low-acceleration ion implantation method is widely used as one of the methods for forming the source / drain region to be shallow. By using this method, a shallow source / drain region of about 0.1 μm can be formed, and a finer and higher performance FET can be obtained.

However, the impurity layer formed only by the ion implantation method as described above has a high resistance and a seed of 100 Ω / □ or more.
It becomes resistance. Therefore, in order to increase the speed of the FET, it is necessary to reduce the sheet resistance of the impurity layer and improve the flow of the drain current.

Further, as the diameter of the contact hole becomes smaller, the Al—Si—
In order to solve the problem that Si in the Cu alloy precipitates in the contact hole and increases the contact resistance, it is increasingly necessary to form a barrier metal between the substrate and the Al-Si-Cu alloy.

In order to solve the above two problems,
Various methods for metallizing a part of the impurity layer or the inside of the contact hole opening are considered, for example, a method called salicide. This is shown in FIG.

In this method, first, as shown in FIG. 4A, the semiconductor device is surrounded by a field oxide film 102 and an insulating film 106 of about 150 nm formed on the side wall of the gate electrode.
0) After the impurity diffusion layer 108 is formed on the substrate 101 having a structure in which the silicon surface is exposed by using a well-known ion implantation method, a titanium (Ti) film 107 having a thickness of 40 nm is deposited.

Then, lamp annealing is performed to form a titanium silicide TiSi ₂ film 109 in a region where the silicon surface and the titanium film 107 are in contact with each other as shown in FIG.

Thereafter, the unreacted Ti film 107 is removed by etching. Finally, an insulating film 110 is provided and an opening is formed, and then a wiring 117 is formed (FIG. 4C).

By using this method, for example, 80
nm thick silicide, and
Resistance can be reduced to 2-3Ω / □.

However, recent energetic research has revealed that this type of method has the following problems.

In order to form a device in which the gate length of the FET is 0.3 μm or less, the depth of the diffusion layer needs to be 0.1 μm or less. p ⁺ due to the large diffusion coefficient than boron used to form a diffusion layer (B) arsenic used for forming the n ⁺ diffusion layer (As), in particular to satisfy the criteria p ⁺ It is important for the diffusion layer.

In order to form such a shallow p ⁺ diffusion layer using boron, it is necessary to perform a heat treatment at a low temperature of about 850 ° C. However, it was found that when TiSi ₂ was formed using the above method, a high-concentration region of B existing on the surface of the Si substrate was consumed with silicide formation, and the B concentration at the TiSi ₂ / Si interface was significantly reduced. For example, heat treatment at 850 ° C. is performed after ion implantation of BF ₂ , and p
^{When a +} diffusion layer was formed, B diffused outward, and the interface concentration between silicide and Si became a low value of 3 × 10 ¹⁹ cm ⁻³ or less. Furthermore, in order to enhance the reliability of the device, it is necessary to perform a high-temperature heat treatment called a gettering step at 850 ° C. for 60 minutes in a POCl ₃ gas atmosphere after the silicide is formed. In this step, the interface concentration between silicide and Si is reduced. It is even lower. As a result, the contact resistivity with respect to the p ⁺ diffusion layer becomes an extremely large value of 1 × 10 ⁻³ Ωcm ² or more, making it impossible to make ohmic electrical connection between the substrate diffusion layer and the upper metal wiring layer. It was possible.

[0013]

As described above, in the conventional semiconductor device, when a contact is formed in a shallow impurity layer of 0.1 μm or less, the impurity concentration at the interface between the metal compound layer and the semiconductor substrate is reduced by a high-temperature heat treatment step. Since the contact resistance continues to decrease with time, the contact resistance increases, and it has been difficult to make a good electrical connection between the substrate diffusion layer and the upper metal wiring layer.

This problem is particularly remarkable in the case of B having a large diffusion length, and there is a problem that the B concentration at the interface decreases due to the diffusion of B to the outside and the contact resistance increases.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a semiconductor device having a stable and low-resistance contact when forming a contact with a diffusion layer formed on a Si substrate. Aim.

[0016]

According to the present invention, an impurity diffusion layer of a second conductivity type is formed on a semiconductor substrate of a first conductivity type, and the impurity diffusion layer is contacted on the impurity diffusion layer. In a semiconductor device having a contact layer, at least an interface of the contact layer with the impurity diffusion layer is formed of a compound layer of the second conductivity type impurity element and a transition metal element.

Further, according to the present invention, in a method of manufacturing a semiconductor device in which a contact is formed in an impurity diffusion layer of a second conductivity type formed on a semiconductor substrate of a first conductivity type, the impurity element of the second conductivity type is chemically A compound layer of the second conductivity type impurity element and the transition metal element, which are contained in a ratio larger than the stoichiometric ratio, is deposited and formed. Here, it is preferable that the compound layer contains the impurity element at a higher stoichiometric ratio.

[0018]

According to the semiconductor device of the present invention, since the metal wiring layer formed on the shallow junction contains the impurity, the impurity hardly diffuses into the metal wiring layer even after the high-temperature heat treatment. Since there is no such layer, no out-diffusion of impurities occurs from the interface between the metal wiring layer and the Si layer, so that an increase in contact resistance is prevented.

Here, as the transition metal, for example, titanium, tantalum or the like is used.

Desirably, the compound of the transition metal and the impurity has a composition such that the impurity is contained more than the stoichiometric ratio.

This is especially true when the impurity is B.
Since the formation energy of the i-B bond is larger than the formation energy of the Ti-Si bond, TiSi ₂ / p ⁺ −
B existing at the Si interface is positively sucked into the TiSi ₂ film. Since the bonding ratio of Ti-B increases in proportion to the heat treatment temperature, the effect of sucking out B is accelerated by adding a high-temperature heat treatment step such as a gettering step or a melt step, and the decrease in the interface B concentration is remarkably reduced. Become. As a result, it has not been possible to form a thermally stable low resistance contact with the prior art.

On the other hand, in the present invention, since the TiB ₂ film is formed directly on p ⁺ -Si, the Ti-B bond is saturated to prevent the active absorption of B from the substrate. Further, since the B concentration in TiB ₂ is higher than that in the p ⁺ -Si substrate, thermal diffusion of B from the substrate is prevented. As a result, the interface B concentration does not decrease, and a thermally stable low resistance contact can be formed.

Further, since the bond of TiB ₂ is stronger than the bond of TiSi ₂ , the composition of TiB ₂ is maintained at the interface and the silicon is not eroded, so that there is no danger of a shallow diffusion layer being formed. . In addition, since there is no diffusion of silicon to the outside, a role as a barrier layer is well exhibited.

Furthermore, if TiB _x (x: 2 <x) where boron is larger than the stoichiometric ratio is used,
This excess B exists at a high concentration at the interface with the diffusion layer, and the interface can have a further lower resistance. Note that x is preferably smaller than 3 because a precipitate of B appears in the heat treatment step.

According to the method of manufacturing a semiconductor device of the present invention, a compound layer of the impurity element of the second conductivity type and a transition metal element is deposited and heat-treated.
The compound layer formed on the shallow junction contains the impurity, and even after the high-temperature heat treatment, there is almost no diffusion of the impurity to the compound side, and the compound layer / S
Since impurities do not diffuse outward from the i interface, an increase in contact resistance is prevented. In particular, when the second conductivity type impurity element is contained in a larger proportion than the stoichiometric ratio, the excess second conductivity type impurity element in the compound layer is highly located at the interface with the diffusion layer of the substrate. Being at a concentration, the interface can be very low resistance.

[0026]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail with reference to embodiments.

Embodiment 1 FIG. 1 is a sectional view showing a manufacturing process of a field effect transistor according to a first embodiment of the present invention.

First, a trench is formed on an n-type silicon substrate 1 having (100) as a main surface, and a trench is formed by embedding.
A field oxide film 2 of 0 nm is formed to perform element isolation. The device forming region surrounded by the oxide film 2 has a thickness of 10 n.
m gate oxide film 3, 150 nm-thick doped polycrystalline silicon layer 4a, 150 nm-thick tungsten silicide WSi ₂ layer 4b, and CVD-silicon oxide (SiO ₂ )
After sequentially depositing the film 5, the film 5 is processed into a gate shape by etching to provide a laminated film. Thereafter, the silicon oxide film 6 is
After being deposited to a thickness of 50 nm, it is processed by anisotropic etching to form a silicon oxide film 6 on the side walls of the gate. Next, after a silicon oxide film 7 having a thickness of 10 nm is formed on the exposed surface of Si, BF ₂ ⁺ ions are implanted at 5 × 10 ¹⁵ cm ⁻² at 35 keV, and heat treatment is performed at 1000 ° C. for 20 seconds in an N ₂ atmosphere. As a result, a shallow p ⁺ diffusion layer 8 of about 0.1 μm is formed (FIG. 1A).

After that, the substrate is introduced into a vacuum device and BCl
₃ By performing the plasma treatment, the thin silicon oxide film 7 on the p ⁺ diffusion layer 8 is removed. Then, after the pressure inside the vacuum apparatus is once reduced to 5 × 10 ⁻⁷ Torr or less, the temperature of the silicon substrate 1 is raised to 650 ° C. Next, a TiCl ₄ gas, a B ₂ H ₆ gas and an H ₂ gas of an Ar carrier are introduced into the vacuum apparatus at 1, 10, and 20 sccm, respectively. At this time, the pressure in the apparatus was set to 0.1 Torr. As a result, a TiB ₂ layer 9 of about 100 nm could be formed only on the p ⁺ diffusion layer 8 (FIG. 1B). Note that in this step, it is desirable to form the film in an atmosphere in which H ₂ exists. This is because, in the selective growth step, titanium chloride reacts with the silicon substrate in the initial stage to form titanium silicide and silicon tetrachloride (SiCl ₄ ). At that time, silicon tetrachloride evaporates, so that etch pits are formed on the substrate surface. And voids are easy to grow. Therefore, it is necessary to suppress the reaction with the silicon substrate using active hydrogen and selectively grow titanium boride.

When this TiB ₂ layer 9 was analyzed using AES, the atomic ratio Ti: B = 1: 2, and TiB ₂
It was confirmed that the film was growing. Next, a laminated film of a CVD-silicon oxide film 10 and a PSG film 11 is deposited on the entire surface so as to have a thickness of 0.1 μm as an interlayer insulating film, and thereafter, at 850 ° C. for 60 minutes in a POCl ₃ atmosphere under atmospheric pressure. Gettering annealing was performed. Thereafter, a contact hole is provided on the source / drain region and, for example, a selective CV
W film 12, TiN film 13 formed by D method and Al.S
The electrode wiring of the laminated film of the i-alloy film 14 is formed to complete the field effect transistor (FIG. 1 (c)).

At this time, when the B concentration at the interface between the TiB ₂ layer 9 and the p ⁺ diffusion layer 8 was examined in detail, it was 1 × 10 ²⁰ cm ^-3 , and despite the high temperature gettering step, It was confirmed that the concentration did not decrease.

When the contact resistance between the TiB ₂ layer 9 and the p ⁺ diffusion layer 8 of the field effect transistor thus formed was measured, the resistance was 23 Ω at a contact area of 1 μm ^2.
And complete ohmic contact was realized.
Further, the sheet resistance of the p ⁺ diffusion layer 8 is reduced to 5Ω / □,
It was confirmed that the transistor characteristics Gm increased by 10% or more as compared with the case where the TiB ₂ layer 9 was not formed.
Furthermore, the joint leak was comparable to the reference.

In the method of the present invention, the mechanism capable of forming a contact stable against high-temperature heat treatment is considered as follows.

In the case of the prior art in which a TiSi ₂ film is formed as a barrier metal, the generation energy of the Ti—B bond is T
B present at the TiSi ₂ / p ⁺ -Si interface is larger than TiS
i sucked into actively ₂ film. Since the bonding ratio of Ti-B increases in proportion to the heat treatment temperature, the effect of sucking out B is accelerated by adding a high-temperature heat treatment step such as a gettering step or a melt step, and the interface B
The decrease in concentration becomes remarkable. As a result, it has not been possible to form a thermally stable low resistance contact with the prior art.

In the present invention, since a TiB ₂ film is formed directly on p ⁺ -Si, Ti-B bonds are saturated to prevent active absorption of B from the substrate. Further, since the B concentration in TiB ₂ is higher than that in the p ⁺ -Si substrate, thermal diffusion of B from the substrate is prevented. As a result, the interface B concentration does not decrease, and a thermally stable low resistance contact can be formed.

To further clarify this effect, the dependence of the contact resistance on the heat treatment temperature was measured. Figure 2 shows the result.
Shown in From these results, it is recognized that the contact is lower even in the heat treatment at 700 ° C. as compared with the conventional technology when the present invention is used, and it is clear that the effect is more remarkably observed at 800 ° C. or higher.

In the first embodiment, the p ⁺ diffusion layer 8
Although the TiB ₂ layer 9 is selectively formed only on the upper surface, the same effect can be obtained by forming a TiB ₂ film on the entire surface of the Si substrate and then patterning to form wiring only on a desired region. Needless to say, this is obtained. In this case, for example, after performing an Ar sputtering process instead of the BCl ₃ plasma process in the first embodiment, the TiC
l ₄ gas, B ₂ H ₆ gas and H ₂ gas
By introducing 200 sccm, it was possible to form a uniform TiB ₂ film. Also, instead of B ₂ H ₆ gas, BCl
Similar results can be obtained when _three gases are used.

Embodiment 2 Next, a second embodiment of the present invention will be described.

FIG. 3 is a sectional view showing a manufacturing process of the field effect transistor according to the second embodiment of the present invention.

First, an 800 nm field oxide film 2 is formed by selective oxidation on an n-type silicon substrate 1 having (100) as a main surface. A gate electrode is formed in the element formation region surrounded by the oxide film 2 in the same manner as in the first embodiment. A gate oxide film 3, a doped polycrystalline silicon layer 4
a, a tungsten silicide WSi ₂ layer 4b and a CVD-silicon oxide film 5 are sequentially deposited and then processed by etching into a gate shape to provide a laminated film.

Thereafter, the BF ₂ ⁺ ions were added at 20 keV for 5 ×.
After implantation of 10 ¹⁴ cm ^-2 , a CVD-SiN film is deposited to a thickness of about 100 nm, and a silicon oxide film 6 is formed on the gate side wall using a well-known anisotropic etching method (FIG. 3A).

Thereafter, as in the first embodiment, the silicon oxide film 7 on the intended source / drain regions is removed by introducing the substrate into a vacuum apparatus and performing a BCl ₃ plasma treatment. Next, the temperature of the silicon substrate 1 was raised to 650 ° C., and TiCl ₄ gas, B ₂ H ₆ gas, and Ar gas were introduced into the vacuum apparatus at 1, 20, and 200 sccm, respectively, so that TiB _x Layer 19 was formed. Here, the difference from Example 1 is that B ₂ H _{6 with} respect to TiCl ₄ gas is used as described above.
The partial pressure ratio of the gas was set to 1 or more. The composition ratio of the thus-formed TiB _x layer 19 of about 100 nm was analyzed using AES, and as a result, the atomic ratio was Ti: B = 1: 2. 5
Was confirmed. After that, 1050 in N ₂ atmosphere
RTA (Rapid thermal annealing) for 2 seconds
+ A diffusion layer 18 is formed. Here, when the distribution of B in the diffusion layer 8 was examined by using the SIMS method, the lower part of the gate sidewall film 6 had a B concentration of 1 × 10 ¹⁹ cm ⁻³ and the TiB _x layer 19.
The lower part has an interface concentration of 1 × 10 ²⁰ cm ⁻³ and Xj = 0.15 μm.
It was confirmed that a diffusion layer 18 having a shallow depth was formed, and a transistor having a so-called LDD structure could be easily formed by the method of the present invention (FIG. 3B).

[0043] As Thereafter interlayer insulating film CVD- a laminated film of a silicon oxide film 10, PSG film 11 is deposited on the entire surface by 1.0μm thick, in POCl ₃ atmosphere under atmospheric subsequent pressure 8
Gettering annealing was performed at 50 ° C. for 60 minutes. Thereafter, a contact hole is provided on the source / drain region,
Here, for example, the W film 12 and the TiN film 1 are formed by selective CVD.
3 and an Al / Si alloy film 14 to form an electrode wiring layer, thereby completing a field effect transistor (FIG. 3C).
).

When the contact formed by using the above-mentioned Example 2 was evaluated, it was confirmed that the contact exhibited thermally stable low resistance characteristics as in Example 1.

In this method, the B of the TiBx film 19 is
Since the composition ratio of Ti to Ti is larger than 2, Ti
The bond with B is completely occupied by the composition of TiB ₂ , and the TiB _X film layer 19 contains excess B not bonded to Ti. The surplus B diffuses into the substrate in the RTA process to form a shallow bond.
In the same manner as in the case (1), Ti bonded to B does not cause the absorption of B, so that it is considered that the contact resistance does not increase even in the subsequent high-temperature heat treatment step. In this embodiment, the composition ratio of B to Ti can be set to a value larger than 3. However, in this case, a precipitate of B appears in the TiB _X film by the RTA process, and the specific resistance of the film is increased. At the same time, there was a problem that unevenness of the film was generated. Therefore, it is most appropriate that the composition ratio of B to Ti is larger than 2 and smaller than 3.

It goes without saying that the present invention can be implemented with various modifications. For example, in the above embodiment, the TiB _X mixed film is formed by using the selective or non-selective CVD method, but the same effect can be obtained by forming the film by using the simultaneous deposition of B and Ti. However, also in this case, it is desirable that the atomic ratio of B to Ti is larger than 2. Further, a laminated structure in which a Ti film is formed after depositing a B film on a Si substrate is not preferable for the purpose of the present invention. This is because the specific resistance of the B film is significantly higher than that of the TiB _X film, so that unlike the so-called salicide structure in which a metal compound layer is attached over the entire surface of the diffusion layer, the effect of reducing the sheet resistance does not occur. is there.

Further, in the above embodiment, Ti is formed on the entire surface of the diffusion layer.
Although the process of forming the B _x film has been described, it is needless to say that the present technology can be applied to the barrier metal forming process of forming the TiB _x film only in the contact hole. In this case, polycrystalline Si film, NiSi film, TiS
The use of a transition metal silicide film such as an i ₂ film, a WSi ₂ film, a MoSi ₂ film, or a high melting point metal film such as W or Ta makes it impossible with a conventional Al alloy film.
Since a low-resistance wiring that can withstand a heat process of not less than ° C. can be easily formed, a device having a three-dimensional laminated structure can be easily formed.

Although the above embodiment has been described on the p ⁺ -Si substrate, it goes without saying that the same technique can be easily applied to the n ⁺ -Si substrate. For example TiCl ₄ gas in the above embodiment, the B ₂ H ₆ to form a TiBx film using the mixed gas of the gas and Ar, B ₂ H ₆
By using AsH ₃ gas instead of gas, n ⁺
It is possible to form a Ti-As film, for example, TiAs ₂ on Si.

Further, in Examples 1 and 2, Ti was used as a transition metal. However, it is needless to say that the present invention is similarly effective for other metals.
For example, similar effects can be obtained for WB, TaB ₂ , ZrB _{2, and the} like.

In addition, the present invention is not limited to the above embodiment, but may be applied to other heat treatment atmospheres, for example, a mixed atmosphere of Ar / H ₂ ,
Needless to say, heat treatment in an N ₂ / H ₂ mixed atmosphere and an inert gas atmosphere containing 1% or less of oxygen can be used with various modifications such as the same effect.

[0051]

As described above, according to the present invention, by forming a transition metal compound having an impurity of the same conductivity type as that of the diffusion layer as a constituent element on the diffusion layer, impurities from the underlying diffusion layer can be removed. Since suction can be suppressed, a low-resistance contact that is stable even with high-temperature heat treatment can be formed.

[Brief description of the drawings]

FIG. 1 is a manufacturing process diagram of a semiconductor device according to a first embodiment of the present invention;

FIG. 2 is a diagram showing a distribution of B when the method of the present invention is used.

FIG. 3 is a manufacturing process diagram of a semiconductor device according to a second embodiment of the present invention;

FIG. 4 is a manufacturing process diagram of a conventional semiconductor device.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 silicon substrate 2 field oxide film 3 gate oxide film 4 a doped polycrystalline silicon layer 4 b tungsten silicide WSi ₂ layer 5 silicon oxide film 6 silicon oxide film 7 silicon oxide film 8 p ⁺ diffusion layer 9 TiB ₂ Layer 10 Interlayer insulating film layer 11 Interlayer insulating film layer 12 W film 13 TiN film 14 Al · Si alloy 19 TiB _x layer

Continuation of front page (56) References JP-A-2-271716 (JP, A) JP-A-5-182982 (JP, A) JP-A-5-90206 (JP, A) JP-A-4-340712 (JP) JP-A-4-14874 (JP, A) JP-A-3-224220 (JP, A) JP-A-3-198329 (JP, A) JP-A-2-246159 (JP, A) JP-A-2-58958 (JP, A) JP-A-2-34918 (JP, A) JP-A 1-268025 (JP, A) JP-A-61-263159 (JP, A) A) (58) Field surveyed (Int. Cl. ⁷ , DB name) H01L 21/28 301

Claims (5)

(57) [Claims] In a semiconductor device, an impurity diffusion layer containing boron B as an impurity is formed on a semiconductor substrate, and a contact layer in contact with the impurity diffusion layer is formed on the impurity diffusion layer. A semiconductor device comprising a titanium boride layer having a composition ratio of boron to titanium of greater than 2 at an interface with the impurity diffusion layer. 2. The thickness of said impurity diffusion layer is 0.15 μm.
2. The semiconductor device according to claim 1, wherein: 3. The semiconductor device according to claim 1, wherein said titanium boride layer is selectively formed on said impurity layer. 4. The semiconductor device according to claim 1, wherein the titanium boride layer has a composition ratio of boron to titanium smaller than 3. 5. A method of manufacturing a semiconductor device in which a contact is formed in a second conductivity type impurity diffusion layer formed on a first conductivity type semiconductor substrate, comprising: an impurity diffusion layer forming step of forming the impurity diffusion layer; A compound layer of the second conductivity type impurity element and the transition metal in which the second conductivity type impurity element is contained in a larger amount than the stoichiometric ratio with respect to the transition metal so as to be in direct contact with the impurity diffusion layer; A method of manufacturing a semiconductor device, comprising: