JPH061774B2 - Semiconductor device - Google Patents

Description

TECHNICAL FIELD OF THE INVENTION The present invention relates to a semiconductor device, and more particularly to a semiconductor device in which an electrode wiring portion of an insulated gate field effect transistor is improved.

[Technical Background of the Invention and Problems Thereof] Conventionally, an insulated zet field effect transistor (hereinafter, MO
It is called an S transistor. ) Is manufactured by the following steps.

First, in FIG. 2A, a field oxide film 12 is formed on an n-type silicon substrate 11 having a plane orientation (100), and an n-type inversion prevention layer 13 is formed on the surface of the substrate 11 below the field oxide film 12. To do. Subsequently, as shown in FIG. 3B, the substrate separated by the field oxide film 12 by thermal oxidation treatment.
A gate oxide film 14 having a thickness of 100 to 500Å is formed on 11 island regions (element regions). Subsequently, a polycrystalline silicon film doped with n-type impurities is deposited on the entire surface and patterned to form a gate electrode 15, and then p-type impurities such as boron are ion-implanted using the gate electrode 15 and the field oxide film 12 as a mask. Then, the p ⁺ -type source region 16 and the drain region 17 are formed in the island region of the substrate 11 by being activated.

Then, as shown in FIG. 3C, after depositing the CVD-SiO ₂ film 18, contact holes are formed.
A MOS transistor is manufactured by forming Al wirings 20 and 21 connected to the source and drain regions 16 and 17 through the contact holes 19 by forming holes 19 and vapor deposition and patterning of Al.

According to the above-described method, the gate electrode 15 is formed of polycrystalline silicon, so that the p ⁺ type source / drain regions 16 and 17 are formed in self-alignment with the gate electrode 15 using the gate electrode 15 as a mask. Yes, and the gate electrode
It has a feature that a high temperature heat treatment for activation can be adopted after the formation step of 15.

However, even if a polycrystalline silicon film is doped with a high concentration of impurities, its specific resistance is reduced only by about 10 ⁻³ Ωcm, and high-speed operation is restricted in a fine device. Further, as the degree of integration of the device increases, the depth of the diffusion layer of the source and drain becomes shallower, and the resistance of the diffusion layer becomes higher due to the shallow junction formation. This increases the parasitic resistance of the transistor and affects the transistor characteristics.

For this reason, the gate electrode is made of metal or metal silicide instead of the polycrystalline silicon film, or the gate electrode is made of a polycrystalline silicon film and a metal silicide formed on the polycrystalline silicon film. It is formed by a double structure.

When a metal is directly used, the metal and silicon or the interlayer insulating film often react with each other in a thermal process, and the subsequent process must be performed at a low temperature, which often limits the application. Therefore, metal silicide is often used at present. As the metal silicide, Pt, Ti,
Silicides such as Mo, W and Ta are used, and titanium silicide is particularly promising because of its low resistance.

As a method of forming the metal silicide on the source / drain regions and the gate electrode described above, for example, JP-A-57-9 is used.
The method described in the 9775 specification is known. That is, first, S is formed on the silicon substrate on which the gate electrode is formed.
After depositing an iO ₂ film and selectively removing the SiO ₂ film portions corresponding to the source and drain regions and the gate electrode, a metal film is deposited on the entire surface. Then, heat treatment is performed at a predetermined temperature to cause a metal silicide formation reaction only on the source and drain regions and on the gate electrode, and then the unreacted metal film is selectively removed by etching. A metal silicide is formed on the region and the gate electrode.

However, when the titanium silicide is formed by such a method, there are the following problems.

Usually, as a method of forming a metal silicide, heat treatment in an inert gas is adopted in consideration of productivity and the like. In this case, titanium is a highly reactive substance, as can be seen from the fact that it is used as a getter material in a vacuum.
Reacts with oxygen in the inert gas to form an oxide film. In this case, it is difficult to eliminate oxygen leakage if a normal diffusion furnace is used. Therefore, titanium becomes an oxide during the heat treatment, and it becomes difficult to form titanium silicide with good controllability. As a result, the surface resistance of titanium silicide also varies from a few Ω / □ to a few KΩ / □, resulting in a reduction in the yield of LSI.

[Object of the Invention] The present invention has been made in view of the above circumstances, and an object of the present invention is to be made of a refractory metal or a refractory metal silicide and to have a low sheet resistance and to be stable without causing a reaction with atmospheric gas or the like. Another object of the present invention is to provide a semiconductor device having an electrode wiring structure that can be formed as described above.

SUMMARY OF THE INVENTION The present invention provides a laminated gate electrode for forming a non-single crystal silicon layer and a low resistance layer containing a refractory metal on the non-single crystal silicon layer in an insulated gate field effect transistor provided on one main surface of a semiconductor substrate. And a protective film layer provided on the low resistance layer, a boundary between the low resistance layer and the non-single-crystal silicon layer, and an interlayer provided between the low resistance layer and the boundary between the protective film layer. 2. A semiconductor device comprising: a titanium nitride layer for preventing the above-mentioned chemical reaction; and an insulating layer for covering at least a side surface of the low resistance layer for blocking a reaction factor to the low resistance layer.

With such a structure, since the active refractory metal is covered with the titanium nitride layer and the insulating layer, the reaction between the refractory metal and silicon or the atmospheric gas can be suppressed.

[Embodiment of the Invention] An embodiment of the present invention will be described below with reference to the drawings. First, as shown in FIG. 1A, a field oxide film 32 is formed on an n-type silicon substrate 31 having a plane orientation (100), and an n-type reaction preventive layer is formed on the surface of the substrate 31 below the field oxide film 32. Form 33. Then, a thermal oxidation process is performed to form a gate oxide film 34 having a thickness of 100 to 500Å on the island region (element region) of the substrate 31 separated by the field oxide film 32. Subsequently, as shown in FIG. 6B, a polycrystalline silicon film 35 doped with n-type impurities is deposited on the entire surface, and then, for example, titanium target is sputtered in a nitrogen atmosphere to form a titanium nitride layer 36 of 200 Å. To do. Then, sputtering is performed in an argon atmosphere to deposit a titanium layer 37 of 2000 liters. Then again the titanium nitride layer
38 is deposited to 200 Å, and then a non-single crystal silicon film 39 doped with n ⁺ impurities is deposited.

After that, patterning is performed to form the gate electrode 40, and then p-type impurities such as boron are ion-implanted using the gate electrode 40 and the field oxide film 32 as a mask, and p ⁺
A source region 41 and a drain region 42 are formed.

Next, as shown in FIG.
After depositing SiO ₂ 43 by mical vapor deposition) and then depositing CVD-SiO ₂ 44, the contact hole 45 is opened, Al is deposited, and patterning is performed to connect through the source / drain regions 41 and 42 and the contact hole 45. The Al wirings 46 and 47 are formed to manufacture a MOS transistor.

In the above MOS transistor, since the active titanium layer 37 is covered with the titanium nitride layers 36 and 38 and the SiO ₂ film 43, the reaction between titanium and silicon and the reaction between titanium and a gas atmosphere such as oxygen are suppressed. This makes it possible to use titanium as a gate electrode. Therefore, if the thickness of the titanium layer 37 is 4000Å,
The sheet resistance is 4Ω / □, which is about 20 times smaller than that when polycrystalline silicon is used. Therefore, when it is used as, for example, a word line of a memory, the speeding up of the device can be realized.

Also, for example, when the titanium film 37 is 1000 Å,
The sheet resistance is about one fifth of that of the polycrystalline silicon film, and a flatter structure can be realized.

Incidentally, in the above-mentioned embodiment, titanium is used as the refractory metal, but the invention is not limited to this.
Tungsten, molybdenum, zirconium, tantalum, and the like, and silicides thereof may be used. Further, in the above embodiment, the example in which the present invention is applied to the structure of the gate electrode has been described, but it goes without saying that the present invention may be applied to the wiring portion.

[Effects of the Invention] As described above, according to the present invention, an electrode and wiring structure which is made of a refractory metal or a refractory metal silicide and has a stable low sheet resistance that does not react with silicon or an atmospheric gas. Can be formed.

[Brief description of drawings]

FIG. 1 is a sectional view showing a manufacturing process of a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a sectional view showing a manufacturing process of a conventional semiconductor device. 31 ... N-type silicon substrate, 34 ... Gate oxide film, 35 ... Polycrystalline silicon film, 36 ... Titanium nitride layer, 37 ... Titanium layer, 38 ... Titanium nitride layer, 39 ... Non-single crystal silicon film, 40 ... Gate electrode, 41 ... Source region, 42 ... Drain region.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location H01L 29/784

Claims (4)

[Claims] 1. An insulated gate field effect transistor provided on one main surface of a semiconductor substrate, wherein a non-single crystal silicon layer and a laminated gate electrode on which a low resistance layer containing a refractory metal is formed are adopted. A protective film layer provided on the low resistance layer,
A boundary between the low resistance layer and the non-single-crystal silicon layer, and a titanium nitride layer for preventing a chemical reaction between layers provided between the low resistance layer and the boundary between the protective film layer, and
A semiconductor device, comprising: an insulating layer that covers at least a side surface of the low resistance layer in order to block a reaction factor to the low resistance layer. 2. The semiconductor device according to claim 1, wherein the refractory metal is any one or a mixture of titanium, tungsten, molybdenum, zirconium, and tantalum. 3. The semiconductor device according to claim 1, wherein the protective film layer is formed of non-single crystal silicon. 4. The semiconductor device according to claim 1, wherein the protective film layer is formed of silicon oxide.