JPS5835919A - Manufacture of metal-semiconductor junction electrode - Google Patents

Manufacture of metal-semiconductor junction electrode

Info

Publication number
JPS5835919A
JPS5835919A JP13419681A JP13419681A JPS5835919A JP S5835919 A JPS5835919 A JP S5835919A JP 13419681 A JP13419681 A JP 13419681A JP 13419681 A JP13419681 A JP 13419681A JP S5835919 A JPS5835919 A JP S5835919A
Authority
JP
Japan
Prior art keywords
layer
thickness
formation
heat treatment
electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP13419681A
Other languages
Japanese (ja)
Other versions
JPH0139222B2 (en
Inventor
Yoshiki Wada
和田 嘉記
Yasuhiro Kawasaki
康弘 川崎
Shuichi Kanamori
金森 周一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP13419681A priority Critical patent/JPS5835919A/en
Publication of JPS5835919A publication Critical patent/JPS5835919A/en
Publication of JPH0139222B2 publication Critical patent/JPH0139222B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268

Abstract

PURPOSE:To obtain a metal-semiconductor junction electrode having a high reverse direction withstand voltage and the desired Schottky barrier height by a method wherein a thin Ti layer and a thin TiN layer are adhered being laminated on the surface of a compound semiconductor substrate provided with an ohmic electrode on the back, and the heat treatment is performed during formation or after formation of the layers thereof. CONSTITUTION:An Au-Ge alloy layer and an Ni layer are evaporated being laminated on the back of a GaAs wafer 1 to form the ohmic electrode 2, and the Ti layer 3 made thickness thereof as to 100Angstrom is adhered by sputting on the surface. Then the TiN layer 4 obtained by performing reactive sputtering of Ti in N2 plasma is laminated on the Ti layer 3, and the Ti layer 5 having 100Angstrom thickness is adhered thereon again. After then, an Al layer 6 having about 3,000Angstrom thickness is evaporated thereon, and is formed in the prescribed shape according to the photo etching method. Then the heat treatment is performed for 30sec in the H2 atmosphere held at 450 deg.C to obtain the desired junction electrode. At this constitution, the heat treatment in H2 gas may be performed during the process of formation of the layer 3, 4, or may be performed after formation thereof is finished.

Description

【発明の詳細な説明】 本発明は、チタン化合物やチタン合金を電極材料とする
金属半導体接合電極の製造方法に関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a metal semiconductor junction electrode using a titanium compound or a titanium alloy as an electrode material.

従来の金属半導体接合電極は、下地半導体(例えばSi
 、 GaAs等)上に直接金属層を設けて構成したも
の、又は下地半導体上にチタニウム(T1)層(第1層
)を形成しさらにその上に金属層(第2層)を設けて構
成したものがある。。
Conventional metal-semiconductor junction electrodes are made of an underlying semiconductor (e.g., Si
, GaAs, etc.), or by forming a titanium (T1) layer (first layer) on the underlying semiconductor and further forming a metal layer (second layer) on top of it. There is something. .

このうち前者に於いては、後に示すように逆方向耐圧が
非常に低くなったり、また、製造後の特性のばらつきが
多いために量産に適さないという欠点があった。
Among these, the former has the disadvantage that the reverse breakdown voltage is extremely low as will be shown later, and that it is not suitable for mass production due to large variations in characteristics after manufacturing.

一方、後者に於いては、Ti層の使用目的が第2層の金
属と下地半導体の間の応力を減少させ接着力を増すこと
にあったため、製造時の厚さ制御が容易で歩留りも良い
ように、厚いT1層(例えば厚さ500人)が用いられ
ていた。従って、第2層の金属(電極材料)と半導体で
決まる固有のシヨ、トキー障壁の高さと電気伝導特性を
得ることが出来ず、第1層のT1とで決まる特性が得ら
れるだけであるという欠点があった。
On the other hand, in the latter case, the purpose of using the Ti layer was to reduce the stress between the second layer metal and the underlying semiconductor and increase the adhesion strength, so it was easy to control the thickness during manufacturing and the yield was good. As such, a thick T1 layer (eg, 500 mm thick) was used. Therefore, it is not possible to obtain the characteristic height and electrical conductivity of the barrier, which is determined by the metal (electrode material) and semiconductor of the second layer, and only the characteristics determined by the T1 of the first layer are obtained. There were drawbacks.

本発明はこれらの欠点を解決するために、第1層のT1
の厚さを薄くして熱処理を行うことを特徴としたもので
あり、以下図面を用いて詳細に説明する。
In order to solve these drawbacks, the present invention aims to improve T1 of the first layer.
This method is characterized by performing heat treatment while reducing the thickness of the material, and will be described in detail below with reference to the drawings.

第1図は本発明の実施例であり、製造された金属半導体
接合電極の断面図である。図において、1はn形砒化ガ
リウム(GaAs )ウェハ、2はこのウェハ1の裏面
に設けた金・ゲルマニウム・ニッケル製オーミック電極
、3はチタニウム(T1)層(第1層)、4は窒化チタ
ニウム(TiN )層(第2層)、5はT1層(第3層
)、6はアルミニウム(Al)層(第4層)である。
FIG. 1 is an embodiment of the present invention, and is a sectional view of a manufactured metal semiconductor junction electrode. In the figure, 1 is an n-type gallium arsenide (GaAs) wafer, 2 is an ohmic electrode made of gold, germanium, and nickel provided on the back surface of this wafer 1, 3 is a titanium (T1) layer (first layer), and 4 is titanium nitride. (TiN) layer (second layer), 5 is a T1 layer (third layer), and 6 is an aluminum (Al) layer (fourth layer).

次に本発明の製造方法の主要工程を説明する。Next, the main steps of the manufacturing method of the present invention will be explained.

■ ウェハ1の裏面に金・ゲルマニウム合金を蒸着し、
次いでニッケルを蒸着し、その後水素雰囲気中で加熱し
て金・ゲルマニウム・ニッケル製オーミック電極2を形
成する。
■ Deposit gold/germanium alloy on the back side of wafer 1,
Next, nickel is vapor-deposited, and then heated in a hydrogen atmosphere to form an ohmic electrode 2 made of gold, germanium, and nickel.

■ ウェハ1の表面に第1層となる厚さ100Aの71
層3を例えばスパッタ法で形成する。
■ 71 with a thickness of 100A as the first layer on the surface of wafer 1
Layer 3 is formed, for example, by sputtering.

■ 上記第1層上に第2層となる厚さ500人のTiN
層4を窒素プラズマ中でTiをリアクティブスパッタ法
で形成する。
■ A second layer of TiN with a thickness of 500 mm on top of the first layer above.
Layer 4 is formed by reactive sputtering of Ti in nitrogen plasma.

■ 上記第2層上に第3層となる厚さ100XのTi層
5を例えばスパッタ法で形成する。
(2) A Ti layer 5 having a thickness of 100X is formed as a third layer on the second layer, for example, by sputtering.

■ さらにその上に第4層として厚さ3000人のA/
層6を例えば蒸着で形成する。
■ Further on top of that is a fourth layer with a thickness of 3000 people.
Layer 6 is formed, for example, by vapor deposition.

■ 次に第1層から第4層で形成された電極な直径20
0μmの大きさに写真食刻法で整形する。
■ Next, the electrodes formed from the first to fourth layers have a diameter of 20
Shape it to a size of 0 μm using photolithography.

■ その後450°Cの水素雰囲気中にて30秒間の熱
処理を加える。なお、この熱処理工程は、第1層と第2
層又は第2層の形成中に行なってもよい。
(2) Heat treatment is then applied for 30 seconds in a hydrogen atmosphere at 450°C. Note that this heat treatment step is performed on the first layer and the second layer.
It may also be performed during formation of the layer or second layer.

以上の工程により本発明の金属半導体接合電極が構成さ
れる。なお、各層の厚さ並にその形成方法については、
本実施例に限定されるものではない。
The metal semiconductor junction electrode of the present invention is constructed by the above steps. Regarding the thickness of each layer and its formation method,
The present invention is not limited to this embodiment.

第2図及び第3図は、裏面のオーミック電極2に対し表
面の電極(A1層6)をそれぞれ正(順方向)と負(逆
方向)にバイアスした時の電流電圧特性である。図にお
いて、7は上記の実施例すなわち本発明の製造方法によ
り作られた場合の代表的な特性であり、8は従来技術す
なわち第1層に相当するTi層を用いないで作成した場
合の代表的な特性例である。
FIGS. 2 and 3 show current-voltage characteristics when the front electrode (A1 layer 6) is biased positively (forward direction) and negatively (reverse direction) with respect to the ohmic electrode 2 on the back surface. In the figure, 7 is the typical characteristic when the product is manufactured using the above-mentioned example, that is, the manufacturing method of the present invention, and 8 is the typical characteristic when it is manufactured using the conventional technique, that is, without using the Ti layer corresponding to the first layer. This is an example of a typical characteristic.

第3図から、本発明による電極は、従来方法による場合
に比べ十分高い逆方向耐圧を有することが明らかである
。本発明は上記の利点に加えさらに次のような利点を有
する。すなわち、第2図の順方向特性から求まるショッ
トキー障壁の高さは、本発明の場合は0.9eVであり
、この値は従来方法の場合より0.3eV高くなってい
る。別に測定した容量電圧特性から求めた障壁の高さは
、両者ともほとんど等しい値で1.1eVとなっている
ことから、本実施例の順方向特性は従来技術の場合に比
べ格段に改善されていることが分かると共に、第2層と
なるTiNとウェノ・のGaAsで決まる大きな障壁の
高さを示していることが分かる。ちなみに、T1のみを
GaAs上に形成した金属半導体接合電極の障壁の高、
さは、本実施例の値より0.2eV低い値を示す。
It is clear from FIG. 3 that the electrode according to the present invention has a sufficiently higher reverse breakdown voltage than the electrode according to the conventional method. In addition to the above advantages, the present invention has the following advantages. That is, the height of the Schottky barrier determined from the forward characteristics shown in FIG. 2 is 0.9 eV in the case of the present invention, which is 0.3 eV higher than in the case of the conventional method. The barrier heights determined from the separately measured capacitance-voltage characteristics are almost the same for both, 1.1 eV, indicating that the forward characteristics of this example are significantly improved compared to the conventional technology. It can be seen that there is a large barrier height determined by the second layer of TiN and WenoGaAs. By the way, the barrier height of the metal semiconductor junction electrode where only T1 is formed on GaAs,
The value is 0.2 eV lower than the value of this example.

上記の実施例に於いて、第1層の71層3があるにも拘
らず第2層の物質固有の特性が得られる理由は、前記の
熱処理により第1層のT1がGaAsと接合を形成した
後、第2層のTiNと反応することにあると考えられる
。T1の厚さは、膜厚の制御性と均一性および実用的に
反応可能な厚さから制限され10乃至150Xである0 熱処理の条件は、前記の実施例に限らず、活性化エネル
ギー1.3eVのアレニウス則で定まる450℃30秒
相当以上の熱処理でも同様の効果が得られることを確認
した。
In the above example, the reason why the properties unique to the material of the second layer are obtained despite the presence of the first layer 71 layer 3 is that T1 of the first layer forms a bond with GaAs through the heat treatment. This is thought to be due to the reaction with the second layer of TiN. The thickness of T1 is limited to 10 to 150X due to the controllability and uniformity of the film thickness and the thickness that can be practically reacted.The conditions of the heat treatment are not limited to the above embodiments, and the activation energy is 1. It was confirmed that a similar effect can be obtained by heat treatment at 450° C. for 30 seconds or more as defined by the Arrhenius law of 3 eV.

以上は、第2層にTiNを用いた例について述べたが、
TINが高融点であるにも拘らず上記の効果がでること
から、上記の反応はTiNに固有のものではなく、従っ
て、第2層はTiNに限らず金属的性質を示すチタン化
合物(例えばTiC等)やチタン合金(例えばTi−W
、 Ti−Mo等)の場合でもT iNの場合と同様で
あることは言うまでもない。
The above describes an example using TiN for the second layer, but
The above effect is obtained despite TIN having a high melting point, so the above reaction is not unique to TiN. Therefore, the second layer is not limited to TiN, but may also be made of a titanium compound exhibiting metallic properties (for example, TiC). etc.) and titanium alloys (e.g. Ti-W
, Ti-Mo, etc.) is the same as the case of TiN.

さらに、上記の説明は良好な表面状態を得にくい化合物
半導体に共通の技術であるため、半導体基板(ウェハ1
)は上記の例にあったGaAsに限定されるものではな
く、例えばGaAlAs 、 GaP等1)であっても
よい。
Furthermore, since the above explanation is a common technique for compound semiconductors where it is difficult to obtain a good surface condition,
) is not limited to GaAs as in the above example, and may be, for example, GaAlAs, GaP, etc.1).

以上説明したように、本発明の方法により製造された金
属半導体接合電極は、製造が容易であること、高い逆方
向耐圧を有すること、第2層の物質で定まるショットキ
ー障壁の高さを容易に得られること等の利点を有するた
め、高耐圧ダイオード、集積回路内のレベルシフトダイ
オード等への利用価値が高い。
As explained above, the metal-semiconductor junction electrode manufactured by the method of the present invention is easy to manufacture, has a high reverse breakdown voltage, and can easily adjust the height of the Schottky barrier determined by the second layer material. Since it has advantages such as being able to obtain high voltage resistance, it has high utility value in high voltage diodes, level shift diodes in integrated circuits, and the like.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明により製造された金属半導体接合電極の
断面図、第2図は本発明及び従来技術による電極の順方
向電流電圧特性、第311′は本発明及び従来技術によ
る電極の逆方向電流電圧特性である。 1・・・ウェハ(半導体基板) 2・・・オーミック電極 3・・・チタニウム(Ti)!(第1層)4・・・窒化
チタニウム(TiN )層(第2層)5・・・チタニウ
ム(T1)層(第3層)6・・アルミニウム(Al)層
(第4層)7・・・本発明の実施例による電極の特性8
・・・従来技術による電極の特性 特許出願人 日本電信電話公社 代理人弁理士 中 村 純之助
FIG. 1 is a cross-sectional view of a metal semiconductor junction electrode manufactured according to the present invention, FIG. 2 is a forward current-voltage characteristic of the electrode according to the present invention and the prior art, and 311' is a reverse direction of the electrode according to the present invention and the prior art. This is the current-voltage characteristic. 1... Wafer (semiconductor substrate) 2... Ohmic electrode 3... Titanium (Ti)! (First layer) 4... Titanium nitride (TiN) layer (second layer) 5... Titanium (T1) layer (third layer) 6... Aluminum (Al) layer (fourth layer) 7...・Characteristics of the electrode according to the embodiment of the present invention 8
...Characteristics of electrodes based on conventional technology Patent applicant: Junnosuke Nakamura, patent attorney representing Nippon Telegraph and Telephone Public Corporation

Claims (1)

【特許請求の範囲】[Claims] 化合物半導体表面上に10乃至150穴の厚さを有する
チタニウムよりなる第1層を形成する工程と、該第1層
上にチタニウムの化合物又はチタニウムを含有する合金
よりなる第2層を形成する工程と、該第1層と該第2層
又は該第2層の形成中あるいは形成後に熱処理を行なう
工程を有することを特徴とした金属半導体接合電極の製
造方法。
A step of forming a first layer made of titanium having a thickness of 10 to 150 holes on the surface of a compound semiconductor, and a step of forming a second layer made of a titanium compound or an alloy containing titanium on the first layer. and a step of performing heat treatment during or after the formation of the first layer, the second layer, or the second layer.
JP13419681A 1981-08-28 1981-08-28 Manufacture of metal-semiconductor junction electrode Granted JPS5835919A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13419681A JPS5835919A (en) 1981-08-28 1981-08-28 Manufacture of metal-semiconductor junction electrode

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13419681A JPS5835919A (en) 1981-08-28 1981-08-28 Manufacture of metal-semiconductor junction electrode

Publications (2)

Publication Number Publication Date
JPS5835919A true JPS5835919A (en) 1983-03-02
JPH0139222B2 JPH0139222B2 (en) 1989-08-18

Family

ID=15122672

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13419681A Granted JPS5835919A (en) 1981-08-28 1981-08-28 Manufacture of metal-semiconductor junction electrode

Country Status (1)

Country Link
JP (1) JPS5835919A (en)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61224435A (en) * 1985-03-29 1986-10-06 Toshiba Corp Semiconductor device
JPH01179316A (en) * 1988-01-05 1989-07-17 Nec Corp Formation of electrode of compound semiconductor device
US4923827A (en) * 1988-05-16 1990-05-08 Eaton Corporation T-type undercut electrical contact process on a semiconductor substrate
US4935805A (en) * 1988-05-16 1990-06-19 Eaton Corporation T-type undercut electrical contact on a semiconductor substrate
JPH0396229A (en) * 1989-08-16 1991-04-22 American Teleph & Telegr Co <Att> Semiconductor device and method of manufacturing the same
JPH0463480A (en) * 1990-07-02 1992-02-28 Sharp Corp Group iii-v compound semiconductor device
US5278099A (en) * 1985-05-13 1994-01-11 Kabushiki Kaisha Toshiba Method for manufacturing a semiconductor device having wiring electrodes
JP2000513882A (en) * 1998-04-20 2000-10-17 ユニフェイズ レーザー エンタープライズ アーゲー Titanium nitride diffusion barrier for non-silicon technology and method

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55120132A (en) * 1979-11-30 1980-09-16 Sumitomo Electric Ind Ltd Manufacture of semiconductor element

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55120132A (en) * 1979-11-30 1980-09-16 Sumitomo Electric Ind Ltd Manufacture of semiconductor element

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61224435A (en) * 1985-03-29 1986-10-06 Toshiba Corp Semiconductor device
US5278099A (en) * 1985-05-13 1994-01-11 Kabushiki Kaisha Toshiba Method for manufacturing a semiconductor device having wiring electrodes
JPH01179316A (en) * 1988-01-05 1989-07-17 Nec Corp Formation of electrode of compound semiconductor device
US4923827A (en) * 1988-05-16 1990-05-08 Eaton Corporation T-type undercut electrical contact process on a semiconductor substrate
US4935805A (en) * 1988-05-16 1990-06-19 Eaton Corporation T-type undercut electrical contact on a semiconductor substrate
JPH0396229A (en) * 1989-08-16 1991-04-22 American Teleph & Telegr Co <Att> Semiconductor device and method of manufacturing the same
JPH0463480A (en) * 1990-07-02 1992-02-28 Sharp Corp Group iii-v compound semiconductor device
JP2000513882A (en) * 1998-04-20 2000-10-17 ユニフェイズ レーザー エンタープライズ アーゲー Titanium nitride diffusion barrier for non-silicon technology and method

Also Published As

Publication number Publication date
JPH0139222B2 (en) 1989-08-18

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