JPH0139222B2 - - Google Patents
Info
- Publication number
- JPH0139222B2 JPH0139222B2 JP56134196A JP13419681A JPH0139222B2 JP H0139222 B2 JPH0139222 B2 JP H0139222B2 JP 56134196 A JP56134196 A JP 56134196A JP 13419681 A JP13419681 A JP 13419681A JP H0139222 B2 JPH0139222 B2 JP H0139222B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- titanium
- metal
- electrode
- present
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000010936 titanium Substances 0.000 claims description 23
- 239000004065 semiconductor Substances 0.000 claims description 19
- 238000010438 heat treatment Methods 0.000 claims description 8
- 238000004519 manufacturing process Methods 0.000 claims description 8
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 6
- 229910052719 titanium Inorganic materials 0.000 claims description 6
- 238000000034 method Methods 0.000 claims description 5
- 150000001875 compounds Chemical class 0.000 claims description 4
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- 150000003609 titanium compounds Chemical class 0.000 claims description 3
- 239000000956 alloy Substances 0.000 claims 1
- 229910045601 alloy Inorganic materials 0.000 claims 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 10
- 229910052751 metal Inorganic materials 0.000 description 10
- 239000002184 metal Substances 0.000 description 10
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 7
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 6
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 6
- 230000004888 barrier function Effects 0.000 description 6
- 230000015556 catabolic process Effects 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- 239000010931 gold Substances 0.000 description 3
- 229910052759 nickel Inorganic materials 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 2
- 229910001069 Ti alloy Inorganic materials 0.000 description 2
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000007772 electrode material Substances 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000001257 hydrogen Substances 0.000 description 2
- 229910052739 hydrogen Inorganic materials 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 229910001020 Au alloy Inorganic materials 0.000 description 1
- 229910000927 Ge alloy Inorganic materials 0.000 description 1
- 229910011214 Ti—Mo Inorganic materials 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000005546 reactive sputtering Methods 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
Description
【発明の詳細な説明】
本発明は、チタン化合物やチタン合金を電極材
料とする金属半導体接合電極の製造方法に関する
ものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a metal semiconductor junction electrode using a titanium compound or a titanium alloy as an electrode material.
従来の金属半導体接合電極は、下地半導体（例
えばSi、GaAs等）上に直接金属層を設けて構成
したもの、又は下地半導体上にチタニウム（Ti）
層（第１層）を形成しさらにその上に金属層（第
２層）を設けて構成したものがある。 Conventional metal-semiconductor junction electrodes are constructed by forming a metal layer directly on a base semiconductor (e.g., Si, GaAs, etc.), or by depositing a metal layer directly on a base semiconductor (e.g., Si, GaAs, etc.), or by depositing a metal layer on a base semiconductor (such as titanium (Ti)).
Some devices are constructed by forming a layer (first layer) and further providing a metal layer (second layer) thereon.
このうち前者に於いては、後に示すように逆方
向耐圧が非常に低くなつたり、また、製造後の特
性のばらつきが多いために量産に適さないという
欠点があつた。 Among these, the former has disadvantages in that the reverse breakdown voltage is extremely low, as will be shown later, and that it is not suitable for mass production due to large variations in characteristics after manufacture.
一方、後者に於いては、Ti層の使用目的が第
２層の金属と下地半導体の間の応力を減少させ接
着力を増すことにあつたため、製造時の厚さ制御
が容易で歩留りも良いように、厚いTi層（例え
ば厚さ500Å）が用いられていた。従つて、第２
層の金属（電極材料）と半導体で決まる固有のシ
ヨツトキー障壁の高さと電気伝導特性を得ること
が出来ず、第１層のTiとで決まる特性が得られ
るだけであるという欠点があつた。 On the other hand, in the latter case, the purpose of using the Ti layer was to reduce the stress between the second layer metal and the underlying semiconductor and increase the adhesion strength, so it was easy to control the thickness during manufacturing and the yield was good. As such, thick Ti layers (eg, 500 Å thick) were used. Therefore, the second
The drawback was that it was not possible to obtain the inherent Schottky barrier height and electrical conductivity characteristics determined by the metal (electrode material) and semiconductor in the layer, but only the characteristics determined by the first layer of Ti.
本発明はこれらの欠点を解決するために、第１
層のTiの厚さを薄くして熱処理を行うことを特
徴としたものであり、以下図面を用いて詳細に説
明する。 In order to solve these drawbacks, the present invention
The feature is that the thickness of the Ti layer is reduced and heat treatment is performed, and will be explained in detail below with reference to the drawings.
第１図は本発明の実施列であり、熱処理直前の
段階まで製造された金属半導体接合電極の断面図
である。図において、１はｎ形砒化ガリウム
（GaAs）ウエハ、２はこのウエハ１の裏面に設
けた金・ゲルマニウム・ニツケル製オーミツクス
電極、３はチタニウム（Ti）層、（第１層）４は
窒化チタニウム（TiN）層（第２層）、５はTi層
（第３層）、６はアルミニウム（Al）層（第４層）
である。 FIG. 1 is a cross-sectional view of a metal-semiconductor junction electrode manufactured to the stage immediately before heat treatment, which is an embodiment of the present invention. In the figure, 1 is an n-type gallium arsenide (GaAs) wafer, 2 is an ohmic electrode made of gold, germanium, and nickel provided on the back side of this wafer 1, 3 is a titanium (Ti) layer, and (first layer) 4 is titanium nitride. (TiN) layer (second layer), 5 is Ti layer (third layer), 6 is aluminum (Al) layer (fourth layer)
It is.
次に本発明の製造方法の主要工程を説明する。 Next, the main steps of the manufacturing method of the present invention will be explained.
ウエハ１の裏面に金・ゲルマニウム合金を蒸
着し、次いでニツケルを蒸着し、その後水素雰
囲気中で加熱して金・ゲルマニウム・ニツケル
製オーミツク電極２を形成する。 A gold/germanium alloy is deposited on the back surface of the wafer 1, and then nickel is deposited, and then heated in a hydrogen atmosphere to form a gold/germanium/nickel ohmic electrode 2.
ウエハ１の表面に第１層となる厚さ100Åの
Ti層３を例えばスパツタ法で形成する。 A first layer with a thickness of 100 Å is deposited on the surface of wafer 1.
The Ti layer 3 is formed by, for example, a sputtering method.
上記第１層上に第２層となる厚さ500Åの
TiN層４を窒素プラズマ中でTiをリアクテイ
ブスパツタ法で形成する。 A second layer with a thickness of 500 Å is placed on top of the first layer.
The TiN layer 4 is formed by reactive sputtering of Ti in nitrogen plasma.
上記第２層上に第３層となる厚さ100ÅのTi
層５を例えばスパツタ法で形成する。 A third layer of Ti with a thickness of 100 Å is formed on the second layer above.
Layer 5 is formed, for example, by sputtering.
さらにその上に第４層として厚さ3000Åの
Al層６を例えば蒸着で形成する。 Furthermore, a fourth layer with a thickness of 3000 Å is added on top of that.
The Al layer 6 is formed, for example, by vapor deposition.
次に第１層から第４層で形成された電極を直
径200μｍの大きさに写真食刻法で整形する。
なお、この時点で第１図に示した断面構造とな
る。 Next, the electrodes formed from the first to fourth layers are shaped to a diameter of 200 μm by photolithography.
At this point, the cross-sectional structure shown in FIG. 1 is obtained.
その後450℃の水素雰囲気中にて30秒間の熱
処理を加える。なお、この熱処理工程は、第１
層と第２層又は第２層の形成中に行なつてもよ
い。 After that, heat treatment is applied for 30 seconds in a hydrogen atmosphere at 450°C. Note that this heat treatment step
It may be performed during formation of the layer and the second layer or the second layer.
以上の工程により本発明の金属半導体接合電極
が構成される。なお、各層の厚さ並びにその形成
方法については、本実施例に限定されるものでは
ない。 The metal semiconductor junction electrode of the present invention is constructed by the above steps. Note that the thickness of each layer and its formation method are not limited to those in this example.
第２図及び第３図は、裏面のオーミツク電極２
に対し表面の電極（Al層６）をそれぞれ正（順
方向）と負（逆方向）にバイアスした時に電流電
圧特性である。図において、７は上記の実施例す
なわち本発明の製造方法により作られた場合の代
表的な特性であり、８は従来技術すなわち第１層
に相当するTi層を用いないで作成した場合の代
表的な特性例である。 Figures 2 and 3 show the ohmic electrode 2 on the back side.
In contrast, current-voltage characteristics are obtained when the surface electrode (Al layer 6) is biased positively (forward direction) and negatively (reverse direction), respectively. In the figure, 7 is the typical characteristic when the product is manufactured using the above-mentioned example, that is, the manufacturing method of the present invention, and 8 is the typical characteristic when it is manufactured using the conventional technique, that is, without using the Ti layer corresponding to the first layer. This is an example of a typical characteristic.
第３図から、本発明による電極は、従来方法に
よる場合に比べ十分高い逆方向耐圧を有すること
が明らかである。本発明は上記の利点に加えさら
に次のような利点を有する。すなわち、第２図の
順方向特性から求まるシヨツトキー障壁の高さ
は、本発明の場合は0.9eVであり、この値は従来
方法の場合より0.3eV高くなつている。別に測定
した容量電圧特性から求めた障壁の高さは、両者
ともほとんど等しい値で1.1eVとなつていること
から、本実施例の順方向特性は従来技術の場合に
比べ格段に改善されていることが分かると共に、
第２層となるTiNとウエハのGaAsで決まる大き
な障壁の高さを示していることが分かる。ちなみ
に、TiのみをGaAs上に形成した金属半導体接合
電極の障壁の高さは、本実施例の値より0.2eV低
い値を示す。 It is clear from FIG. 3 that the electrode according to the present invention has a sufficiently higher reverse breakdown voltage than the electrode according to the conventional method. In addition to the above advantages, the present invention has the following advantages. That is, the height of the Schottky barrier determined from the forward characteristics shown in FIG. 2 is 0.9 eV in the case of the present invention, which is 0.3 eV higher than in the case of the conventional method. The barrier heights determined from the separately measured capacitance-voltage characteristics are almost the same for both, 1.1 eV, indicating that the forward characteristics of this example are significantly improved compared to the conventional technology. As I understand that,
It can be seen that this shows a large barrier height determined by the second layer of TiN and the wafer's GaAs. Incidentally, the barrier height of the metal semiconductor junction electrode formed only of Ti on GaAs is 0.2 eV lower than the value of this example.
上記の実施例に於いて、第１層のTi層３があ
るにも拘らず第２層の物質固有の特性が得られる
理由は、前記の熱処理により第１層のTiがGaAs
と接合を形成した後、第２層のTiNと反応する
ことにあると考えられる。Tiの厚さは、膜厚の
制御性と均一性および実用的に反応可能な厚さか
ら制限され10乃至150Åである。 In the above example, the reason why the properties unique to the material of the second layer are obtained despite the existence of the first Ti layer 3 is that the first layer of Ti is changed to GaAs by the heat treatment.
This is thought to be due to the reaction with the second layer of TiN after forming a bond with the TiN layer. The thickness of Ti is limited to 10 to 150 Å, which is limited by the controllability and uniformity of the film thickness and the thickness that allows practical reaction.
熱処理の条件は、前記の実施例に限らず、活性
化エネルギー1.3eVのアレニウス則で定まる450
℃30秒相当以上の熱処理でも同様の効果が得られ
ることを確認した。 The heat treatment conditions are not limited to the above examples, but are determined by Arrhenius law with an activation energy of 1.3 eV.
It was confirmed that similar effects could be obtained by heat treatment for 30 seconds or more at °C.
以上は、第２層にTiNを用いた例について述
べたが、TiNが高融点であるにも拘らず上記の
効果がでることから、上記の反応はTiNに固有
のものではなく、従つて、第２層はTiNに限ら
ず金属的性質を示すチタン化合物（例えばTiC
等）やチタン合金（例えばTi−Ｗ、Ti−Mo等）
の場合でもTiNの場合と同様であることが言う
までもない。 The above describes an example in which TiN is used in the second layer, but since the above effect is obtained even though TiN has a high melting point, the above reaction is not unique to TiN, and therefore, The second layer is not limited to TiN, but also titanium compounds that exhibit metallic properties (for example, TiC).
etc.) and titanium alloys (e.g. Ti-W, Ti-Mo, etc.)
Needless to say, the situation is similar to that of TiN.
さらに、上記の説明は良好な表面状態を得にく
い化合物半導体に共通の技術であるため、半導体
基板（ウエハ１）は上記の例にあつたGaAsに限
定されるものではなく、例えばGaAlAs、GaP等
であつてもよい。 Furthermore, since the above explanation is a common technique for compound semiconductors where it is difficult to obtain a good surface condition, the semiconductor substrate (wafer 1) is not limited to GaAs as in the above example, but may include GaAlAs, GaP, etc. It may be.
以上説明したように、本発明の方法により製造
された金属半導体接合電極は、製造が容易である
こと、高い逆方向耐圧を有すること、第２層の物
質で定まるシヨツトキー障壁の高さを容易に得ら
れること等の利点を有するため、高耐圧ダイオー
ド、集積回路内のレベルシフトダイオード等への
利用価値が高い。 As explained above, the metal-semiconductor junction electrode manufactured by the method of the present invention is easy to manufacture, has a high reverse breakdown voltage, and can easily adjust the height of the Schottky barrier determined by the material of the second layer. Because of these advantages, it is highly useful for high voltage diodes, level shift diodes in integrated circuits, and the like.
第１図は本発明により製造された金属半導体接
合電極の断面図、第２図は本発明及び従来技術に
よる電極の順方向電流電圧特性、第３図は本発明
及び従来技術による電極の逆方向電流電圧特性で
ある。
１……ウエハ（半導体基板）、２……オーミツ
ク電極、３……チタニウム（Ti）層（第１層）、
４……窒化チタニウム（TiN）層（第２層）、５
……チタニウム（Ti）層（第３層）、６……アル
ミニウム（Al）層（第４層）、７……本発明の実
施例による電極の特性、８……従来技術による電
極の特性。
FIG. 1 is a cross-sectional view of a metal semiconductor junction electrode manufactured according to the present invention, FIG. 2 is a forward current-voltage characteristic of the electrode according to the present invention and the prior art, and FIG. 3 is a reverse direction diagram of the electrode according to the present invention and the prior art. This is the current-voltage characteristic. 1... Wafer (semiconductor substrate), 2... Ohmic electrode, 3... Titanium (Ti) layer (first layer),
4...Titanium nitride (TiN) layer (second layer), 5
... Titanium (Ti) layer (third layer), 6 ... Aluminum (Al) layer (fourth layer), 7 ... Characteristics of the electrode according to the embodiment of the present invention, 8 ... Characteristics of the electrode according to the prior art.
Claims (1)
有するチタニウムよりなる第１層を形成する工程
と、該第１層上にチタニウムの化合物またはチタ
ニウムを含有する合金よりなる第２層を形成する
工程と、該第１層と該第２層または該第２層の形
成中あるいは形成後に、該化合物半導体と該第１
層の反応を起こさせかつ該第２層が該化合物半導
体と接するのに要する時間の熱処理を行う工程を
有することを特徴とした金属半導体接合電極の製
造方法。1. A step of forming a first layer made of titanium having a thickness of 10 to 150 Å on the surface of a compound semiconductor, and a step of forming a second layer made of a titanium compound or an alloy containing titanium on the first layer. and the compound semiconductor and the first layer during or after the formation of the first layer and the second layer or the second layer.
A method for manufacturing a metal-semiconductor junction electrode, comprising the step of performing heat treatment for a time required for causing a reaction in the layer and for the second layer to come into contact with the compound semiconductor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13419681A JPS5835919A (en) | 1981-08-28 | 1981-08-28 | Manufacture of metal-semiconductor junction electrode |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13419681A JPS5835919A (en) | 1981-08-28 | 1981-08-28 | Manufacture of metal-semiconductor junction electrode |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5835919A JPS5835919A (en) | 1983-03-02 |
| JPH0139222B2 true JPH0139222B2 (en) | 1989-08-18 |
Family
ID=15122672
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13419681A Granted JPS5835919A (en) | 1981-08-28 | 1981-08-28 | Manufacture of metal-semiconductor junction electrode |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5835919A (en) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH061774B2 (en) * | 1985-03-29 | 1994-01-05 | 株式会社東芝 | Semiconductor device |
| US5278099A (en) * | 1985-05-13 | 1994-01-11 | Kabushiki Kaisha Toshiba | Method for manufacturing a semiconductor device having wiring electrodes |
| JPH0732146B2 (en) * | 1988-01-05 | 1995-04-10 | 日本電気株式会社 | Method for forming electrode of compound semiconductor device |
| US4923827A (en) * | 1988-05-16 | 1990-05-08 | Eaton Corporation | T-type undercut electrical contact process on a semiconductor substrate |
| US4935805A (en) * | 1988-05-16 | 1990-06-19 | Eaton Corporation | T-type undercut electrical contact on a semiconductor substrate |
| US5036023A (en) * | 1989-08-16 | 1991-07-30 | At&T Bell Laboratories | Rapid thermal processing method of making a semiconductor device |
| JPH0463480A (en) * | 1990-07-02 | 1992-02-28 | Sharp Corp | Group iii-v compound semiconductor device |
| US6204560B1 (en) * | 1998-04-20 | 2001-03-20 | Uniphase Laser Enterprise Ag | Titanium nitride diffusion barrier for use in non-silicon technologies and method |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS55120132A (en) * | 1979-11-30 | 1980-09-16 | Sumitomo Electric Ind Ltd | Manufacture of semiconductor element |
-
1981
- 1981-08-28 JP JP13419681A patent/JPS5835919A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS55120132A (en) * | 1979-11-30 | 1980-09-16 | Sumitomo Electric Ind Ltd | Manufacture of semiconductor element |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5835919A (en) | 1983-03-02 |
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