JPS61224435A - Semiconductor device - Google Patents

Abstract

PURPOSE:To suppress the reaction of the high-melting point metal layer with the silicon layer or the atmosphere gas by a method wherein the high-melting point metal CONSTITUTION:N-type inversion preventing layers 33 are formed in parts of the surface of a substrate 31, which are located under field oxide films 32, a thermal oxidation.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor device, and more particularly to a semiconductor device in which an electrode wiring portion of an insulated gate field effect transistor is improved.

[Technical background of the invention and its problems] Conventionally, insulated gate field effect transistors (hereinafter referred to as MO
It is called an S transistor. ) is manufactured by the following process.

First, as shown in FIG. 2('a), a field oxide film 12 is formed on an n-type silicon substrate 11 with a plane orientation (100), and an n-type inversion prevention layer 13 is formed on the surface of the substrate 11 under the field oxidation film 112. Form. Subsequently, as shown in FIG. 2B, a thermal oxidation process is performed to form a layer with a thickness of 10 mm on the island region (device region) of the substrate 11 separated by the field oxide film 12.
0 to 500 gate oxide films 14 are formed. Subsequently, after depositing polycrystalline silicon doped with n-type impurities over the entire surface and patterning to form the gate electrode 15,
Using the gate electrode 15 and field oxide film 12 as a mask, a p-type impurity, such as boron, is ion-implanted and activated to form a p+-type source region 16 and drain region 17 separated from each other in the island region of the substrate 11. .

Next, as shown in FIG. 1C, after depositing a CVD-3i02 film 18, forming a contact hole 19, depositing A1, and buttering, the source and drain regions 16, 11 and the contact hole 19 are formed.
Form A1 wiring 20 and 21 to connect through the MoS
Manufacture transistors.

According to the method described above, by forming the gate electrode 15 from polycrystalline silicon, the p+ type source and drain regions 16.11 can be formed in self-alignment with the gate electrode 15 using the gate electrode 15 as a mask. Moreover, it has the feature that high temperature heat treatment for activation can be applied after the step of forming the gate electrode 15.

However, even when polycrystalline silicon is doped with impurities at a high concentration, the resistivity decreases by only about 10°3Ωα, which limits high-speed operation in fine devices.

Furthermore, as the degree of integration of elements increases, the depth of the source and drain diffusion layers becomes shallower, and the resistance of the diffusion layers increases due to the formation of shallower junctions. These things increase the parasitic resistance of the transistor and have a wide impact on the transistor characteristics.

For this reason, it is possible to use a metal or metal silicide instead of a polycrystalline silicon film for the gate electrode, or to use a combination of a polycrystalline silicon film and a metal silicide layered on the polycrystalline silicon film for the gate electrode. Formation using a layered structure is also practiced.

When metal is used directly, the metal and silicon or interlayer insulating film often react with each other during a thermal process, and subsequent processes must be performed at low temperatures, which often limits applications. Therefore, metal silicides are now often used.

Examples of metal silicides include Pt, Ti, and Mo5W.

Silicides such as T8 are used, and titanium silicides are particularly promising because of their low resistance.

As a method for forming metal silicide on the source and drain regions and the gate electrode mentioned above, for example, Japanese Patent Laid-Open No. 57-9
The method described in US Pat. No. 9,775 is known. That is, first, S is deposited on a silicon substrate on which a gate electrode is formed.
After depositing an iO2 film and selectively removing portions of the SiO2 film corresponding to the source, drain regions and gate electrodes, a metal film is deposited over the entire surface. Next, heat treatment is performed at a predetermined temperature to cause a metal silicide formation reaction only on the source and drain regions and the gate electrode, and then the unreacted metal film is selectively etched away to form the source and drain regions. A metal silicide is formed on the region and on the gate electrode.

However, when attempting to form titanium silicide by such a method, there are problems as shown below.

Usually, as a method for forming a metal silicide, heat treatment in an inert gas is adopted in consideration of productivity and the like. In this case, titanium is a highly reactive substance, as can be seen from the fact that it is used as a getter material in a vacuum.
Reacts with oxygen in inert gas to form an oxide film. In this case, it is best to use a normal diffusion furnace to eliminate oxygen leakage. Therefore, titanium becomes an oxide during heat treatment, making it difficult to form titanium silicide with good controllability. As a result, the sheet resistance of titanium silicide varies from several Ω/hole to several Ω/hole, resulting in a decrease in the yield of LSI.

[Object of the Invention] The present invention has been made in view of the above circumstances, and its purpose is to provide a material that is made of a high melting point metal or a high melting point metal silicide, has low sheet resistance, and does not react with atmospheric gas, etc. An object of the present invention is to provide a semiconductor device having an electrode wiring structure that can be stably formed.

[Summary of the Invention] The present invention is applicable to a semiconductor device in which a MoS transistor is formed on a semiconductor substrate, for example, and is used on a source or drain region provided on the main surface of the semiconductor substrate, or on a gate electrode or wiring. A first titanium nitride layer is disposed on the non-single crystal silicon layer, and a refractory metal layer is disposed on the first titanium nitride layer. Further, a second titanium nitride layer is disposed on the high melting point metal layer, an insulating layer is disposed on the side surface of the high melting point metal layer, and a protective film is disposed on the second titanium nitride layer. It is.

With such a structure, since the active high melting point metal is covered with the titanium nitride layer and the insulating layer, the reaction between the high melting point metal and silicon or atmospheric gas can be suppressed.

[Embodiment of the Invention] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. First, as shown in FIG. 1(a), a field oxide film 32 is formed on an n-type silicon substrate 31 with a plane orientation (100), and an n-type film is formed on the surface of the substrate 31 under the field oxide film 32.
A mold reversal prevention layer 33 is formed.

Subsequently, thermal oxidation treatment is performed to form the field oxidation 1I.
A gate oxide film 34 having a thickness of 100 to 500 wafers is formed on the island region (device region) of the substrate 31 separated by the gate oxide film 32 . Subsequently, as shown in FIG. 2B, a polycrystalline silicon film 35 doped with n-type impurities is deposited on the entire surface, and then, for example, a titanium target is sputtered in a nitrogen atmosphere.
A titanium nitride layer 36 is formed by 200 people. Next, 2000 titanium layers 37 are deposited by sputtering in an argon atmosphere. Subsequently, 200 layers of titanium nitride layer 38 are deposited again, and then a non-single crystal silicon film 39 doped with n+ impurities is deposited.

After that, patterning is performed to form a gate electrode 40, and then an n-type impurity, such as boron, is ion-implanted using the gate electrode 40 and field oxide film 32 as a mask to form a p+ source region 41 and a drain region 42. .

Next, as shown in the same figure (C), plasma CVD (C
chemical vapor deposition
) followed by CVD-8i
After depositing 0244, the contact hole 45 is opened,
A is connected to the source and drain regions 41 and 42 through the contact hole 45 by vapor deposition and patterning of A1.
One wiring 46 and 47 are formed to manufacture a MOS transistor.

In the above MOS transistor, the active titanium layer 37 is replaced by a titanium nitride layer 36, 38 and a 5102 film 4.
3, so the reaction between titanium and silicon,
It becomes possible to suppress the reaction between titanium and a gas atmosphere such as oxygen, and titanium can be used as a gate electrode. Therefore, the thickness of the titanium layer 3γ is 40
In the case of 00 people, the sheet resistance is 4Ω/mouth, which is about 20 times lower than that when polycrystalline silicon is used. Therefore, when used as a word line of a memory, for example, it is possible to realize an increase in the speed of the element.

For example, even when titanium J137 is made of 1000 layers, the sheet resistance is about 5 times lower than that of a polycrystalline silicon film, and a flatter structure can be realized.

Although titanium was used as the high melting point metal in the above embodiments, the invention is not limited to this.
Tungsten, molybdenum, zirconium, tantalum, etc., and silicides thereof may also be used. Further, in the above embodiments, an example in which the present invention is applied to the structure of a gate electrode has been described, but it goes without saying that the present invention may also be applied to a wiring portion.

' [Effects of the Invention] As described above, according to the present invention, stable low sheet resistance electrodes and wiring that are made of a refractory metal or a refractory metal silicide and that do not react with silicon or atmospheric gas can be obtained. structure can be formed.

[Brief explanation of drawings]

FIG. 1 is a sectional view showing the manufacturing process of a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a sectional view showing the manufacturing process of a conventional semiconductor device. 31... N-type silicon substrate, 34... Gate oxide film, 35... Polycrystalline silicon film, 36... Titanium nitride layer, 37... Titanium layer, 38... Titanium nitride layer, 39 ...Non-single crystal silicon film, 40...
Gate electrode, 41...source region, 42...drain region. Applicant's representative Patent attorney Takehiko Suzue Figure 1 Figure 2

Claims (4)

[Claims] (1) A non-single crystal silicon layer provided on one main surface of a semiconductor substrate via an insulating film, a first titanium nitride layer provided on this non-single crystal silicon layer, and a first titanium nitride layer provided on the non-single crystal silicon layer, and a layer containing a high melting point metal provided on the titanium layer; an insulating layer covering a side surface of the layer containing the high melting point metal; and a second titanium nitride layer provided on the layer containing the high melting point metal. , and a protective film provided on the second titanium nitride layer. (2) The high melting point metal is titanium, tungsten,
The semiconductor device according to claim 1, which is any one of molybdenum, zirconium, and tantalum, or a mixture thereof. (3) The semiconductor device according to claim 1 or 2, wherein the protective film is formed of non-monocrystalline silicon. (4) The semiconductor device according to claim 1 or 2, wherein the protective film is made of silicon oxide.