JP3238804B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device having a silicide formed by alloying a refractory metal and Si.

[0002]

2. Description of the Related Art In a highly integrated MOSIC,
The wiring resistance is increasing due to the reduction of the wiring width and the increase of the wiring length due to the high integration, and particularly, the reduction of the operation speed due to the increase of the wiring resistance of the gate electrode has become a problem. Therefore, in order to reduce the wiring resistance and improve the operation speed, instead of the conventional gate electrode made of polycrystalline Si, a silicide generated by alloying a refractory metal and Si is made of polycrystalline Si.
A gate electrode having a polycide structure laminated thereon is being used.

As a method of forming a gate electrode having the polycide structure, a gate oxide film is formed on a semiconductor substrate by a thermal oxidation method, and a polycrystalline Si film is formed on the gate oxide film by a reduced pressure chemical vapor deposition method. An impurity is introduced into the polycrystalline Si film to add conductivity, and a high melting point metal layer is formed on the polycrystalline Si film by sputtering or chemical vapor deposition to form these layers. The semiconductor substrate is subjected to heat treatment to form a silicide film by alloying the refractory metal layer and Si, thereby reducing the resistance.
A method of patterning these films by a well-known dry etching method to form a gate electrode is known (for example, see Japanese Patent Publication No. 61-95516).

In the above method, a stable oxide film (SiO.sub.2) is formed on a surface of a silicide film constituting a gate electrode by a heat treatment process.
₂ ) is formed, but in the subsequent patterning step, the side surface of the silicide film is exposed without a stable oxide film formed. It is known that when the silicide film is exposed to an oxidizing atmosphere in a bare state, the silicide film is deteriorated and peels off. For this reason, when the silicide film is bare, heat treatment conditions and film deposition conditions in the subsequent steps are known. Is severely limited and causes inconvenience.

Therefore, in order to solve this problem, first, patterning for forming a gate electrode is performed.
Immediately thereafter, a method has been proposed in which a heat treatment for forming a silicide film is performed to form a stable oxide film on the surface and side surfaces of the silicide film. However, according to this method, a large internal stress is generated in the silicide film, whereby the stress is concentrated on the lower end portion of the gate electrode and the breakdown voltage of the gate oxide film is deteriorated. For this reason, conventionally, the polycrystalline S
The i film is formed to a thickness of 2000 angstroms or more to reduce stress concentration and prevent the gate oxide film from deteriorating withstand voltage.

[0006]

However, in the above-mentioned method of forming the polycrystalline Si film to a thickness of 2000 Å or more, the step of the gate electrode is increased by the thickness of the polycrystalline Si film. As a result, there is a problem that the accuracy of the subsequent wafer process is reduced. on the other hand,
When the polycrystalline Si film is thinned, there is a problem that the breakdown voltage of the gate oxide film is deteriorated as described above.

SUMMARY OF THE INVENTION In view of the above circumstances, the present invention provides a method of manufacturing a semiconductor device capable of preventing a gate oxide film from deteriorating withstand voltage even if a polycrystalline Si layer constituting a gate electrode is made thinner than a conventional one to reduce a step of the gate electrode. The aim is to provide a method.

[0008]

According to the present invention, there is provided a method of manufacturing a semiconductor device, comprising the steps of: (1) forming an oxide film on a semiconductor substrate; (2) Step of forming a polycrystalline Si film on the oxide film (3) Step of depositing a mixture of metal and Si on the polycrystalline Si film to form a mixed film composed of the mixture (4) ) A step of patterning the polycrystalline Si film and the mixed film; (5) a step of forming an insulating film on the semiconductor substrate after the patterning is completed; and (6) a heat treatment of the semiconductor substrate on which the insulating film is formed. Forming a silicide by alloying the mixed film.

[0009]

In order to solve the above-mentioned problem, the present inventors investigated the stress distribution when forming the gate electrode by computer simulation. The results are shown in FIGS. FIG. 1 is a diagram showing the distribution of tensile stress when a heat treatment for silicidation is performed after patterning of the gate electrode 10, and FIG. 2 is a diagram showing an example in which an insulating film is deposited after patterning of the gate electrode 10 and then silicidation is performed. FIG. 5 is a view showing a distribution of tensile stress when heat treatment of FIG.
2, thickness of 1500 Å, silicide layer 1
The thickness of No. 4 was set to 2000 angstroms.

According to FIGS. 1 and 2, the tensile stress caused by the volume reduction during the silicidation causes the gate oxide film 16 at the lower end of the gate electrode 10 to undergo heat treatment after patterning of the gate electrode 10. In contrast, when the insulating film 18 was deposited and heat-treated after patterning of the gate electrode 10, it was found that the tensile stress was hardly present in the gate oxide film 16.

Based on this finding, after patterning a mixed film composed of a mixture of metal and Si or a two-layer film composed of a polycrystalline Si film and a metal film, an insulating film is formed on a semiconductor substrate, and this semiconductor substrate is formed. By forming a silicide layer by heat treatment, even if the polycrystalline Si film constituting the gate electrode is made thinner than before and the step of the gate electrode is reduced, the concentration of stress on the gate oxide film can be reduced. Deterioration of breakdown voltage of the gate oxide film is prevented.

[0012]

Embodiments of the present invention will be described below with reference to the drawings. 3 to 8 are sectional views showing one embodiment of a method for manufacturing a semiconductor device according to the present invention. Here, an embodiment applied to the manufacture of an N-channel MOSFET will be described. First, as shown in FIG. 3, the device active region 24 separated by the device isolation insulating film 22 formed on the Si substrate 20
A gate insulating film 26 made of SiO ₂ is formed by a thermal oxidation method, and a 1500 angstrom thick polycrystalline Si film 28 is formed on the element isolation insulating film 22 and the gate insulating film 26 by a well-known low-pressure chemical vapor deposition method. Formed, and the polycrystalline Si
On the film 28, a mixed film 30 made of a mixture of Mo and Si
Is formed by sputtering or chemical vapor deposition. After these films are formed, as shown in FIG. 4, the polycrystalline Si film 28 and the mixed film 30 are patterned into a layer 32 in the shape of a gate electrode by well-known photoetching. Next, as shown in FIG. 5, using the element isolation insulating film 22 and the layer 32 as a mask, an impurity (for example, P) having a conductivity type opposite to the conductivity type of the Si substrate 20 is ion-implanted into the Si substrate 20 and n
^- to form an impurity implanted region 34. Next, as shown in FIG. 6, an insulating film 36 made of SiO ₂ is formed on the entire surface of the Si substrate 20 by well-known CVD. Next, annealing is performed by an infrared lamp heating device (not shown), and as shown in FIG.
Then, a low-resistance gate electrode 40 composed of the silicide film 38 and the polycrystalline Si film 28a is formed. Next, FIG.
As shown in FIG. 2, the insulating film 36 is etched back by anisotropic etching to form a side wall oxide film 36a on the side wall of the gate electrode 40, and using the side wall oxide film 36a and the element isolation insulating film 22 as a mask, Impurities (for example, As) of a conductivity type opposite to the conductivity type of the Si substrate 20 are ion-implanted into the Si substrate 20 and annealing for activation is performed to form an n ⁺ impurity implantation region 42. Thereafter, a PSG film (not shown) is formed by CVD as an interlayer insulating film, and N
Annealing is performed at 900 ° C. in _two atmospheres, an opening for taking out an electrode (not shown) is formed in a predetermined region using a known processing technique, and a predetermined Al alloy wiring (not shown) is formed. To manufacture an N-channel type MOSFET.

Next, the MOS manufactured by the method of the above embodiment will be described.
The breakdown voltage distribution of the FET gate insulating film 26 (see FIG. 8)
A description will be given in comparison with a breakdown voltage distribution of a gate insulating film of a MOSFET manufactured by a conventional method. FIG. 9 shows a conventional MOSFE in which a gate electrode having a polycrystalline Si film having a thickness of 1500 angstroms is formed by annealing and silicidation immediately after forming the shape of the gate electrode by etching.
FIG. 10 is a graph showing the breakdown voltage distribution of the gate insulating film of the MOSFET manufactured by the method of the above embodiment. As shown in these figures, even if the thickness of the polycrystalline Si film constituting the gate electrode is 1500 angstroms, the MO manufactured by the method of the present embodiment is obtained.
The withstand voltage of the gate insulating film of the SFET has been improved, and the withstand voltage failure of the LSI can be drastically reduced as compared with the conventional method.

[0014]

As described above, according to the method of manufacturing a semiconductor device of the present invention, an insulating film is formed on a semiconductor substrate prior to a heat treatment for silicidation, and then a heat treatment for silicidation is performed. Even if the polycrystalline Si film constituting the gate electrode is made thinner than before so as to reduce the step of the gate electrode, concentration of stress on the gate oxide film can be reduced, and deterioration of the breakdown voltage of the gate oxide film can be prevented. Thereby, the product yield of MOS transistors can be improved. Further, since the polycrystalline Si film constituting the gate electrode can be made thinner than before, it greatly contributes to miniaturization of the MOS transistor.

[Brief description of the drawings]

FIG. 1 is a diagram showing a distribution of tensile stress when a heat treatment for silicidation is performed after patterning of a gate electrode.

FIG. 2 is a diagram showing the distribution of tensile stress when an insulating film is deposited after patterning of a gate electrode and then heat treatment for silicidation is performed.

FIG. 3 is a cross-sectional view illustrating one embodiment of a method of manufacturing a semiconductor device according to the present invention, showing a state where an element isolation insulating film, a gate insulating film, a polycrystalline Si film, and a mixed film are formed on a Si substrate. .

FIG. 4 is a cross-sectional view showing a state where the shape of the gate electrode is formed by patterning the semiconductor device in the state shown in FIG. 3;

FIG. 5 is a cross-sectional view showing a state where ions are implanted into the semiconductor device in the state shown in FIG. 4 to form an n ⁻ impurity implantation region.

FIG. 6 is a cross-sectional view showing a state where an insulating film is formed on the semiconductor device in the state shown in FIG. 5;

FIG. 7 is a cross-sectional view showing a state where a heat treatment is performed on the semiconductor device in the state shown in FIG. 6 to form a silicide film;

8 is a cross-sectional view showing a state in which a sidewall oxide film is formed on the semiconductor device in the state shown in FIG. 7 and an n ⁺ impurity implantation region is formed.

FIG. 9 is a graph showing a breakdown voltage distribution of a gate insulating film of a conventional MOSFET in which a gate electrode is formed by annealing and silicidation immediately after a gate electrode is formed by etching.

FIG. 10 shows a MOSFE manufactured by the method according to the embodiment of the present invention.
4 is a graph showing a breakdown voltage distribution of a gate insulating film of T.

[Explanation of symbols]

 Reference Signs List 20 Si substrate 26 Gate insulating film 28 Polycrystalline Si film 30 Mixed film 36 Insulating film 38 Silicide film

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-3-24732 (JP, A) JP-A-2-130830 (JP, A) JP-A-61-259573 (JP, A) JP-A-4- 207025 (JP, A) JP-A-4-199629 (JP, A) JP-A-62-296468 (JP, A) JP-A-61-174628 (JP, A) (58) Fields investigated (Int. ⁷ , DB name) H01L 21/28 301 H01L 29/78

Claims (2)

(57) [Claims] 1. A method of manufacturing a semiconductor device having silicide formed therein, comprising: forming an oxide film on a semiconductor substrate; forming a polycrystalline Si film on the oxide film; Forming a mixed film of the mixture by depositing a mixture of metal and Si; patterning the polycrystalline film and the mixed film; forming an insulating film on the semiconductor substrate after the patterning is completed. Performing a heat treatment on the semiconductor substrate on which the insulating film is formed, thereby alloying the mixed film to form a silicide. 2. The method according to claim 1, wherein the insulating film is formed by mixing the patterned mixture.
It is formed directly on the top and side surfaces of the composite film.
A method for manufacturing a semiconductor device according to claim 1.