JPH07115194A - Manufacture of semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To improve the oxidation-resistance of the high melting point metal silicide film of a gate electrode by a method wherein a part of an oxidation- resistant film is formed on the surface of the high melting point metal silicide of the gate electrode and then processes such as a heat treatment for forming source and drain regions, etc., are carried out. CONSTITUTION:A gate electrode 5 is formed on a gate insulating film 4 formed on the active region of a p-type semiconductor substrate l. Then low concentration n-type impurities 6n are introduced into the active region of the substrate 1 with the electrode 5 and a field insulating film 2 as a mask. After an oxidation-resistant film 70 is formed over the whole surface of the substrate 1, the film 70 is subjected to anisotropic etching to the extent not reading the full film thickness and a part 71 of the film 70 is left on the top surface of the electrode 5. After a mask 10 is formed on the film 71, an-isotropic etching is performed again to the extent corresponding to the remaining thickness of the electrode 5. The mask 10 is removed and, after high impurity concentration n-type semiconductor regions 9 are formed in source and drain forming regions, the film 71 is removed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a technique effectively applied to a semiconductor integrated circuit device having an insulated gate field effect transistor.

[0002]

2. Description of the Related Art MOSFETs (Metal Oxide Semiconductors) mounted on semiconductor integrated circuit devices such as ICs and LSIs
In the ctor Field Effect Transistor, a composite film in which a refractory metal silicide film is laminated on a polycrystalline silicon film is used as a gate electrode material. WS as a high melting point metal silicide film
Any one of i, MoSi, TiSi, etc. is used. The refractory metal silicide film has a smaller resistance than a single-layer gate electrode of a polycrystalline silicon film, and can speed up the switching speed of the MOSFET.

Further, the above-mentioned MOSFET is a so-called LDD (L) for the purpose of preventing a short channel effect due to high integration.
ightly Doped Drain) structure is adopted.

A manufacturing method of a MOSFET adopting this LDD structure is shown in FIGS.

First, as shown in FIG. 7, a gate insulating film 4 is formed on the active region of the main surface of the p-type semiconductor substrate 1, and a gate electrode 5 is formed on the gate insulating film 4. The active region of the semiconductor substrate 1 is defined by being surrounded by the field insulating film 2 and the p-type channel stopper region 3 formed in the inactive region of the semiconductor substrate 1. A silicon oxide film formed by a thermal oxidation method is used as the gate insulating film 4. The gate electrode 5 comprises a refractory metal silicide film 5 on the polycrystalline silicon film 5A.
B, for example, a composite film in which WSi films are laminated.

Next, as shown in FIG. 8, the gate electrode 5 and the field insulating film 2 are used as a main body of a mask, and a low concentration n-type impurity for forming an LDD structure in the active region of the main surface of the semiconductor substrate 1. Introduce 6n. The n-type impurity 6n is
It is introduced into the main surface portion of the semiconductor substrate 1 by an ion implantation method through an insulating film (an insulating film formed in the same step as the gate insulating film 4). The n-type impurity 6n is introduced in self alignment with the gate electrode 5.

Next, as shown in FIG. 9, a sidewall spacer 7 is formed on the sidewall of the gate electrode 5. The sidewall spacer 7 is formed by depositing a silicon oxide film by a CVD method and anisotropically etching the entire surface of the silicon oxide film by an amount corresponding to the deposited film thickness. The sidewall spacer 7 is formed in self-alignment with the gate electrode 5. The n-type impurity 6n is slightly expanded and diffused by heating or the like when forming the silicon oxide film to form the low-concentration n-type semiconductor region 6.

Next, as shown in FIG. 10, the semiconductor substrate 1
A high-concentration n-type semiconductor region 9 is formed on the main surface portion of, and a source region and a drain region having the n-type semiconductor regions 6 and 9 are formed. The high-concentration n-type semiconductor region 9 is formed by using the gate electrode 5, the field insulating film 2 and the sidewall spacers 7 as a main mask and introducing an n-type impurity by an ion implantation method. The introduction of the n-type impurities is performed through the silicon oxide film 8 previously formed by the high temperature thermal oxidation method or the high temperature deposition method for the purpose of preventing contamination, preventing damage, and the like.

When the source region and the drain region are formed, the MOSFET adopting the LDD structure is completed.

[0010]

However, the above-mentioned L
The following points are not taken into consideration in the MOSFET adopting the DD structure.

(1) The refractory metal silicide film 5B used for the gate electrode 5 of the MOSFET has a property that its composition is changed by heat treatment, thermal oxidation treatment or the like. In particular, since the step of forming the silicon oxide film of the sidewall spacers 7 after the formation of the gate electrode 5 is accompanied by heat treatment at high temperature,
The refractory metal silicide film 5B is crystallized from an amorphous state. At this time, the oxidation resistance of the refractory metal silicide film 5B is suddenly weakened, and an oxide film is formed on the surface layer of the refractory metal silicide film 5B due to abnormal oxidation.

Further, since the silicon oxide film on the gate electrode 5 is completely removed after the formation of the sidewall spacers 7, the surface of the refractory metal silicide film 5B is exposed. The exposed surface of the refractory metal silicide film 5B is exposed to a high temperature heat treatment atmosphere for forming the silicon oxide film 8 or a high temperature oxidation treatment atmosphere. Therefore, similarly to the above, an oxide film is generated due to abnormal oxidation on the surface layer of the refractory metal silicide film 5B, and in the worst case, the oxide film is peeled off.

(2) In the step of forming the side wall spacer 7, over-etching is performed when anisotropically etching the silicon oxide film. However,
Since the silicon oxide film forming the sidewall spacers 7 and the insulating film (silicon oxide film) formed in the active region of the main surface of the semiconductor substrate 1 are the same insulating material,
The etching selectivity cannot be secured. At the same time, a sufficient etching selectivity cannot be secured between each of these silicon oxide film and silicon (semiconductor substrate 1). Therefore, the active region of the semiconductor substrate 1 (region where the source region and the drain region are formed) is abnormally over-etched.

The present invention has been made to solve the above-mentioned problems, and it is an object of the present invention to provide a MISFET (Metal Ins) adopting the LDD structure of a semiconductor integrated circuit device.
ulator Semiconductor Field Effect Transisto
In r), the following objects (1) to (3) are achieved.

(1) The oxidation resistance of the refractory metal silicide film of the gate electrode is improved.

(2) Over-etching at the time of forming the sidewall spacer is reduced.

(3) The number of manufacturing steps is reduced.

[0018]

In order to achieve such an object, (1) the present invention provides a method for manufacturing a semiconductor integrated circuit device having a MISFET, wherein the main surface of the first conductivity type semiconductor region is formed. Forming a gate electrode having at least a refractory metal silicide film in the gate electrode forming region via a gate insulating film; and forming the gate insulating film over the entire main surface of the semiconductor region including the gate electrode. A step of forming an oxidation resistant film capable of ensuring an etching selection ratio with respect to the film,
An amount corresponding to the thickness of the formed oxidation resistant film is anisotropically etched on the entire surface of the oxidation resistant film, and a part of the oxidation resistant film is left on the upper surface of the gate electrode, Forming a sidewall spacer of the oxidation resistant film on the sidewall of the gate electrode, and using the gate electrode and the sidewall spacer as a mask,
Introducing a second conductivity type impurity into the main surface of the semiconductor region,
A step of activating this impurity, forming a source region and a drain region, and forming a MISFET.

(2) Further, in the present invention, the step of forming the gate electrode is a step of forming a composite film in which a refractory metal silicide film is laminated on a single layer of a refractory metal silicide film or a polycrystalline silicon film. The step of forming the gate insulating film is a step of forming a silicon oxide film, and the step of forming the oxidation resistant film is a step of forming a silicon nitride film.

(3) Further, in the present invention, the step of forming each of the oxidation resistant coating and the sidewall spacer left on the upper surface of the gate electrode is performed by anisotropic etching on the entire surface of the oxidation resistant coating. And a part of the oxidation resistant film is left on the upper surface of the gate electrode, and an etching mask is formed through a part of the oxidation resistant film left on the gate electrode. Again, the entire surface of the oxidation resistant film is subjected to anisotropic etching, and a part of the oxidation resistant film is left unetched on the upper surface of the gate electrode, and the side wall of the gate electrode It is characterized in that it is a step of forming a sidewall spacer.

[0021]

The present invention provides the following actions (1) to (3).

(1) MISF adopting the LDD structure
In ET, since a part of the oxidation resistant film is formed on the surface of the refractory metal silicide film of the gate electrode, and then a step such as heat treatment for forming the source region and the drain region is performed, the refractory metal silicide film is formed. It is possible to prevent oxides from being generated on the surface portion of the film and to prevent the oxides from peeling off.

(2) Since the sidewall spacers are formed of an oxidation resistant film capable of ensuring an etching selection ratio with respect to the gate insulating film, the gate insulating film functions as an etching stopper film when the sidewall spacers are formed, Overetching of the semiconductor region (semiconductor substrate) can be reduced.

(3) Since the step of forming the oxidation resistant film can also be used as a part of the step of forming the sidewall spacers, the number of manufacturing steps can be reduced by the amount corresponding to this combined step.

[0025]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment of the present invention will be described below with reference to the drawings.

A method of manufacturing a main part of a semiconductor integrated circuit device having a MISFET according to an embodiment of the present invention will be shown in FIGS. 1 to 6 (cross-sectional views of main parts in each step).

First, as shown in FIG. 1, a gate insulating film 4 is formed on the active region of the main surface of a p-type semiconductor substrate (or well region) 1 made of single crystal silicon, and the gate insulating film 4 is formed.
The gate electrode 5 is formed on top. The active region of the semiconductor substrate 1 is defined by being surrounded by the field insulating film 2 and the p-type channel stopper region 3 formed in the inactive region of the semiconductor substrate 1.

As the gate insulating film 4, a silicon oxide film formed by a thermal oxidation method is used. For example, when the 0.5 μm manufacturing process is adopted (when the gate length of the MISFET is 0.5 μm), the gate insulating film 4 has a thickness of 10 to 15 nm.
It is formed with a film thickness of about.

The gate electrode 5 is formed of a composite film in which a refractory metal silicide film 5B is laminated on a polycrystalline silicon film 5A. The polycrystalline silicon film 5A is deposited by, for example, a low temperature low pressure CVD (LPCVD) method using SiH ₂ Cl ₂ as a source gas.
It is formed with a film thickness of 0 nm. After the deposition, the polycrystalline silicon film 5A is introduced with an n-type impurity that reduces the resistance value, for example, P, and is heat-treated for activation at 800 ° C. for 2 hours.

As the refractory metal silicide film 5B, a WSi film is used in this embodiment. Refractory metal silicide film 5B
Basically, any of MoSi, TiSi and the like may be used. The refractory metal silicide film 5B is deposited by the CVD method or the sputtering method to have a film thickness of 150 nm.

The gate electrode 5 is a polycrystalline silicon film 5A,
After depositing each of the refractory metal silicide films 5B, patterning is performed using photolithography technology and anisotropic etching technology.

Next, as shown in FIG. 2, the gate electrode 5 and the field insulating film 2 are used as a main body of a mask, and a low concentration n-type impurity that forms an LDD structure in the active region of the main surface of the semiconductor substrate 1. Introduce 6n. The n-type impurity 6n is
It is introduced into the main surface portion of the semiconductor substrate 1 by an ion implantation method through an insulating film (an insulating film formed in the same step as the gate insulating film 4). The n-type impurity 6n is introduced in self alignment with the gate electrode 5.

Next, as shown in FIG. 3, an oxidation resistant film 70 is formed on the entire surface of the semiconductor substrate 1 including the gate electrode 5. The oxidation resistant film 70 is formed of a film having oxidation resistance and capable of ensuring an etching selection ratio with respect to the gate insulating film 4 (silicon oxide film), which is a silicon nitride film in this embodiment. This silicon nitride film is, for example, SiH ₂ Cl ₂
And deposited by LPCVD using NH ₃ as source gas,
It is formed with a substantially uniform film thickness of 150 nm.

Next, the oxidation resistant coating 70 is provided to the extent that it does not reach the thickness corresponding to the deposited thickness of the oxidation resistant coating 70.
Is subjected to anisotropic etching to leave a part 71 of the oxidation resistant film 70 in the film thickness direction on the upper surface of the gate electrode 5. The remaining part of the oxidation resistant coating 71 is formed to have a film thickness such that the oxidation resistance, that is, the passage of oxygen can be prevented, specifically, a film thickness of about 10 nm. At this stage, the sidewall spacers (72) are almost finished. Further, a part of the oxidation resistant film 70 is left on the respective formation regions of the source region and the drain region and on the field insulating film 3.

Next, as shown in FIG. 4, an etching mask 10 is formed on the remaining oxidation resistant film 71, that is, on the gate electrode 5. The etching mask 10 is formed for the purpose of preventing the thickness of the oxidation resistant film 71 on the gate electrode 5 from being reduced by further etching. The etching mask 10 is formed of, for example, a photosensitive resin film formed by a photolithography technique.

Next, the etching mask 10 is used, and anisotropic etching is performed again on the entire surface of the oxidation resistant coating 70 by an amount corresponding to the finally deposited film thickness of the oxidation resistant coating 70. As a result, sidewall spacers 72 made of the oxidation resistant coating 70 are formed on the sidewalls of the gate electrode 5. At this time, the oxidation resistant film 7 on the gate electrode 5
1 is left by the etching mask 10. Also,
In each of the formation regions of the source region and the drain region, the silicon oxide film (the insulating film formed in the same step as the gate insulating film 4) acts as an etching stopper film when the oxidation resistant coating 70 is anisotropically etched. , Over-etching of the active region of the semiconductor substrate 1 can be reduced.
The sidewall spacer 72 is formed in self alignment with the gate electrode 5. The n-type impurities 6n are slightly stretched and diffused by heating or the like when forming the oxidation resistant film 70 to form the low-concentration n-type semiconductor region 6.

Next, the etching mask 10 is removed. Then, as shown in FIG. 5, a high-concentration n-type semiconductor region 9 is formed in the main surface portion of the semiconductor substrate 1 in each of the source region and drain region formation regions. The n-type semiconductor region 9 is formed by using the gate electrode 5, the field insulating film 2 and the sidewall spacer 72 as a main mask and introducing an n-type impurity by an ion implantation method. The n-type impurities are stretched and diffused by high temperature heat treatment. At this time, the refractory metal silicide film 5 of the gate electrode 5
Since the upper surface of B is coated with the oxidation resistant coating 71 and the side walls thereof are coated with the sidewall spacers 72, the oxidation resistance becomes extremely good.

Further, the silicon oxide film (4) used as the etching stopper film is left in the formation regions of the source region and the drain region, and n-type impurities are introduced through the left silicon oxide film. Therefore, when the n-type impurities are introduced, the formation of the silicon oxide film for the purpose of preventing pollution, preventing damage, etc. can be eliminated, and the high temperature treatment and the high temperature thermal oxidation treatment can be eliminated.

When the high-concentration n-type semiconductor region 9 is formed, the source region having the low-concentration n-type semiconductor region 6 is formed,
Each of the drain regions is formed, and as a result, the MISFET adopting the LDD structure is completed.

Next, as shown in FIG. 6, the oxidation resistant film 71 on the gate electrode 5 is removed, and thereafter, although not shown, an interlayer insulating film, a connection hole, and an aluminum alloy wiring are sequentially formed. To do. The oxidation resistant coating 71 is
When forming the connection hole, the shape of the connection hole may be removed together.

As described above, according to this embodiment,
In the MISFET adopting the LDD structure, a part 71 of the oxidation resistant coating 70 is formed on the surface of the refractory metal silicide film 5B of the gate electrode 5, and then a heat treatment for forming a source region and a drain region is performed. Because the process is performed
It is possible to prevent an oxide from being generated on the surface portion of the refractory metal silicide film 5B or to prevent the oxide from peeling off.

Further, since the side wall spacers 72 are formed of the oxidation resistant film 70 capable of ensuring the etching selection ratio with respect to the gate insulating film 4, the gate insulating film 4 is etched by the etching stopper when the side wall spacers 72 are formed. It functions as a film and can reduce over-etching of the semiconductor region 9 (semiconductor substrate 1).

Further, since the step of forming the oxidation resistant film 71 can also be used as a part of the step of forming the sidewall spacer 72, the number of manufacturing steps can be reduced by the amount corresponding to this combined step.

The present invention is not limited to the above-mentioned embodiment, but various modifications can be made without departing from the scope of the invention. For example, the present invention provides an n-channel MISF.
Although it is applied to the ET, it can be applied to either the p-channel MISFET or the complementary MISFET.

[0045]

As described above, according to the present invention, the following effects (1) to (3) can be obtained in the MISFET adopting the LDD structure of the semiconductor integrated circuit device. (1) The oxidation resistance of the refractory metal silicide film of the gate electrode can be improved. (2) Over-etching at the time of forming the sidewall spacer can be reduced.

(3) The number of manufacturing steps can be reduced.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of essential parts in a first step of a semiconductor integrated circuit device including a MISFET that is an embodiment of the present invention.

FIG. 2 is a cross-sectional view of a main part in a second step.

FIG. 3 is a cross-sectional view of main parts in a third step.

FIG. 4 is a cross-sectional view of main parts in a fourth step.

FIG. 5 is a main-portion cross-sectional view in a fifth step.

FIG. 6 is a sectional view of a key part in a sixth step.

FIG. 7 is a main-portion cross-sectional view of a semiconductor integrated circuit device including a conventional MOSFET in a first step.

FIG. 8 is a main-portion cross-sectional view in the second step.

FIG. 9 is a cross-sectional view of main parts in a third step.

FIG. 10 is a sectional view of a key portion in a fourth step.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 4 Gate insulating film 5 Gate electrode 5A Polycrystalline silicon film 5B Refractory metal silicide film 6,9 Semiconductor region 70,71 Oxidation resistant film 72 Sidewall spacer

Claims (3)

[Claims] 1. A method of manufacturing a semiconductor integrated circuit device having an insulated gate field effect transistor, comprising: a gate electrode formation region on a main surface of a first conductivity type semiconductor region; A step of forming a gate electrode having a metal silicide film, and an oxidation resistant film capable of ensuring an etching selection ratio with respect to the gate insulating film, over the entire main surface of the semiconductor region including on the gate electrode. The step of forming and the amount of film thickness of the formed oxidation resistant film is anisotropically etched on the entire surface of the oxidation resistant film, and a part of the oxidation resistant film is formed on the upper surface of the gate electrode. And forming a sidewall spacer of the oxidation resistant film on the side wall of the gate electrode, and using the gate electrode and the sidewall spacer as a mask Introducing a second conductivity type impurity into the main surface of the semiconductor region, activating the impurity, forming a source region and a drain region, and forming an insulated gate field effect transistor. Method for manufacturing semiconductor integrated circuit device. 2. The step of forming the gate electrode according to claim 1, wherein the step of forming the gate electrode is a single layer of a refractory metal silicide film or a composite film in which a refractory metal silicide film is laminated on a polycrystalline silicon film. A step of forming the gate insulating film, a step of forming a silicon oxide film, and a step of forming the oxidation resistant film is a step of forming a silicon nitride film. Method for manufacturing semiconductor integrated circuit device. 3. The step of forming each of the oxidation resistant coating and the sidewall spacer left on the upper surface of the gate electrode according to claim 1 or 2, wherein the entire surface of the oxidation resistant coating is formed. Anisotropic etching is performed on the top surface of the gate electrode, and a part of the oxidation resistant film is left on the upper surface of the gate electrode, and an etching mask is formed through a part of the oxidation resistant film left on the gate electrode. Formed, using the etching mask, anisotropic etching is performed again on the entire surface of the oxidation resistant film, and a part of the oxidation resistant film is left unetched on the upper surface of the gate electrode, and A method of manufacturing a semiconductor integrated circuit device, comprising the step of forming the sidewall spacer on a sidewall of a gate electrode.