JPS58101454A - Electrode for semiconductor device - Google Patents

Electrode for semiconductor device

Info

Publication number
JPS58101454A
JPS58101454A JP56199489A JP19948981A JPS58101454A JP S58101454 A JPS58101454 A JP S58101454A JP 56199489 A JP56199489 A JP 56199489A JP 19948981 A JP19948981 A JP 19948981A JP S58101454 A JPS58101454 A JP S58101454A
Authority
JP
Japan
Prior art keywords
layer
tin
substrate
electrode
prevented
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56199489A
Other languages
Japanese (ja)
Other versions
JPH033395B2 (en
Inventor
Masamichi Mori
金森周一
Shuichi Kanamori
森正道
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP56199489A priority Critical patent/JPS58101454A/en
Publication of JPS58101454A publication Critical patent/JPS58101454A/en
Publication of JPH033395B2 publication Critical patent/JPH033395B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To stabilize the ageing variation of a contactor resistance by superposing Al which contains TiN and Cu on an ohmic contact layer or a Schottky junction layer, thereby preventing a void from forming due to electromigration. CONSTITUTION:A window is opened at an SiO2 film 2 on a diffused layer 8 of an Si substrate 1, Ti 3 is sputtered in Ar, TiN 4 is superposed by a reactive sputtering method in atmosphere having Ar and N or 5:1 of pressure dividing ratio, is annealed at 450 deg.C in N2, Ti4Si3 is formed in the boundary between Si and Ti as an ohmic contact. Then, Al 7 which contains Cu is covered by a sputtering method on the TiN4. The range of containing Cu is 0.5-16wt%. According to this structure, Cu is segregated in Al grain boundary, thereby suppressing electromigration along the grain boundary. Accordingly, the production of voids can be prevented, thereby reducing the ageing variation in the contacting resistance. Since the TiN is interposed and Si diffusion is prevented from the substrate, the void in the substrate can be prevented, thereby obtaining stable electrode in large current.

Description

【発明の詳細な説明】 4−、#51#0%千尋体装置ycおいて、筒い耐熱性
會南し、大嵐流省展に鮒えるオーミック接触または7ヨ
ツト一?振合會提供する電極vc圓するものである0 健米、尚い−I熱性t−有し、大電流省度に耐えるオー
ミンク熾雁1次にショットキ振合としては。
[Detailed description of the invention] 4-, #51 #0% Chihiro body device yc, the tube heat resistant meeting south, Ohmic contact that can be enjoyed in the great storm style exhibition or 7 yachts? The swinging meeting provides an electrode VC circle which is 0 healthy, yet has -I thermal T-, and can withstand large current savings as a Schottky swing of the first order.

第11rこ不すように、拡散層8を設けたシリコン千尋
体基板(Si趣板)1とのコンタクトに、ナタ7 (’
l”i )ま7jは白金シリサイド(PtSi)を第1
層3と(7て用イ、第2HIkVC−化fJlン(T>
N)4、第3層にアルミニウム(At)5を用いるよう
・に栴成嘔れていた。図中2は杷鍼層(Bias) t
−不丁〇しかし、このような1ih成を行りても、大−
6tm度の電*’r辿電すると、電流が流れ込む十−(
図示の場合は上ll11)フンタクトの電極において、
第3層アルミニウム5かエレクトロマイクレージョン【
起し、第2図に示すようK s第3階のアルミニウムの
矢先したボイド6が形成される。このようなホイド杉成
によって、抵抗体となる拡散層8が実効的rC延ひるこ
と、実効的なコンタクト向槙か縮小することによって、
コンタクト部分の抵抗が増大し%経時変動か赳きる。
At the 11th point, a machete 7 ('
l”i) or 7j is platinum silicide (PtSi) as the first
Layer 3 and (7), 2nd HIkVC-ization
N) 4. It was proposed to use aluminum (At) 5 for the third layer. 2 in the figure is the loquat layer (Bias) t
- Inappropriate〇However, even if you do this kind of 1ih formation, it will be a big deal.
When an electric current of 6 tm degrees is traced, the current flows into the
In the case shown above,
3rd layer aluminum 5 or electromicration [
As shown in FIG. 2, a void 6 is formed in the aluminum of the third stage. Due to such formation, the effective rC of the diffusion layer 8 serving as a resistor is extended, and the effective contact width is reduced.
The resistance of the contact portion increases and may change over time.

このLうvc、第319IIVCエレクトロマイクレー
ジヨン耐蓋の小さいアルミニウムを用いた榊敗でに、エ
レクトロマ1クレーショ/Vcよるボイド°形敗C(よ
ってコンタクト部分の抵抗が社時[11起こ)不安定f
!1:′に壱する欠点がおった。
Due to this Lvc, 319th IIVC electromicration using a small aluminum lid, voids caused by the electromigration/Vc (therefore, the resistance of the contact part was reduced to 11%). stable f
! 1:' had one drawback.

17t、他の一つの方法としては、第3凶?こ示すよう
に、拡tk層8會設り゛たS1基板1に鯖入リアルミニ
クム(Cu入りA/、、)7N−麹嫉做触させ、安定化
を図るように構成されていたが、MとSi基板の反応お
よびエレクトロマイクレージョンによって第4凶にホj
ようKhCu人9M電憔7電他i基板のコ/タクト■W
仁ホイド9が形成場れ、このボイド9を(よって上配嵐
極栴奄と同様の社時賀動會匙丁欠点かめった。
17t, Another method is the third evil? As shown in the figure, the S1 substrate 1 on which eight expanded Tk layers were provided was made to contact with Sabari Real Minicum (Cu-containing A/...) 7N-koji malt to stabilize it. Due to the reaction between the Si substrate and the electromicration, the fourth
YoKhCu person 9M electric 7 electric and other i board co/tact ■W
Ninhoid 9 was formed, and this Void 9 (therefore, it had the same disadvantage as the upper Arashi Gokusei).

1九に未第5凶に不すようV(拡散層8を弔するSi丞
ml上にSi人9AL電憔lOをl扶接触させて一敗名
7L’tいたものがめるが、大電流を流子と、1ラス1
1L+jlL、l1lIllのコンタクト向にボイド1
1が池数されBIA敏抵抗抵失効的の置場が魅ひること
が餡められ。
In 19th, I brought the Si person 9 AL electric gas into contact with the Si layer 8 to avoid the fifth damage, but a large current was generated. Ryuko and 1st 1st
Void 1 in the contact direction of 1L + jlL, l1lIll
1 is the number of ponds, and it is believed that the BIA resistance and resistance will be attractive.

このため峠#f雀動を匙こ丁欠点かわった0向図中12
はSi粒をボテ。
For this reason, 12 in the 0-direction map where the pass #f sparrow was replaced with a spoon defect.
Use Si grains.

本宛明龜、これらの欠点金除去するために、第3%のM
の代vvこ、エレクトロマイクレージョン−1朧に丁ぐ
jしたCu入9 AL f用い、エレクトロマイクレー
ジョンVCよ心ホ゛イド形成*U*コンタクト帥分の抵
抗の鮭時変(転)の安定化を図ること金目的とする。
To this end, in order to remove these defects, 3% M
In this case, electromicration VC was used to form a core hoid using 9 AL f containing finely divided Cu. The goal is to make money.

前記の目的伊達欲するため5不発vAはオーミック接触
層又はショットキ嵌合mk含む半導体基板と、前記のオ
ーミック接触層又はショットキ修合増上VC形成さrし
た線化チタン鳩と%#配の電化ナタン鳩上に形成された
銅入りアルミニウム鳩と倉惜えることt−%徴とする半
導体装置の嵐惚を発明の資旨とするものである。
In order to achieve the above purpose, 5 unexploded VA is made of a semiconductor substrate containing an ohmic contact layer or Schottky mating MK, a VC formed on the ohmic contact layer or Schottky mating, and a wired titanium dome and an electrified natan dome of % # distribution. The gist of the invention is to develop a semiconductor device with a copper-containing aluminum dovetail formed on top and a t-% characteristic.

次に本祐稠の実施?IJを硝附図面Vこついて説明する
。なお実施例は一つの例示でわって1本発明の精神會逸
脱しない範囲内で%柚々の変史多るいU改良を行いうる
ことは云うまでもない。
Next is the implementation of Motosuke? IJ will be explained with reference to the attached drawing V. It goes without saying that the embodiments are merely illustrative, and that numerous modifications can be made without departing from the spirit of the present invention.

第6図は本発明の半導体装置の電極の寮hガであって1
図yc寂いて、1にSi基板、2はIi8縁課。
FIG. 6 shows the structure of the electrode of the semiconductor device of the present invention.
Figure yc lonely, 1 is Si substrate, 2 is Ii8 edge section.

3にTiまたはPt Si% 4に’I’s N h 
 fは0人9M、8は拡散層でめる0 このように構成すると、入電tILvf展の電流を通−
して%Cu人!JAL’lとbi & * 1との反%
n、TiN/#に4で紺止δiL%Cu人9M自身にエ
レクトロマイクレージョン耐蓋にすぐれているため、第
2図に示すようlホイド杉成%防止される0したかつて
1コンタクト跡分の抵抗が経時変動しない安定な電4k
k倚るCとができる0 ここでTi 3は熱処理により、Siと反応し、硅化チ
タンを形成する。この反応層かオーミック黴触層又はシ
ョットキ黴合層として働くo拡散層の鎖良の鎖度が為い
場合は、オーミック接触になり、績度が低い場合に、シ
ョットキ振合となるO仄に不発明の電極の袈造方法會第
7図−)〜(f)について&川する0 (1)図に示すようK 8i基板IK拡歓層8を形成せ
(2め、ついで(b)図に示すように上面に絶縁II 
8i 0x2を杉敗し、公知の方法によpii!、縁膜
2にコンタクトホール13i形敗する(C幽参照)0次
に(d)図に示すように上山にス/1ツタ法によりTi
層3を池数する0これにアルゴン雰囲気内で圧力16.
8 wa Torr (/J ”’Fで、RFF力40
0Wで竹なわれ、厚δ約50OAのTi層が形成された
0次Vこ(e)凶1c示すように2反応性スノくツタ法
により’llI+3上にTiN層4を形成するOこれi
j Ar : 拠=5 : 1 (分圧比)の#囲気で
圧力16.8 vm Torrの)で、RF亀方力40
0W行われ、厚さ約500^のTiN鳩4が池数された
0ついでN、雰囲気内で450C、10分間焼鈍し 8
1とTiとの界面にチタンシリサイドを形成し、オーミ
ックコンタクトとする0次K(f)図に示すようにTi
N層4上にスパッタ法によpCu入9紅層7を形成する
0 この場合%Cu入りM中の伽のiiは重量Sで表わ丁と
、0.5N−16XかmtしvhOこの場合、龜の含有
蓋が0.5X以下ではエレクトロマイクレージョンがお
こり中子<、m他たる伽入りのM中にボイドが発生し、
このため、コンタクト部分の抵抗の経時変動tおこしや
すい0また伽が16%以上ではボンティングする際にボ
ンティング部分で電他材料とボンティングワイヤ材料の
相互拡散がおこりrc<<なり、ボンティング部分の頚
層性が急くなる欠点かめるからである。
3 Ti or Pt Si% 4 'I's N h
f is 0 and 9M, and 8 is the diffusion layer. With this configuration, the current of the incoming current tILvf is passed through -
%Cu people! The opposite % between JAL'l and bi & * 1
n, TiN/#4 is dyed with δiL% Cu, which has excellent electromicrition resistance, as shown in Figure 2. A stable electric current whose resistance does not change over time.
Here, Ti 3 reacts with Si by heat treatment to form titanium silicide. If the chain strength of this reaction layer or the diffusion layer that acts as an ohmic contact layer or a Schottky contact layer is not good, it will become an ohmic contact, and if the performance is low, it will become a Schottky vibration. (1) Form the IK expansion layer 8 on the K8i substrate as shown in Figure 7-) to (f) (2nd, then (b)) Insulation II on the top surface as shown in
8i 0x2 and pii! by a known method! , a contact hole 13i is formed in the marginal film 2 (see C). Next, as shown in Figure (d), Ti is formed on the upper mountain by the S/1 ivy method.
Layer 3 is placed at a pressure of 16.0 in an argon atmosphere.
8 wa Torr (/J”'F, RFF force 40
A Ti layer with a thickness of about 50 OA is formed by 0W. As shown in (e) 1c, a TiN layer 4 is formed on 'llI+3 by the two-reactive snow vine method.
j Ar: Base = 5:1 (partial pressure ratio) #surrounding pressure of 16.8 vm Torr), RF force 40
TiN pigeon 4 with a thickness of about 500^ was subjected to 0W and then annealed in N atmosphere at 450C for 10 minutes 8
As shown in the zero-order K(f) diagram, titanium silicide is formed at the interface between
A pCu-containing layer 7 is formed on the N layer 4 by a sputtering method. In this case, the ii in the % Cu-containing M is expressed by the weight S, and 0.5N-16X or mt is vhO in this case. , If the lid containing the barrel is less than 0.5X, electromicration will occur and voids will occur in the M with the shell inside the core.
For this reason, when the resistance of the contact part tends to change over time t is more than 16%, interdiffusion of the electrical material and the bonding wire material occurs in the bonding part, resulting in rc<<, and the bonding This is because there is a disadvantage that the neck layer of the part becomes abrupt.

本発明の電極fC寂いて、電極構成として、TiN/ 
Ti kはさんたCu入りのMとする理由は次のような
根拠にもと丁くtのでわる0 (IJ  ALfSl入9M咎の電他では1Mの粒界に
沿うてエレクトロマイグレーションをおこすか、1人9
のMではMの粒界に(1が偏析し1粒界に沿ったエレク
トロマイグレーションを抑制するため−ボイドの発生t
−防止できコンタクト部分の抵抗の経時変動を少くする
ことかできる。
The electrode fC of the present invention has a TiN/
The reason for selecting M with interspersed Cu is based on the following grounds. 9 per person
In the case of M, since 1 segregates at the grain boundaries of M and suppresses electromigration along the 1 grain boundaries, voids occur t
- It is possible to prevent the change in resistance of the contact portion over time.

(IIJ  Cu入9A1.と81か直嵌振触しておら
す、TiNがSi基板〃≧らCu入りの)−1m物への
Siの拡散を防ぐ役割を釆た丁ので81中でのボイドの
発生音防止できる。
(IIJ Cu-containing 9A1. and 81 are directly fitted and shaken. TiN serves to prevent Si from diffusing into the -1m Si substrate (with Cu)), so there are voids in 81. The noise generated can be prevented.

(Ill)  又Ti Bオーミックコンタクトをと9
やすくするための役割t−米たす。
(Ill) Also, with Ti B ohmic contact 9
Role to make it easier T-rice table.

以上の塩山によるものである。This is due to the above-mentioned Shioyama.

第8凶yc亀健として、従来糸のM/慣N/Ti電極お
よびへ入9AL@他と本発明の一例であるCu入9 A
L/ Ti N / Ti電極を用いた約lOΩの拡散
抵抗について、入電a@度の亀ILky&電した場合の
経時tmk比較して示す。この場合本発明品に、M中1
の宮4g鎗は4重重九でるり、各階の厚さはCu人9A
L層Ja 1.5 p 、TiN層fi 500 A、
a層$j 500^でめる0区験粂杆はコンタクトの電
流智度4 X 10’A / ct、抵抗体のに度30
0℃でるる。
As the 8th yc Kameken, conventional yarn M/N/Ti electrode and Heiri 9AL@etc. and Cu containing 9A which is an example of the present invention.
Regarding the diffusion resistance of approximately 10Ω using L/TiN/Ti electrodes, the graph shows a comparison of time-lapse tmk when current is applied at a@degree. In this case, in the product of the present invention, 1 in M
Nonomiya 4g spear is 4 layers and 9 layers, the thickness of each floor is Cu person 9A
L layer Ja 1.5 p, TiN layer fi 500 A,
A-layer $j 500^ The 0-section test rod has a contact current of 4 x 10'A/ct, and a resistor current of 30
It's 0℃.

この図〃為ら、明らかなように、従来技術で娶る@l−
の第3層のALfエレクトロマイクレージョン耐量の丁
ぐれた0人9klに代えることによって、きわめて安定
な電極になることがわかる。
As is clear from this figure, it is clear that @l-
It can be seen that an extremely stable electrode can be obtained by replacing the third layer with 0.9 kl, which has a poor ALf electromicration resistance.

以上vt明したように、不発#!Aによればコンタクト
部分の抵抗が安定な電極であるため、大1に流會過篭す
るハイパワートランジスタ、ハイパワーICの電極とし
て利用できるほか、局密匿化、機軸化によるai6亀流
密流密度るLSIの^安定な電離として利用できる利点
がるる。特に、従来1lib′!pI度のために個別部
品の抵抗で代用嘔れてぃたアナログLSIの入電R通電
下で篇稽度が資求される高相度拡散抵抗の安定なIK憾
として用いることができる利点かある。
As explained above, misfire #! According to A, since the contact part is an electrode with stable resistance, it can be used as an electrode for high-power transistors and high-power ICs that are used in large quantities, and it can also be used as an electrode for high-power transistors and high-power ICs. There is an advantage that it can be used as stable ionization of LSI with high current density. In particular, the conventional 1lib'! It has the advantage of being able to be used as a stable IK resistor for high-phase diffused resistors, which require high controllability when current is applied to analog LSIs, which are used as a substitute for individual component resistors due to the pI degree. .

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は梃米の電極、帛2−はボイド発生状態、@3図
は同じ〈従来の電極、第4−はボイド発生電極%第5図
は同じく従来の電極を示す。第6図は本@明の電極を示
し、第7゛図(a)〜(f)はその皺造工根を示し、第
8図は、従来の11に徳と本発明の電極を用いたlOΩ
拡散抵抗の通電試験における経時変imt示し7′cも
のである。 1・・・・・・シリコン基板、2・・・・・・絶一層、
3・・・・・・チタン層、4・・・・・・富化チタン、
5・・・・・・アルミニウム電極、6・・・・・・ボイ
ド、7・・・・・・銅入9AL、8・・・・・・拡散層
、9 ・・・ボイド、lO・・・・・・Sl入9 AL
、11−−ボイド、 12・・・・・・Si′B%13
・・・・・・コンタクトホール特許出願人 日不電傷電
鮎公社 第111 第2図 第3図 第4図 第6図
Fig. 1 shows a levered electrode, Fig. 2 shows a state in which voids are generated, Fig. 3 shows the same conventional electrode, and Fig. 4 shows a void-generated electrode. Fig. 5 also shows a conventional electrode. Figure 6 shows the electrode according to the present invention, Figures 7 (a) to (f) show its wrinkled roots, and Figure 8 shows the electrode of the present invention used in contrast to the conventional 11. lOΩ
This figure shows the time-dependent change imt in the current conduction test of the diffused resistor. 1... Silicon substrate, 2... Absolute layer,
3... Titanium layer, 4... Enriched titanium,
5...Aluminum electrode, 6...Void, 7...9AL containing copper, 8...Diffusion layer, 9...Void, lO... ...Sl containing 9 AL
, 11--void, 12...Si'B%13
・・・・・・Contact Hole Patent Applicant: Nichifu Denkiden Ayu Corporation No. 111 Figure 2 Figure 3 Figure 4 Figure 6

Claims (1)

【特許請求の範囲】[Claims] オーミンク候M鳩又にショットキ接谷層會含む′p碑捧
#板と1削配のオーミック像触層又にショットキ嵌合階
上に形成された窒化チタン層と、割礼の迩化ナタン層上
に杉成塾nた勤人リアルミニウム増とt−匍χることを
物音とする半導体装置の亀4110
The Schottky contact layer is included in the Ohminck-like layer and the titanium nitride layer formed on the Schottky contact layer and the excised Ohmic contact layer, and the titanium nitride layer formed on the Schottky contact layer and the circumcision Natan layer. Semiconductor device turtle 4110, which makes noises due to the increase in the number of real aluminum workers who went to Suginarijuku school.
JP56199489A 1981-12-12 1981-12-12 Electrode for semiconductor device Granted JPS58101454A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56199489A JPS58101454A (en) 1981-12-12 1981-12-12 Electrode for semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56199489A JPS58101454A (en) 1981-12-12 1981-12-12 Electrode for semiconductor device

Publications (2)

Publication Number Publication Date
JPS58101454A true JPS58101454A (en) 1983-06-16
JPH033395B2 JPH033395B2 (en) 1991-01-18

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Application Number Title Priority Date Filing Date
JP56199489A Granted JPS58101454A (en) 1981-12-12 1981-12-12 Electrode for semiconductor device

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Country Link
JP (1) JPS58101454A (en)

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6074675A (en) * 1983-09-30 1985-04-26 Fujitsu Ltd Semiconductor device
JPS6190445A (en) * 1984-10-09 1986-05-08 Nec Corp Semiconductor device
JPS61224435A (en) * 1985-03-29 1986-10-06 Toshiba Corp Semiconductor device
JPS61263159A (en) * 1985-03-15 1986-11-21 フエアチヤイルド セミコンダクタ コ−ポレ−シヨン High temperature mutual connection for integrated circuit
EP0209654A2 (en) * 1985-05-13 1987-01-28 Kabushiki Kaisha Toshiba Semiconductor device having wiring electrodes
JPS6255929A (en) * 1985-09-05 1987-03-11 Toshiba Corp Manufacture of semiconductor device
JPS62219921A (en) * 1986-03-20 1987-09-28 Mitsubishi Electric Corp Semiconductor device
US5155063A (en) * 1990-10-09 1992-10-13 Nec Corporation Method of fabricating semiconductor device including an al/tin/ti contact
US5240880A (en) * 1992-05-05 1993-08-31 Zilog, Inc. Ti/TiN/Ti contact metallization
US5278099A (en) * 1985-05-13 1994-01-11 Kabushiki Kaisha Toshiba Method for manufacturing a semiconductor device having wiring electrodes
US6051490A (en) * 1991-11-29 2000-04-18 Sony Corporation Method of forming wirings
US6268290B1 (en) * 1991-11-19 2001-07-31 Sony Corporation Method of forming wirings
US8168996B2 (en) 2006-04-17 2012-05-01 Nichia Corporation Semiconductor light emitting device

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS507430A (en) * 1973-05-18 1975-01-25
JPS5024596A (en) * 1973-02-20 1975-03-15
JPS5271174A (en) * 1975-12-10 1977-06-14 Fujitsu Ltd Production of semiconductor device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5024596A (en) * 1973-02-20 1975-03-15
JPS507430A (en) * 1973-05-18 1975-01-25
JPS5271174A (en) * 1975-12-10 1977-06-14 Fujitsu Ltd Production of semiconductor device

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6074675A (en) * 1983-09-30 1985-04-26 Fujitsu Ltd Semiconductor device
JPS6190445A (en) * 1984-10-09 1986-05-08 Nec Corp Semiconductor device
JPS61263159A (en) * 1985-03-15 1986-11-21 フエアチヤイルド セミコンダクタ コ−ポレ−シヨン High temperature mutual connection for integrated circuit
JPS61224435A (en) * 1985-03-29 1986-10-06 Toshiba Corp Semiconductor device
US5278099A (en) * 1985-05-13 1994-01-11 Kabushiki Kaisha Toshiba Method for manufacturing a semiconductor device having wiring electrodes
EP0209654A2 (en) * 1985-05-13 1987-01-28 Kabushiki Kaisha Toshiba Semiconductor device having wiring electrodes
JPS6255929A (en) * 1985-09-05 1987-03-11 Toshiba Corp Manufacture of semiconductor device
JPS62219921A (en) * 1986-03-20 1987-09-28 Mitsubishi Electric Corp Semiconductor device
US5155063A (en) * 1990-10-09 1992-10-13 Nec Corporation Method of fabricating semiconductor device including an al/tin/ti contact
US6268290B1 (en) * 1991-11-19 2001-07-31 Sony Corporation Method of forming wirings
US6051490A (en) * 1991-11-29 2000-04-18 Sony Corporation Method of forming wirings
US5240880A (en) * 1992-05-05 1993-08-31 Zilog, Inc. Ti/TiN/Ti contact metallization
US8168996B2 (en) 2006-04-17 2012-05-01 Nichia Corporation Semiconductor light emitting device
US8362516B2 (en) 2006-04-17 2013-01-29 Nichia Corporation Semiconductor light emitting device

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