JPH06151356A - Semiconductor device and manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a manufacturing method, of a semiconductor device, wherein a barrier property is sufficient, the coverage of an interconnection layer is good and a low-resistance and shallow junction can be formed surely, to prevent that W or the like is reacted with Si or the like, to obtain a connection whose heat-resistant property is good or to reduce a junction leak by using an Al-based material and to obtain a good connection. CONSTITUTION:In the manufacturing method of a semiconductor device, a metal film 4 is formed on an Si compound film 3, a metal silicide film 5 is formed, a barrier metal layer 7 is obtained, or a heat-resistant silicide is formed on a semiconductor substrate, impurities are ion-implanted into it, and a junction region is formed by a solid-phase diffusion operation. In addition, in the semiconductor device and the manufacturing method, a high-melting-point metal-based material interconnection is formed via a metal silicide film obtained by forming a metal film on a silicon compound film formed on the semiconductor substrate, or the metal silicide film obtained by forming the metal film on the silicon compound film on the semiconductor substrate is formed only inside a junction hole, and an Al-based material interconnection or the like is formed via it.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device. In particular, the present invention relates to a semiconductor device using a silicide technique and a manufacturing method thereof, and also relates to a manufacturing method of a semiconductor device having a structure in which a barrier metal layer is interposed between a semiconductor substrate such as a silicon substrate and a wiring layer formed thereon. It is a thing.

[0002]

2. Description of the Related Art Conventionally, in order to improve the reliability of various elements of a semiconductor device, a wiring layer and a base semiconductor substrate (Si substrate, etc.)
A barrier layer is formed between the wiring layer and the semiconductor substrate in order to prevent the reaction with the wiring layer, improve the adhesion of the wiring film, prevent disconnection defects, and prevent stress migration. The barrier layer is usually a metal (sometimes an alloy),
Alternatively, it is made of a metal compound and is called a barrier metal layer. In this specification, the term "barrier metal layer" is used to generically refer to those that exhibit some kind of barrier action as described above. As a material for forming such a barrier metal layer, TiN, TiW, or the like, or Ti or TiO
N, tungsten nitride and other metals or metal compounds have been used (for conventional techniques of this kind, I
EDM90 (1990 IEEE) EO Travis, et al., Pages 47-50, "A
SCALABLE SUBMICRON CONTACT TECHNOLOGY USING CONFOR
See the description of "MAL LPCVD TiN").

[0003]

Various elements have been miniaturized due to the recent demand for integration of semiconductor devices.
Along with this, for example, contact holes are also miniaturized in ULSI. Therefore, when the barrier metal applied to these structures is formed by depositing in the contact hole 8 as shown in FIG. 3 by the conventional sputtering method as shown in the above-mentioned publicly known document, sufficient coverage can be obtained. I can't. That is, as the contact hole 8 is miniaturized, the coverage is reduced. As a result, as shown in FIG. 3, the non-uniform barrier metal 70 is formed in the contact hole 8 formed in the interlayer film 6.
Film is formed, the opening is closed at the opening portion of the contact hole 8, and the hole diameter R for filling the wiring material such as Al is reduced, and the contact hole 8 is formed.
The barrier metal layer 70 'at the bottom of the is thinned. Therefore, the wiring material (for example, Al) formed in the upper layer can easily form "su" (hollow called void) as shown by the broken line in FIG.
Therefore, the reliability of the connection is lowered, and the base S of the wiring material is
There is a problem of punching through into i. As a result, junction leakage may increase, which may reduce the reliability of the semiconductor device such as a transistor.

As a measure against the above problem, there is a method of forming a taper in the contact hole to increase the coverage. For example, as shown in FIG. 4 (A), a material having a relatively low melting point such as AsSG is used as a material for the interlayer film 6, a contact hole 8 is formed therein, and annealing at about 900 ° C. is performed to reflow the hole 8. There is a method of forming the taper T1. However, when this method is used, there is a problem that the shape of the contact hole 8 becomes an inverse taper shape as shown in FIG. 4B (the inverse taper is indicated by T2).
For this reason, sufficient coverage cannot be obtained, and this method is not a drastic solution after all.

On the other hand, as described above, as the process rule of the device has been reduced, in order to prevent the adverse effect such as the short channel effect due to the reduction, the impurity of the shallow junction in the semiconductor device is low. It is important to form a diffusion region.

First, as a technique for reducing the resistance, salicide (SALICIDE; Self Aligned Silicide) is used to selectively form silicide on the surface of the source / drain regions.
There is a technology, and as an example of the salicide forming technology,
A technique is also known in which, after performing Ar ⁺ sputter etching on the substrate surface, a metal film is bonded and a silicide layer is formed in a self-aligned manner by a two-step RTA (short-time heat treatment) method (for example, “J. Elecrochem. Soc. '' Vol 137, No.
6, June 1990, pp. 1914 to 1917, The Elecrochemica
l Society inc. Issued).

Further, a general method for forming a junction is a method by ion implantation, and in a normal process,
Although impurities are ion-implanted into the silicon substrate for forming the source / drain regions, crystal defects are likely to occur due to damage during the ion implantation. When the junction is deep, the increase in junction leak due to crystal defects does not occur, but when the junction is shallow, the increase in junction leak due to crystal defects occurs.

Therefore, without directly implanting ions into the substrate, a polysilicon layer or a silicide layer is formed in advance on the source / drain regions, impurities are ion-implanted into the polysilicon layer or the silicide layer, and then diffused. There is a method of forming an impurity region by annealing, for example, “Monthly Sem
“Iconductor World”, May 1984, pp. 49-53 (published by Press Journal, Inc.). By such solid-phase diffusion from the polysilicon layer or the silicide layer to the silicon substrate, it is possible to suppress the generation of silicon crystal defects and suppress an increase in junction leak.

By the way, when a silicide is used to reduce the resistance, it must have heat resistance of 900 ° C. or higher. This is because high temperature annealing at 900 ° C. or higher is generally required to diffuse the impurities from the silicide. Even when silicide is not used, when performing activation annealing after contact ion implantation after forming a transistor, it is necessary to perform high temperature annealing at 900 ° C. or higher in the process.

However, a silicide such as TiSi ₂ alloyed by a general heat treatment aggregates in a high temperature process of about 900 ° C., and its sheet resistance increases. For example,
In the experiment on the sheet resistance, 10Ω / □ is 300
In some cases, the sheet resistance increased to Ω / □.

Furthermore, as described above, the following problems must be solved with the miniaturization and integration.

That is, a narrow and deep (that is, high aspect ratio) contact hole and through hole (in this specification,
These buried holes are collectively referred to as connection holes), but connection by a wiring material is important. For example, in the conventional film formation of an Al-based material such as an Al alloy by a sputtering method,
Due to the shadowing effect in which the Al sputtered particles are shadowed on the side wall of the hole and do not enter much inside, the Al coverage is deteriorated in the hole, and disconnection failure is likely to occur at a weak point near the lower part of the hole. Therefore, a process technology for filling the inside of the connection hole with a wiring material has become indispensable. Among these means, as a technique closer to practical application on a mass production level, the substrate is heated at a high temperature of several hundred degrees to
A high-temperature sputtering method has been studied in which an Al alloy or the like is formed by sputtering while an l-based material is in a molten state or a state similar to the molten state.

By the way, when filling a contact hole with such a high-temperature sputtered Al alloy, good filling characteristics can be obtained by depositing a substance such as Ti that easily reacts with Al on the sidewall of the hole. It is difficult to embed it with good coverage. In the case of Ti, the melting point is 16
Since it is as high as 80 ° C., improvement in coverage due to high temperature sputtering cannot be expected.

As described above, the high temperature Al sputtering technique has a limit in embedding the fine connection hole by itself. As another technique, a technique of embedding a refractory metal such as W by CVD is drawing attention. According to this method, CV
Since W or the like is grown in the connection hole by D, it is possible to bury it stably regardless of the size of the connection hole.

However, if W is grown directly on the Si substrate, there is a problem that the junction leak of the transistor increases due to the reaction between W and the underlying substrate, particularly Si, in the subsequent heat treatment. As a countermeasure, Ti
There is a method of forming N on the underlayer of W, but there is a problem that TiN by sputtering does not enter the fine connection hole, and TiN formation by CVD is not technically established at the mass production level and is stable. There is a problem that it cannot be formed.

As another method, it is possible to form TiSi ₂ as salicide on the source / drain regions in advance to prevent the reaction between the underlying Si and W by using TiSi ₂ as a barrier. This means W / T
In iSi ₂ / Si contact structure 600 to 700
It has a heat resistance of about ℃ and is effective. But 800
℃ for W in the above the Si can diffuse through the TiSi _2, WSi ₂ turned into, is broken heat resistance. Therefore, there is a problem that it can generally be used only in a process limited to 700 ° C. or less.

FIG. 12 is a diagram of the W / TiSi ₂ / Si structure measured by RBS after heat treatment at 800 ° C. From this measurement graph I, it can be seen that W diffuses Si and becomes W silicide. This is because, in addition to the peak Ib of W, the portion Ia showing WSi ₂ is seen.

[0018]

An object of the present invention is to solve the above-mentioned problems of the prior art and to provide a semiconductor device having a barrier metal layer, which has a sufficient barrier property and can achieve the formation of a wiring layer of a wiring material with good coverage. Accordingly, it is an object of the present invention to provide a semiconductor device manufacturing method capable of obtaining a highly reliable and highly reproducible semiconductor device in a simple process.

It is another object of the present invention to provide a method of manufacturing a semiconductor device which can surely form a shallow junction while maintaining low resistance.

It is another object of the present invention to provide a semiconductor device and a method for manufacturing the same which can prevent a reaction between a refractory metal such as W and a semiconductor substrate, such as Si, and allow a connection with good heat resistance.

Still another object of the present invention is to provide a semiconductor device using an Al-based material, which can reduce junction leakage and obtain good connection, and a method of manufacturing the same. Other objects of the invention of the present application will be apparent from the following description.

[0022]

According to a first aspect of the present invention, a diffusion region is formed in a semiconductor substrate, a silicon compound film is formed on the diffusion region, and a metal film is formed on the silicon compound film. , A metal silicide film is formed, an interlayer film is further formed, a barrier metal material film is formed on the interlayer film, and then the barrier metal material film is patterned to obtain a barrier metal layer. A method of manufacturing a semiconductor device, which comprises a step of patterning an interlayer film to form a contact hole and burying a wiring material in the contact hole to form a wiring, which achieves the above object by this configuration.

The invention of claim 2 of the present application is the method of manufacturing a semiconductor device according to claim 1 in which the semiconductor device is a MOS transistor, and achieves the above object by this configuration.

The invention of claim 3 of the present application is the method of manufacturing a semiconductor device according to claim 1 in which the semiconductor device is a bipolar transistor, and achieves the above object by this configuration.

According to a fourth aspect of the present invention, a semiconductor device is manufactured in which a heat-resistant silicide is formed on a semiconductor substrate, impurities are ion-implanted into the heat-resistant silicide, and then a junction region is formed by solid phase diffusion. A method that achieves the above object by this configuration.

According to the invention of claim 5 of the present application, the heat-resistant silicide is a layer formed by subjecting a metal film formed on a semiconductor substrate via a thin semiconductor compound film to a low temperature heat treatment followed by a high temperature heat treatment. According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, wherein the above object is achieved by this configuration.

According to a sixth aspect of the present invention, a metal silicide film obtained by forming a metal film on a silicon compound film formed on the semiconductor substrate is formed on the semiconductor substrate, and the metal silicide film is formed. A semiconductor device in which a refractory metal-based material wiring is formed via the above-mentioned structure, and the above object is achieved by this configuration.

The invention of claim 7 of the present application is the semiconductor device according to claim 6 which is a MOS transistor, and achieves the above object by this configuration.

The invention of claim 8 of the present application is the semiconductor device according to claim 6 which is a bipolar transistor, and achieves the above object by this configuration.

According to a ninth aspect of the present invention, a silicon compound film is formed on a semiconductor substrate, a metal film is formed on the silicon compound film, a metal silicide film is formed, and the metal silicide film is formed on the metal silicide film. A method for manufacturing a semiconductor device, which comprises a step of forming a refractory metal-based material wiring, and achieves the above object by this configuration.

The invention of claim 10 of the present application is the method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor device is a MOS transistor, and achieves the above object by this configuration.

The invention of claim 11 of the present application is the method of manufacturing a semiconductor device according to claim 1 in which the semiconductor device is a bipolar transistor, and achieves the above object by this configuration.

According to a twelfth aspect of the present invention, a contact hole is formed on a semiconductor substrate, and a metal silicide film obtained by forming a metal film on a silicon compound film formed on the semiconductor substrate is formed. The metal silicide film is a semiconductor device formed only inside the connection hole, and achieves the above object by this configuration.

According to a thirteenth aspect of the present invention, a contact hole is formed on a semiconductor substrate, and a metal silicide film obtained by forming a metal film on a silicon compound film formed on the semiconductor substrate is formed. , The metal silicide film is formed only in the connection hole, and Al is formed through the metal silicide film.
A semiconductor device having a system material wiring formed therein, which achieves the above object.

According to a fourteenth aspect of the present invention, a contact hole is formed on a semiconductor substrate, a silicon compound film is formed in the contact hole, and a metal film is formed on the silicon compound film to form a metal film. A method of manufacturing a semiconductor device in which a silicide film is formed only in the connection hole, and a high temperature Al-based material is formed by sputtering, and the above object is achieved by this structure.

In the invention of claim 15 of the present application, the high temperature condition is 3
15. The method for manufacturing a semiconductor device according to claim 14, wherein the temperature is not lower than 00 ° C., and the object is achieved by this configuration.

According to a sixteenth aspect of the present invention, a contact hole is formed on a semiconductor substrate, a silicon compound film is formed in the contact hole, and a metal film is formed on the silicon compound film to form a metal film. A silicide film is formed only inside the connection hole, and further, C
A method for manufacturing a semiconductor device, in which a metal-based material is formed by the VD method, and the above object is achieved by this configuration.

In the present invention, any silicon compound may be used as long as a metal film can be formed thereon to form a metal silicide film. For example, a silicon oxide film such as SiO ₂ or Si ₃ N _{4 can be used.} The silicon nitride film or the like can be used. The thickness of the silicon compound film is 3 to 30.
When the thickness is nm, silicidation by heat treatment or the like is easy, which is preferable. Any metal film can be used as long as it can be silicided to form a barrier metal, such as Ti, W, and C.
O, Ni, alloys (or intermetallic compounds) of these, or oxides, nitrides, oxynitrides or the like thereof can be used.

The technique for forming a metal film on a silicon compound film to obtain a metal silicide film was proposed by the present applicant, and the obtained metal silicide film structure is
It is called a SITO X structure. Regarding this, Japanese Patent Application Laid-Open No. 2-260630 of the present applicant and IEDM
90 (1990 IEEE) Hirofumi Sumi et al., Pp. 249-252,
`` New Silicidation Technology by SITOX (Silicidatio
n Through Oxide) and Its Impact on Sub-half Micron
See MOS Devices ”for more information.

According to the invention of the present application, such SITOX
Further improvements in structure can be achieved.

For example, in the invention of claim 5 of the present application, in manufacturing a semiconductor device, a heat-resistant silicide is formed on a semiconductor substrate, impurities are ion-implanted into the heat-resistant silicide, and then solid phase diffusion is performed. The junction region is to be formed, and the heat resistant silicide is 900
It is a silicide that does not aggregate even at a high temperature of about ℃,
As an example thereof, a layer formed by subjecting a metal film formed on a semiconductor substrate via a thin semiconductor compound film to a low temperature heat treatment followed by a high temperature heat treatment can be used. The action is brought about.

That is, when the solid phase diffusion is performed using silicide only to form a shallow junction, sufficient heat resistance cannot be obtained, and the resistance cannot be reduced. However, in the technique of forming a silicide structure as described above, since heat-resistant silicide is used, the sheet resistance does not increase even during solid phase diffusion, and a semiconductor device having a low resistance and a shallow junction can be manufactured.

A silicide formed by two-step annealing at a low temperature and a high temperature with a semiconductor compound of a thin film interposed as an example of the heat-resistant silicide is disclosed in Japanese Patent Laid-Open No. 3-38823 previously proposed by the present applicant. Although disclosed, it is found that the silicide has particularly high heat resistance, and by applying the present invention, a semiconductor device having a low resistance and a shallow junction can be reliably formed.

Next, the configuration of the invention of claim 1 of the present application will be outlined below with reference to the example of FIG. 1 showing an embodiment of the invention which will be described later in detail.

In the method of manufacturing a semiconductor device according to the present invention, the diffusion regions 21 and 22 are formed in the semiconductor substrate 1 such as a silicon substrate and the diffusion regions 21 and 22 are formed as illustrated in FIG.
A silicon compound film 3 such as SiO ₂ is formed on the silicon film 22, and a metal film 4 is formed on the silicon compound film 3 with a refractory metal material such as Ti to form a structure as illustrated in FIG. Then, a metal silicide film 5 (for example, a titanium silicide film) is formed by performing a process such as heat treatment (see the example of FIG. 1C), and an interlayer film 6 is further formed.
A barrier metal material film 71 made of TiN, TiW or the like is formed on the interlayer film 6 to have a structure as illustrated in FIG.
Next, the barrier metal material film 71 is patterned to obtain the barrier metal layer 7 (see the example of FIG. 1E), and then the interlayer film 6 is patterned to form the contact hole 8.
A wiring material 9 such as Al is embedded in the contact hole 8 to form a wiring to obtain a structure illustrated in FIG. 1 (f).

According to the present invention, since the barrier metal layer is formed in advance by the above-described SITO X structure without forming the barrier metal layer after opening the contact hole, the barrier metal is not formed at the bottom of the opening. There is no problem that it is not formed sufficiently, and there is no problem that the opening is narrow and the wiring material is not sufficiently filled, and it is possible to improve the barrier property and the coverage of the wiring film. The reliable process can be used as it is, the reliability is not lowered, and the process can be simplified. Therefore, it is possible to obtain a semiconductor device having excellent reliability and reproducibility.

[0047]

EXAMPLES Examples of the present invention will be described below. However, as a matter of course, the present invention is not limited to the examples described below.

Example 1 In this example, the present invention was applied to the manufacture of a MOS transistor having a structure as shown in FIG. 1 (a)-
Reference is made to (f).

In this embodiment, a silicon substrate is used as the semiconductor substrate 1, and LOCOS, which is the field oxide region 11, is formed on the silicon substrate, and then the gate region 12 and the diffusion region 21,
22 (source 21 and drain 22) are formed to make a MOS transistor. 13 is a gate insulating film (here, a SiO ₂ film)
Is. As a result, the structure shown in FIG. 1A is obtained.

Next, a thermal oxide film of about 5 nm is formed on the entire surface, and this oxide film (SiO ₂ film) is used as the silicon compound film 3
Further, 300 Å of Ti is deposited on the entire surface as the metal film 4. As a result, the structure shown in FIG. 1B is obtained.

Then, the metal silicide film 3 (here, SITOX-TiSi ₂ ) is formed only on the diffusion regions 21 and 22 by the two-step annealing method. Here, the two-step annealing method is a heat treatment by the following first and second annealing (low temperature heat treatment and high temperature heat treatment).
You get the structure. First anneal: 650 ° C., 30 seconds, etching with ammonia-hydrogen peroxide solution Second anneal: 900 ° C., 30 seconds As a result, diffusion regions 21 and 22 which are source / drain regions
A structure shown in FIG. 1C is obtained in which the upper surface is covered with the metal silicide film 3 (SITOX-TiSi ₂ ). SITOX-
TiSi ₂ is a film having a barrier property against Al, as reported in the above-mentioned reference by H. Sumi et al.

After that, the interlayer film 6 is formed as a CVD oxide film 61 (S by using TEOS (tetraethoxyoxysilane), for example.
iO ₂ film) and the like, and a film 62 of BPSG (boron phosphorus-containing impurity glass) or the like. The interlayer film may be formed by any means such as using other silicon-containing organic gas such as DADBS, TMCTS and DES, or using glass containing impurities such as AsSG, BSG and PSG. Subsequently, TiN (titanium nitride), which is a barrier metal material here, is formed by sputtering. As a result, the structure of FIG. 1D having the barrier metal material film 71 is obtained. Here, as in this example, T
When iN is used, it has favorable barrier properties and is preferable, and also has good stress migration prevention performance. For example, TiN relieves the stress of Al even if stress is caused by a passivation film or the like formed in the upper layer.
If TiW or the like having good conductivity is used instead of TiN, connection failure can be prevented even if Al or the like of the wiring is broken.

Next, a photoresist pattern 81 for forming the contact hole 8 is formed by patterning using a normal photolithography technique. Then, isotropic etching is performed with hydrogen peroxide water to etch the TiN that is the barrier metal material film 71, thereby forming a structure including the barrier metal layer 7 as shown in FIG. The isotropic etching may use an isotropic dry etching means which is plasma etching with CF ₄ or the like. The etching conditions with CF _{4 at} this time are, for example, CF ₄ / Ar / O ₂ = 45/50 / 5sc.
The conditions of cm, 106.4 Pa and 300 W can be adopted.

Subsequently, the interlayer film 6, which is a base oxide film, is anisotropically etched with a gas such as CHF ₃ to form a contact hole 8. The condition is, for example, C ₄ F ₈ = 50 s
ccm, RF power: 1200 W, 2 Pa.

Next, the contact hole 8 is filled by high temperature Al sputtering. As a result,
The structure of (f) is obtained. As the Al forming conditions at this time, the following two-step high temperature Al filling conditions can be adopted. First step: 22.5 kW, Ar100 sccm,
0.47 Pa, 1.2 μm / min Second step: 10.5 kW, 500 ° C., Ar100s
ccm, 0.47Pa, 0.6μm / min

According to this embodiment, a semiconductor device (MOS transistor) which solves the problems of the prior art can be obtained with good reproducibility by the conventionally used process of good reliability.

Example 2 In this example, the same technique as in Example 1 described above was applied to the manufacture of a bipolar transistor. Please refer to FIG.

In this embodiment, the semiconductor substrate 1 made of silicon or the like is used.
A metal silicide film 5 having a SITO X structure is formed on the P diffusion region 24 on the n-well 23 by the same method as the above example.
A contact hole 8 was formed on this, and a wiring material 9 was embedded therein. As described above, the present invention can be effectively used for manufacturing the bipolar transistor structure.

Example 3 In this example, a thin silicon oxide film having a thickness of about 5 nm or less is formed on a diffusion region, a Ti film for silicidation is formed on the silicon oxide film, two-step annealing, ion A method of manufacturing a semiconductor device having a MOS transistor through implantation and solid phase diffusion. Hereinafter, this embodiment will be described in accordance with the steps thereof with reference to FIGS. 5A to 5F and FIG.

First, a thick field oxide film 32 is formed on the surface of the silicon substrate 31 by the selective oxidation method. Next, a thin gate oxide film 33 is formed on the surface of the substrate in a region surrounded by the field oxide film 32, and a polysilicon layer 34 is further formed on the gate oxide film 33. Then, the polysilicon layer 34 is patterned into a desired gate electrode pattern by a lithographic technique.

Next, a patterned polysilicon layer
Using the 34 and the field oxide film 32 as a mask, low concentration ion implantation is performed by self-alignment,
35, 35 are formed on the substrate surface. The low-concentration impurity diffusion regions 35, 35 alleviate the electric field concentration near the drain of the MOS transistor.
Formed into a structure.

Next, a CVD silicon oxide film is formed on the entire surface, and the CVD silicon oxide film is etched back to form a CVD film on the side portion of the polysilicon layer 34 which will be a gate electrode, as shown in FIG. 5A. Sidewalls 36, 36 made of the remaining portion of the silicon oxide film are formed.

After forming the sidewalls 36, 36, silicon oxide films 37, 37 having a film thickness of 5 nm are formed on the exposed surface of the silicon substrate 31, as shown in FIG. 5B.
The conditions for forming the silicon oxide films 37, 37 are, for example, 850
It suffices to put the furnace in a dry O ₂ atmosphere for 15 minutes. Since the silicon oxide films 37, 37 are extremely thin films, in the case of silicidation, the silicon of the substrate is a silicon oxide film.
Supplied via 37,37. For example, silicon oxide film 3
When the film thickness of 7 and 37 is 7 nm or more, since the film thickness is large, silicon is no longer supplied from the substrate, and the sheet resistance increases conversely.

After forming the silicon oxide films 37, 37, a Ti film 38 is formed on the entire surface including the silicon oxide films 37, 37. As a result, the structure shown in FIG. This Ti film 38
Is, for example, 30 nm, and the deposition conditions are, for example, RF bias of 50 W, DC 1 kW of sputtering power, Ar of 40 sccm, and pressure of 0.4.
Pa, deposition temperature 200 ° C., deposition rate 60 nm / mi
Each condition of n.

After forming such a Ti film, a first annealing process is performed. The annealing treatment is performed by, for example, RTA (Rapid Thermal Annealing) in an Ar atmosphere, and the low temperature first annealing treatment is performed at 650 ° C. for 30 seconds. By this first low temperature annealing treatment, titanium is silicidized, and a titanium silicide film made of TiSi and Ti ₃ Si ₃ is formed in the region to which silicon is supplied. In addition, Ti on the titanium silicide film
The film 38 is oxidized into a TiOx (titanium oxide) film.

After the first annealing process and before the second annealing process, the Ti film and the TiOx film on the titanium silicide film are removed using ammonia hydrogen peroxide or the like. As an example of ammonia hydrogen peroxide, NH ₄ OH: H ₂ O ₂ : H ₂ O =
The one used is 1: 2: 2. This etching is performed by immersing it for about 10 minutes, for example. By the etching using this ammonia-hydrogen peroxide mixture, the unreacted Ti film and the oxidized TiOx film are removed. During this removal, for example, the Ti film 38 on the surface of the sidewall 36 and the field oxide film 32 is removed.
Is removed to form a salicide structure in which silicide is formed by self-alignment only on the surface of the source / drain region and the upper surface of the polysilicon layer 34 which will be the gate electrode.

Next, a high temperature second annealing process is performed.
The condition of this annealing treatment is, for example, 900 nm in a nitrogen atmosphere.
The conditions of the RTA method are 30 ° C. and 30 seconds. By this second annealing treatment, the titanium silicide film made of TiSi and Ti ₃ Si ₃ is changed to the titanium silicide film 39 made of a TiSi ₂ film which is stable with low resistance. This TiSi
_As shown in FIG. 5D, the titanium silicide film 39 composed of the _two films is formed on the upper surface of the gate electrode and the surface of the silicon substrate 31 which will be the source / drain regions to reduce the resistance of these parts. Further, since the titanium silicide film 39 formed by performing the two-step annealing after forming the thin oxide film as described above is heat resistant so that aggregation does not occur even at high temperature,
Then, low resistance can be maintained even after a high temperature process.

After the two-stage annealing process at low temperature and high temperature, impurities are implanted into the titanium silicide film 39 by ion implantation, as schematically shown by reference numeral I ² in FIG. 5 (e). At this time, the sidewall 36 and the field oxide film
32 also works as part of the mask. The impurities implanted here are for forming the high-concentration impurity diffusion regions of the source / drain regions. Since impurities are not directly implanted into the substrate by ion implantation, damage to the substrate can be suppressed, and junction leakage due to crystal defects can be mitigated. Ion implantation is performed under the conditions of 50 keV and 3 × 10 ¹⁵ / cm ^{2 using} As (arsenic) as a dopant, for example.

FIG. 6 shows SIMS (Secondly Ion).
Micro analysis) shows the profile of impurities when As is ion-implanted, the horizontal axis is the substrate depth in nm, the vertical axis is the concentration distribution in arbitrary units for Ti, and the number / cm ³ unit for As. The impurity concentration is shown by. As shown in FIG. 6, the ion-implanted A
The peak of the s (arsenic) dopant is within the depth of 50 nm where Ti is rich due to silicide. It is generally known that the damage area due to ion implantation is located in about 75% of the project range from the surface (for example, VLSI Process Data Handbook, P.
248, published by Science Forum Co., Ltd.), some of the As dopant diffuses to a certain depth in the silicon substrate 31, but the region where damage occurs is limited to the inside of the titanium silicide film 39, It can be seen that the damage of is not deep.

When ions are directly implanted into the silicon substrate instead of the silicide film as in the conventional case, silicon is transferred to the side portion of the side wall due to the synergistic effect of substrate damage and high temperature annealing in the subsequent process. Although a kind of crystal defect) has occurred, by implanting ions into the titanium silicide film 39 as in this embodiment,
No damage to the silicon substrate occurs, and finally no crystal defects occur even after a high temperature process.

Subsequent to the ion implantation, as shown in FIG. 5F, an interlayer insulating film 30 made of a CVD silicon oxide film is deposited on the entire surface. The deposition conditions for this interlayer insulating film 30 are
For example, SiH ₄ : O ₂ : N ₂ = 250: 250: 10
The conditions are 0 sccm, 420 ° C., 13.3 Pa, and 0.5 μm. After forming the interlayer insulating film 30, for example, N
Annealing is performed for a short time at a temperature of 1100 ° C. for 10 seconds in _two atmospheres. This short-time annealing activates the region in which impurities have been implanted and activates the silicide, so that the source / drain region 30 of a sufficiently shallow junction is formed.
s, 30d will be formed. Although a temperature of 110 ° C. is applied during this annealing, the titanium silicide film 39
As described above, since the heat resistance is such that agglomeration does not occur even at a high temperature, a low resistance sheet resistance can be maintained.

The semiconductor device having a MOS transistor is completed through the required electrode formation and the like.

In the MOS transistor formed by this embodiment, as shown in FIG. 8, the junction leakage of the MOS transistor of this embodiment shown by the curve A is about one digit as compared with the conventional one (curve B in the drawing). Will also decrease. At the same time, a low resistance sheet resistance is obtained, and as an example of the sheet resistance obtained in the present embodiment, a low resistance value of about 8Ω / □ is obtained.

Embodiment 4 This embodiment is an example in which a process of forming a silicide on a thin silicon compound film and obtaining a shallow junction with low resistance by two-step annealing is applied to a process of a bipolar transistor. This embodiment will be described with reference to FIGS.

First, a p-type well region is formed on an n-type silicon substrate, and an n-type epitaxial layer 42 is formed on the n ⁺ -type buried layer 41 in the p-type well region. After forming the n-type epitaxial layer 42, a field oxide film (LOCOS film) 43 is formed by selective oxidation.
As shown in FIG. 7A, the surface of the field oxide film 43 is shaved and flattened, and a collector extraction region is formed in a region communicating with the epitaxial layer 42 below the field oxide film 43 through the buried layer 41. Forming 44.

Next, a 5 nm silicon oxide film is formed on the substrate surface.
Forming 45. The formation of this thin silicon oxide film 45 is
For example, it is formed by thermal oxidation for a short time. After the silicon oxide film 45 is formed, as shown in FIG.
A film 46 is formed. The Ti film 46 can be formed by the same sputtering as in Example 3, and has a film thickness of about 30 nm.

After the Ti film 46 is laminated on the thin silicon oxide film 45, the titanium silicide film 47 is formed by the two-step annealing as shown in FIG. 7C. Explaining this alloying treatment, first, at 650 ° C. in an Ar atmosphere,
A low temperature annealing process by the RTA method is performed for 30 seconds. By this annealing, silicon and Ti pass through a thin oxide film.
Are alloyed to form a silicide composed of TiSi and Ti ₃ Si ₃ . After this first annealing treatment, the unreacted Ti and T are immersed in ammonia-hydrogen peroxide mixture for about 10 minutes.
Remove iOx. That is, the Ti film 46 and the like on the field oxide film 43 are removed. Subsequently, a high temperature annealing treatment at 900 ° C. is performed in a nitrogen atmosphere for 30 seconds. In this high temperature annealing treatment, a titanium silicide film made of TiSi ₂ is formed, and the exposed surface of the silicon substrate is covered with the heat resistant titanium silicide film 47.

Next, a resist film is applied on the entire surface, and after selective exposure and development, a resist mask is formed on the substrate.
Forming 48. The resist mask 48 has a pattern having an opening 48a in the base / emitter region. Next, using the resist mask 48 as a mask, FIG.
As shown in (d), impurity ion implantation for forming a base region is performed. In particular, in this ion implantation, the ion implantation is not performed with energy that directly damages the silicon substrate, and impurities are implanted into the titanium silicide film 47 on the substrate surface. Here, as an example of the implantation conditions of the ion implantation, the dopant is BF
Ions may be implanted under the conditions of _2, 20 keV and 1 × 10 ¹⁵ ions / cm ² .

After ion implantation is performed on the titanium silicide film 47, an interlayer insulating film 49 is formed on the entire surface as shown in FIG. 7 (e). The interlayer insulating film 49 is made of a CVD silicon oxide film, and the forming condition is SiH ₄ : O ₂ : N ₂ =
250: 250: 100 sccm, 420 ° C, 13.3
It is set to Pa. An interlayer insulating film 49 having a film thickness of about 5000 Å is formed by this CVD.

After forming the interlayer insulating film 49, annealing is performed at 1100 ° C. for 10 seconds in a nitrogen atmosphere for a short time. By this annealing, the silicon substrate and the titanium silicide film
47 is activated and the titanium silicide film 47 is activated.
A base region 40 formed of a p-type impurity diffusion region is formed immediately below the titanium silicide film 47 by the impurity diffusion from. At the time of this annealing, a high temperature treatment of 1100 ° C. is performed, but in this embodiment, since the heat-resistant silicide film is formed by the two-step annealing through the thin oxide film 45, the conventional silicide aggregation phenomenon occurs. Without doing so, the titanium silicide film 47 maintains a low resistance.

Next, the interlayer insulating film 49 in the region where the emitter region is to be formed is removed. In the selective removal step, first, a resist layer is applied to the entire surface, a resist mask having an opening corresponding to the emitter region is formed by selective exposure and development, and then the resist mask is used to dry-etch the interlayer. This is performed by removing the insulating film 49 according to the mask pattern. As a result, the structure shown in FIG. The formed opening is indicated by 51. The conditions of dry etching are, for example, C ₄ F ₈ gas, 50 scc
m, RF power 1200 W, 2 Pa.

After opening the interlayer insulating film 49, the opening 51 is formed.
The titanium silicide film 47 exposed to the bottom of the substrate is removed by hydrofluoric acid to expose the substrate surface as shown in FIG. The aqueous solution of hydrofluoric acid is, for example, H ₂ O: HF = 10.
It is set to 0: 5, and the surface of the substrate appears by immersing it for about 3 minutes.

When the surface of the substrate to be the emitter region is exposed, as shown in FIG. 7H, a CVD silicon oxide film 52 is formed on the entire surface to a thickness of about 0.3 μm. This CVD silicon oxide film 52 is, for example, Si
_{H 4: O 2: N 2} = 250: 250: 100sccm,
It is formed under the conditions of 420 ° C. and 13.3 Pa.

As shown in FIG. 7 (i), the formed C
The VD silicon oxide film 52 is entirely etched back to open
The CVD silicon oxide films 52a and 52a are left on the side walls of 51. The condition of the etch back is, for example, C ₄ F ₈ gas of 50.
sccm, RF power 1200 W, 2 Pa. By this etch back, the CVD silicon oxide film 52 becomes a so-called sidewall, contributes to the formation of a minute emitter region, and realizes self-aligned separation between the base and the emitter.

When the substrate surface is exposed between the CVD silicon oxide films 52a which function as sidewalls, as shown in FIG.
As shown in (j), a doped polysilicon layer (DOPOS layer) 53 containing a high concentration of n-type impurities is formed on the entire surface. The conditions for forming this doped polysilicon layer 53 are
For example, SiH ₄ : H ₂ : N ₂ = 100: 400: 200
The conditions are sccm and 70 Pa, and the film thickness is about 1500Å.

After forming the doped polysilicon layer 53, the doped polysilicon layer 53 is left only inside the opening 51 by resist patterning and etching, and the doped polysilicon layer 53 on another interlayer insulating film 49. To remove.
The conditions for this removal are, for example, a microwave etcher, SF ₆ : Freon 113 = 6: 44 sccm, 1.
33Pa, magnetron filament current 220m
The conditions for A and RF power are 100 W.

Next, as shown in FIG. 7K, contact holes 54 and 55 are formed from the surface of the interlayer insulating film 49. The contact hole 54 is a contact hole for taking out the base electrode, and the contact hole 55 is a contact hole for taking out the collector electrode. The contact holes 54 and 55 are formed by forming a resist pattern serving as a mask and then processing the interlayer insulating film 49 by dry etching using the resist pattern. An example of the conditions of this dry etching is that the C ₄ F ₈ gas is 50 sccm and the RF power is 1200 W and 2 Pa. Due to the formation of the contact holes 54 and 55, the low resistance titanium silicide film 47 faces the bottoms of the contact holes 54 and 55.

Next, as shown in FIG. 7L, an aluminum-based wiring layer 56 is formed on the entire surface. The aluminum-based wiring layer 56 is a layer containing silicon, copper, or the like in aluminum, and can be formed under the conditions of Ar gas 40 sccm, 0.4 Pa, sputtering power DC 6 kW, and 8000 Å / min. The film thickness.

After the entire surface of the aluminum-based wiring layer 56 is formed, the aluminum-based wiring layer 56 is patterned for each electrode as shown in FIG. 7 (m). This patterning is performed by a resist mask and dry etching, and the base electrode 56B and the emitter electrode made of an aluminum-based wiring layer are used.
56E and collector electrode 56C are respectively formed. As conditions for dry etching, an RF applied type ECR etcher was used, and BCl ₃ : Cl ₂ = 60: 90 sccm,
Microwave power 1000W, RF power 50W, 2.
Each condition is 13 Pa. In this way, each electrode 56E, 56
After B and 56C are formed, the bipolar transistor is completed according to a normal process.

In the bipolar transistor manufactured by the above manufacturing process, the titanium silicide film 47 having sufficient heat resistance is formed by the two-step annealing through the thin silicon oxide film 45 instead of the normal silicide. The coagulation phenomenon does not occur even after annealing at a high temperature of about 1100 ° C., and the titanium silicide film 47 can be kept at a low resistance. With this titanium silicide film 47, the response speed of the device can be increased by about 20% as compared with the case where no silicide is formed.

Further, the base region 50 is formed by solid phase diffusion of impurities from the titanium silicide film 47, and since impurities are not directly implanted into the silicon substrate, damage is prevented and crystal defects are generated. It is possible to form a bipolar transistor which is not adversely affected by. Further, as in the conventional manufacturing method, in a method of forming Ti in a region which is already highly doped with p-type boron and performing silicidation by annealing, boron reacts with Ti to react with boron and titanium such as TiB _3. a compound of the formation, but formation of TiSi ₂ is difficult, in the present embodiment is easy is relatively forming the TiSi _2, the sheet resistance value is finally 5 [Omega / □ degree of far superior It becomes a value.

Although the npn-type bipolar transistor has been described in the above embodiments, the semiconductor device manufacturing method according to the present invention is applicable to various processes such as a pnp-type bipolar transistor, a CMOS bipolar transistor, and a lateral-type bipolar transistor. Can also be applied.

Fifth Embodiment Next, a fifth embodiment will be described. This embodiment embodies a MOS transistor, and in this embodiment, the steps of FIGS. 9A to 9F are performed.

(A) A LOCOS 11 and a gate region 12 are formed on the semiconductor substrate 1 to form the structure of FIG. 9A (13 is a gate insulating film).

(B) As the silicon compound film 3, a thermal oxide film of 3 nm is formed on the entire surface. For example, the following conditions can be adopted. Gas H ₂ O / O ₂ = 1.5 / 6 liter / min, temperature: 850 ° C., film thickness: 3 nm Further, as the refractory metal film 4, Ti is formed on the entire surface to 30 nm. As a result, the structure shown in FIG. 9B is obtained. condition is,
For example, the following can be adopted. Ar = 40 sccm, pressure: 0.04 Pa, sputtering power: 1 kW, film thickness: 30 nm

(C) Next, the metal silicide film 5 (SIT) is formed only on the diffusion regions 21 and 22 by a two-step annealing method.
OX-TiSi ₂ ) is formed. Here, the two-step annealing method is to obtain a SITO X structure by heat treatment by first and second annealing (low temperature heat treatment and high temperature heat treatment). First anneal 600 ° C. 30 seconds (in Ar) Selective etching Unreacted Ti selective etching with ammonia hydrogen peroxide H ₂ O: H ₂ O ₂ : NH ₄ OH = 2: 2: 1 Second anneal 900 ° C. 30 seconds (In N ₂ ) As a result, the diffusion regions 21, which are the source / drain regions,
22 was covered with a metal silicide (SITOX-TiSi ₂ ). This structure is shown in FIG.

(D) After that, the interlayer film 61 is formed by, for example, TE.
It is formed of a CVD oxide film using OS, and further a BPSG film 62
And so on. As the conditions for forming the TEOS oxide film, for example, the following can be adopted. Gas TEOS = 50 sccm, pressure: 40 Pa, temperature: 720 ° C., film thickness: 400 nm The following film forming conditions can be adopted for the film such as BPSG. Gas SiH ₄ / PH ₃ / B ₂ H ₆ / O ₂ / N ₂ = 80
/ 7/7/1000 / 32000sccm, temperature: 40
At 0 ° C., pressure: 101325 Pa, film thickness: 500 nm The interlayer film 61 composed of the films 61 and 62 is formed as described above. As a result, the structure shown in FIG. 9D is obtained.

(E) After patterning the resist, the contact hole 8 is formed by dry etching to obtain the structure shown in FIG. 9 (e). The resist pattern is shown by reference numeral 8. For example, the following conditions can be adopted. Gas C ₄ F ₈ = 50 sccm, RF power: 1200
W, pressure: 2 Pa

(F) Deposit CVD-W on the entire surface. For example, under the following conditions. Gas WF ₆ / H ₂ = 95/550 sccmP, temperature:
450 ° C., pressure: 10640 Pa, film thickness: 400 nm Next, W is formed only in the connection hole 8 by etch back.
The etch back conditions are as follows, for example. Gas SF ₆ = 50 sccm, microwave power: 85
0W, RF power: 150W, Pressure: 1.33Pa

Next, a Ti layer 91 is formed, and Al-1% Si is formed as an Al-based wiring material 9 on the Ti layer 91 by sputtering to obtain the structure shown in FIG. The following conditions can be adopted to obtain the Al-Si / Ti structure. Example of AlSi film forming conditions Power: 22.5 kW, film forming temperature: 150 ° C., Ar = 4
0 sccm, film thickness: 500 nm Ti film forming condition example power: 4 kW, film forming temperature: 150 ° C., Ar = 100 s
ccm, film thickness: 70 nm After that, an Al-1% Si / Ti wiring layer is formed by using resist patterning and dry etching. The conditions are as follows, for example. Gas BCI ₃ / CI ₂ = 60/90 sccm, microwave power: 1000 W, RF power: 50 W, pressure:
0.016 Pa

Sixth Embodiment Next, a sixth embodiment will be described. This is the case where TiSALICIDE is formed on the entire surface of the source / drain.
This is an example of the case where ITOX-TiSi ₂ is formed only in the fine connection holes. This will be described with reference to FIG.

(A) Semiconductor substrate 1 in the same manner as in Example 5.
The LOCOS 11 and the gate region 12 are formed on the upper surface of FIG.
The structure of (a) is obtained.

(B) Thereafter, the interlayer film is formed of TEOS, for example.
Is formed by using a CVD oxide film under the following conditions. Gas TEOS = 50 sccm, pressure: 40 Pa, temperature: 720 ° C., film thickness: 400 nm Further, a film such as BPSG is formed under the following conditions to form the interlayer film 6
To form. Gas SiH ₄ / PH ₃ / B ₂ H ₆ / O ₂ / N ₂ = 80
/ 7/7/1000 / 32000sccm, temperature: 40
At 0 ° C., pressure: 101325 Pa, film thickness: 500 nm As described above, the interlayer film 6 including the films 61 and 62 is formed as shown in FIG.

(C) After patterning the resist, the contact hole 8 is formed by dry etching. The conditions can be as follows, for example. Gas C ₄ F ₈ = 50 sccm, RF power: 1200
W, pressure: 2 Pa

Next, a thermal oxide film of 3 nm is formed on the entire surface under the following conditions, for example. Gas H ₂ O / O ₂ = 1.5 / 6 liter / min, temperature: 850 ° C., film thickness: 3 nm Further, Ti is formed on the entire surface to 30 nm. Ar = 40 sccm, pressure: 0.04 Pa, sputtering power: 1 kW, film thickness: 30 nm

(D) Next, a metal silicide film (SITOX-TiSi ₂ ) is formed by a two-step annealing method. Here, the two-step annealing method means the first and second
The SITO X structure 5 is obtained by heat treatment by annealing. By this annealing, the metal silicide film 5 is selectively formed only in the diffusion region, that is, in the bottom of the hole 8 in this example. Unreacted T below the bottom of hole 8
i is removed by the next selective etching. First anneal 600 ° C. 30 seconds (in Ar) Selective etching Unreacted Ti selective etching with ammonia hydrogen peroxide H ₂ O: H ₂ O ₂ : NH ₄ OH = 2: 2: 1 Second anneal 900 ° C. 30 seconds (In N ₂ ), the metal silicide (SITOX-TiSi) is formed on the diffusion region which is the source / drain region at the bottom of the hole 8.
₂ ) covered. As a result, the structure shown in FIG.

(E) Ti is formed by sputtering. Ti film forming condition example Power: 4 kW, film forming temperature: 150 ° C., Ar = 100 s
ccm, film thickness: 70 nm Further, Al-1% Si is continuously formed by high temperature sputtering. Example of AlSi film forming conditions Power: 22.5 kW, film forming temperature: 500 ° C., Ar = 4
0 sccm, film thickness: 500 nm After that, an Ai-1% Si / Ti wiring layer is formed by resist patterning and dry etching. The conditions are as follows, for example. Gas BCl ₃ / Cl ₂ = 60/90 sccm, microwave power: 1000 W, RF power: 50 W, pressure:
0.016 Pa This makes it possible to form a contact plug having a stable barrier in the fine connection hole. RB of this embodiment
The S measurement result is shown in FIG. W / SITOX as in this example
-If the TiSi ₂ / Si structure is adopted, SITO X-T
It can be seen that W remains in a pure state because iSi ₂ acts as a barrier. That is, it can be seen that WSi ₂ was not generated and the silicidation of W due to Si diffusion was prevented. Therefore, heat resistance is maintained.

The structure of the present invention is not limited to the above embodiment, and other film forming apparatus such as the vapor deposition method,
It can also be applied to film formation by a chemical vapor deposition method. Further, the film to be formed is not limited to Ti and the like, but can be applied to other metals or semiconductors other than metals, and insulating films.

[0108]

According to the invention of the present application, a semiconductor device having a barrier metal layer, which has a sufficient barrier property,
In addition, it is possible to provide a method for manufacturing a semiconductor device, which can achieve the formation of a wiring layer of a wiring material with good coverage, and thus can obtain a highly reliable and highly reproducible semiconductor device in a simple process, and also has a low resistance. It is possible to provide a method for manufacturing a semiconductor device capable of reliably forming a shallow junction while maintaining
Further, it is possible to provide a semiconductor device and a method for manufacturing the same capable of making a connection with good heat resistance while preventing a reaction between a refractory metal such as W and a semiconductor substrate such as Si. Further, an Al-based material is used. Further, it is possible to provide a semiconductor device capable of reducing junction leak and obtaining good connection, and a manufacturing method thereof.

[Brief description of drawings]

FIG. 1 is a diagram showing a process of Example 1.

FIG. 2 is a diagram showing a second embodiment.

FIG. 3 is a diagram showing a problem of the conventional technique.

FIG. 4 is a diagram showing a problem of the conventional technique.

FIG. 5 is a diagram showing a process of a third embodiment.

FIG. 6 is a diagram showing an analysis result of an impurity distribution in Example 3.

FIG. 7 is a diagram showing a process of Example 4.

FIG. 8 is a comparison diagram of characteristics between Example 3 and a conventional example.

FIG. 9 is a diagram showing a process of Example 5;

FIG. 10 is a diagram illustrating a process of Example 6.

11 is a result of RBS measurement in Example 6. FIG.

FIG. 12 is a RBS measurement result of a conventional example.

[Explanation of symbols]

 1 Semiconductor Substrate 21, 22, 24 Diffusion Area 3 Silicon Compound Film 4 Metal Film 5 Metal Silicide Film (Sl) 6 Interlayer Film 71 Barrier Metal Material Film 7 Barrier Metal Layer 8 Contact Hole 9 Wiring Material 31 Silicon Substrate 32 Field Oxide Film 37 Silicon oxide film 38 Ti film 39 Titanium silicide film 30 Interlayer insulating film 42 Epitaxial layer 43 Field oxide film 45 Silicon oxide film 46 Ti film 47 Titanium silicide film 49 Interlayer insulating film 41 Opening 56E Emitter electrode 56B Base electrode 56C Collector electrode

─────────────────────────────────────────────────── ───

[Procedure amendment]

[Submission date] November 11, 1993

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be corrected] Brief description of the drawing

[Correction method] Change

[Correction content]

[Brief description of drawings]

FIG. 1 is a diagram showing a process of Example 1.

FIG. 2 is a diagram showing a second embodiment.

FIG. 3 is a diagram showing a problem of the conventional technique.

FIG. 4 is a diagram showing a problem of the conventional technique.

FIG. 5 is a diagram showing a process of a third embodiment.

FIG. 6 is a diagram showing an analysis result of an impurity distribution in Example 3.

FIG. 7 is a diagram showing a process of Example 4 (1).

FIG. 8 is a comparison diagram of characteristics between Example 3 and a conventional example.

FIG. 9 is a diagram showing a process of Example 5;

FIG. 10 is a diagram showing a process of Example 6.

11 is an RBS measurement result of Example 6. FIG.

FIG. 12 is a result of RBS measurement of a conventional example.

FIG. 13 is a diagram showing a process of Example 4 (2).

FIG. 14 is a diagram showing a process of Example 4 (3).

FIG. 15 is a diagram showing the process of Example 4 (4).

FIG. 16 is a diagram showing the process of Example 4 (5).

[Description of Reference Signs] 1 semiconductor substrate 21, 22, 24 diffusion region 3 silicon compound film 4 metal film 5 metal silicide film (Sl) 6 interlayer film 71 barrier metal material film 7 barrier metal layer 8 contact hole 9 wiring material 31 silicon Substrate 32 Field oxide film 37 Silicon oxide film 38 Ti film 39 Titanium silicide film 30 Interlayer insulating film 42 Epitaxial layer 43 Field oxide film 45 Silicon oxide film 46 Ti film 47 Titanium silicide film 49 Interlayer insulating film 41 Opening 56E Emitter electrode 56B Base Electrode 56C Collector electrode

[Procedure Amendment 2]

[Document name to be corrected] Drawing

[Correction target item name] All drawings

[Correction method] Change

[Correction content]

[Figure 1]

[Fig. 2]

[Figure 3]

[Figure 4]

[Figure 5]

[Figure 8]

[Figure 9]

FIG. 11

[Figure 6]

[Figure 7]

[Fig. 12]

[Figure 10]

[Fig. 13]

FIG. 14

FIG. 15

FIG. 16

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification number Office reference number FI technical display location H01L 21/331 29/73 21/336 29/784 7514-4M H01L 21/88 N 7377-4M 29 / 72 7377-4M 29/78 301 Y

Claims (16)

[Claims] 1. A diffusion region is formed on a semiconductor substrate, a silicon compound film is formed on the diffusion region, a metal film is formed on the silicon compound film, a metal silicide film is formed, and an interlayer film is formed. Then, a barrier metal material film is formed on this interlayer film, then the barrier metal material film is patterned to obtain a barrier metal layer, and then the interlayer film is patterned to form a contact hole, and a wiring is formed in this contact hole. A method for manufacturing a semiconductor device, comprising a step of forming wiring by burying a material. 2. The method for manufacturing a semiconductor device according to claim 1, wherein the semiconductor device is a MOS transistor. 3. The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor device is a bipolar transistor. 4. A refractory silicide is formed on a semiconductor substrate, and impurities are ion-implanted into the refractory silicide.
Then, a method for manufacturing a semiconductor device, in which a junction region is formed by solid phase diffusion. 5. The heat resistant silicide is a layer formed by subjecting a metal film formed on a semiconductor substrate via a thin semiconductor compound film to a low temperature heat treatment and then a high temperature heat treatment. 4. The method for manufacturing a semiconductor device according to 4. 6. A metal-silicide film obtained by forming a metal film on a silicon compound film formed on the semiconductor substrate is formed on a semiconductor substrate, and a refractory metal-based material wiring is formed through the metal silicide film. Forming a semiconductor device. 7. The semiconductor device according to claim 6, which is a MOS transistor. 8. The semiconductor device according to claim 6, which is a bipolar transistor. 9. A silicon compound film is formed on a semiconductor substrate, a metal film is formed on the silicon compound film, a metal silicide film is formed, and a refractory metal-based material wiring is formed on the metal silicide film. A method of manufacturing a semiconductor device, comprising: 10. The method for manufacturing a semiconductor device according to claim 1, wherein the semiconductor device is a MOS transistor. 11. The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor device is a bipolar transistor. 12. A metal silicide film obtained by forming a connection hole on a semiconductor substrate and forming a metal film on a silicon compound film formed on the semiconductor substrate, wherein the metal silicide film is A semiconductor device formed only in the connection hole. 13. A metal silicide film obtained by forming a contact hole on a semiconductor substrate and forming a metal film on a silicon compound film formed on the semiconductor substrate. A semiconductor device in which an Al-based material wiring is formed only in the connection hole and via the metal silicide film. 14. A connection hole is formed on a semiconductor substrate, a silicon compound film is formed in the connection hole, a metal film is formed on the silicon compound film, and a metal silicide film is formed only in the connection hole. And a method of manufacturing a semiconductor device, further comprising: forming an Al-based material by sputtering at a high temperature. 15. The method of manufacturing a semiconductor device according to claim 14, wherein the high temperature state is 300 ° C. or higher. 16. A connection hole is formed on a semiconductor substrate, a silicon compound film is formed in the connection hole, a metal film is formed on the silicon compound film, and a metal silicide film is formed only in the connection hole. And a metal-based material by a CVD method.