JPH0661359A - Semiconductor device wiring connection and forming method thereof - Google Patents

Abstract

PURPOSE:To fully bury a wiring material in an opening so as to lessen a wiring connection in contact resistance by a method wherein an opening provided for an insulating layer penetrating an Si wiring layer and a wiring connection formed of a barrier layer provided for a part of the Si wiring layer which confronts the opening concerned are provided. CONSTITUTION:A wiring connection of a semiconductor device is formed to electrically connect an Si wiring layer 28A provided between insulating layers 26 and 40 to other wirings 24 and 50. The wiring connection concerned is composed of a through-hole 42 provided the insulating layers 26 and 40 penetrating the Si wiring layer 28A and a barrier layer 44 formed on a part 28B of the Si wiring layer 28A confronting the opening 42. A region of the barrier layer 44 which is located adjacent to the Si wiring layer 28A contains oxygen more than that adjacent to the opening 42. By this setup, as the barrier layer 44 is formed on a part of the Si wiring layer 28A which faces the opening 42, a wiring connection of this design can be lessened in contact, resistance and enhanced in barrier properties.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring connecting portion of a semiconductor device and a method for forming the wiring connecting portion.

[0002]

2. Description of the Related Art With the miniaturization of semiconductor devices, studies are underway to increase the number of layers of semiconductor elements. Calculating the reduction ratio of the cell area of a semiconductor device, the CMOS is
It has been found that the cell area can be reduced by 80% in the case of forming cells, but further cell reduction is being studied. As one means for that, in order to improve the degree of integration particularly in a memory device such as SRAM, a high resistance part is formed in a thin film transistor (TF).
There is a method in which the cell area is reduced by using T). For example, the document “High Density Dual-Acti
ve-Device-Layer (DUAL) -CMOS Structure with Vertical
Tungsten Plug-in Wiring ", K. Oyama, et el, Intern
ational Electron Devices Meeting (IEDM) 1990 Techn
As described in ical Digest pp 59, the cell area is reduced to 56% by adopting the so-called plug-in method in which a connection hole that penetrates a certain wiring layer and is electrically connected to this wiring layer is formed. Can be realized.

Along with the reduction of the cell area as described above, the connection hole in which the wiring material is embedded in the opening formed in the insulating layer is also miniaturized, which makes it difficult to embed the wiring material in the minute opening. Is increasing. In the so-called plug-in method, for example, to electrically connect a lower wiring layer formed in a semiconductor element, an upper wiring layer, and an intermediate wiring layer formed with an insulating layer between these wiring layers. In these insulating layers, an opening penetrating the intermediate wiring layer is provided, and aluminum (Al) used as a wiring is formed in the opening.
It is necessary to embed wiring materials such as

As one of the embedding methods, an aluminum embedding technique by a high temperature sputtering method has recently received attention. In this method, a semiconductor substrate is heated to a high temperature of hundreds of degrees to form an aluminum alloy by sputtering to reflow aluminum in the opening,
This is a technique of filling aluminum into the opening and flattening it. In this case, as the aluminum base, for example, T
When a material such as i that easily reacts with aluminum is used, the interfacial reaction between aluminum during film formation and Ti as a base improves the wettability between the two, and as a result, the aluminum spreads and good embedding is achieved. It is known to be possible.

An outline of the process in which the high temperature sputtering method is applied to the so-called plug-in method will be described below with reference to FIG.

[Step-10] First, the element isolation region 12 is formed in the semiconductor substrate 10.

[Step-20] Next, the gate oxide film 14 is formed, and then the polysilicon layer 16 and the WSi ₂ layer 1 are formed.
After depositing No. 8, patterning is performed to form a gate wiring portion, and then ion implantation is performed to form an LDD structure. After that, the side wall 2 is formed on the side wall of the gate wiring portion.
Form 0. Thus, the gate electrode region 22 including the gate oxide film 14, the polysilicon 16, the WSi ₂ 18 and the sidewall 20 is formed.

[Step-30] Next, ion implantation is performed to form the source / drain regions 24 (see FIG. 9A). The source / drain regions 24 formed on the semiconductor substrate are lower wiring layers electrically connected to other wiring layers through connection holes formed in the subsequent steps.

[Step-40] A first insulating layer 26 is formed on the entire surface, and a thin film transistor (T) is formed on the first insulating layer 26.
FT) is formed. For that purpose, first, a first polysilicon layer 28 for wiring and for forming source / drain regions is formed. This first polysilicon layer 28 becomes a wiring layer for the TFT. Then, a TFT gate oxide film 32 is formed on the first polysilicon layer 28, and a phosphorus-doped second polysilicon layer 34 for the TFT gate electrode is further deposited, and then the second polysilicon layer 34 is formed. The TFT gate electrode 36 is formed by patterning, and ion implantation is further performed to form the source / drain regions 38 for the TFT in the first polysilicon layer.

[Step-50] Next, a second insulating film 40 is deposited on the entire surface, patterned and etched,
A source layer formed on the semiconductor substrate through the second insulating layer 40, the first polysilicon layer 28, and the first insulating layer 26.
An opening 42 reaching the drain region 24 is formed (see FIG. 9B).

[Step-60] Then, in the opening, metal wiring layers 48 and 50 (for example, Al / Ti / TiON / T) are formed.
i structure) is formed. Next, resist patterning is performed, and upper layer wiring is formed by dry etching (see FIG. 9C). In this way, the connection hole in which the metal wiring material is embedded in the opening is completed. The connection holes electrically connect the lower wiring layer formed of the source / drain regions 24 formed in the semiconductor substrate, the wiring layer 28 for TFT, and the upper wiring 50.

[0012]

However, in the above process, since the wiring layer for the TFT and the aluminum are electrically connected via the barrier metal layer having the Ti / TiON / Ti structure, There is a problem that the contact resistance between the wiring layer for TFT and aluminum is high. Further, it is difficult to uniformly form such a barrier metal layer on the sidewall of the opening and on the exposed wiring layer for TFT, and with such a barrier metal layer alone,
There is a problem that aluminum cannot be prevented from penetrating into the TFT wiring layer. Further, there is a problem that the filling property of aluminum in the opening is poor due to the wettability between aluminum and the barrier metal layer.

As a technique for filling the opening, a method of forming a tungsten (W) plug in the opening is also known. Since tungsten is a refractory metal, forming a tungsten plug enables high-temperature treatment in the subsequent steps. Since W and Si easily react at about 600 ° C., for example, W diffuses into Si in the boundary region between Si and W of the TFT wiring layer exposed in the opening to form tungsten silicide. . There is a problem that voids are formed in the W plug due to the diffusion of W into Si. In addition, W diffuses into the silicon semiconductor substrate and junction leakage deteriorates. Therefore, even when the tungsten plug is used, there is a problem that the process temperature is limited.

The entire side wall of the opening including the TFT wiring layer exposed in the opening and the source exposed in the bottom of the opening.
By forming a TiSi ₂ layer in the drain region,
It is also possible to reduce the contact resistance between the aluminum buried in the opening and the TFT wiring layer or the lower wiring layer composed of the source / drain regions, and improve the aluminum embedding property by improving the wettability of aluminum. However, the T formed by the usual method
The iSi ₂ layer aggregates in a high temperature process of about 900 ° C., resulting in an increase in sheet resistance. For example, in an experiment relating to sheet resistance, 100Ω /
In some cases, the sheet resistance increased from □ to 300Ω / □.

As described above, in the case of forming an integrated circuit having fine connection holes on a mass production level, it has a low resistance value,
It has excellent heat resistance, stable and high barrier properties,
Furthermore, a wiring connection portion of a semiconductor device and a method of forming the wiring material, which can completely fill the wiring material in the opening, have not yet been known. Therefore, an object of the present invention is to provide a wiring connection portion of a semiconductor device and a method of forming the wiring connection portion, which can satisfy such requirements.

[0016]

The above object can be achieved by the first aspect of the present invention having the following features. That is, the first embodiment of the present invention, in which the Si-based wiring layer provided between the insulating layers is electrically connected to another wiring portion.
The wiring connection portion of the semiconductor device according to the embodiment of FIG.
As shown in the schematic partial cross-sectional view of the structure in (a)
It is characterized by comprising an opening formed in the insulating layer and penetrating the Si-based wiring layer, and (b) a barrier layer formed in the portion of the Si-based wiring layer facing the opening.

In the wiring connection portion of the semiconductor device according to the first aspect of the present invention, the barrier layer is preferably made of a metal silicide layer. Further, as shown in the schematic partial cross-sectional view in FIG. 1B, the region of the barrier layer made of metal silicide near the Si wiring layer contains more oxygen than the region near the opening. It is more preferable that the barrier layer made of metal silicide has high heat resistance.

The wiring connection portion of the semiconductor device according to the first aspect of the present invention can be formed by the method for forming the wiring connection portion of the semiconductor device according to the first aspect of the present invention having the following characteristics. it can. That is, the method for forming a wiring connecting portion according to the first aspect, in which the Si-based wiring layer provided between the insulating layers is electrically connected to another wiring portion,
(A) A step of forming an opening penetrating the Si-based wiring layer in the insulating layer, and (b) a step of forming a barrier layer in the portion of the Si-based wiring layer exposed in the opening. .

In the method for forming the wiring connection portion of the semiconductor device according to the first aspect of the present invention, the barrier layer is made of a metal silicide layer, and the step of forming the barrier layer of (b) comprises:
(B-1) A step of forming an oxide layer on the portion of the Si-based wiring layer exposed in the opening, and (b-2) forming a metal layer on the surface of the oxide layer on the side wall of the opening. It is preferable to include a silicidation step, (b-3) a step of removing the unreacted metal layer, and (b-4) an annealing step of subjecting the formed metal silicide layer to an annealing treatment at a high temperature. By the step of forming the barrier layer, the region of the barrier layer made of metal silicide near the Si wiring layer contains more oxygen than the region near the opening, and as a result, the barrier layer made of metal silicide has high heat resistance. Can be given.

The above object can be further achieved by the second aspect of the present invention having the following features. That is, the wiring connection portion of the semiconductor device according to the second aspect of the present invention, which electrically connects the Si-based wiring layer provided between the insulating layers to another wiring portion, is shown in FIG. As shown in the schematic partial cross-sectional view of the structure in (A), (a) an opening formed in the insulating layer and penetrating the Si-based wiring layer, and (b) a side wall of the opening and a surface on the opening. And a metal silicide layer formed on the surface of the (c) Si-based material thin layer.

In the wiring connection portion of the semiconductor device according to the second aspect of the present invention, as shown in the schematic partial sectional view of FIG. 2B, the Si-based wiring layer facing the opening is formed. It is desirable to further include a barrier layer formed of a metal silicide formed in the portion of. It is more preferable that the region near the Si wiring layer of the barrier layer made of the metal silicide contains more oxygen than the region near the opening, whereby the barrier layer made of the metal silicide has high heat resistance. Can be granted.

The wiring connecting portion of the semiconductor device according to the second aspect of the present invention can be formed by the method for forming the wiring connecting portion of the semiconductor device according to the second aspect of the present invention having the following characteristics. it can. That is, the method for forming the wiring connecting portion according to the second aspect, in which the Si-based wiring layer provided between the insulating layers is electrically connected to another wiring portion,
(A) a step of forming an opening in the insulating layer that penetrates the Si-based wiring layer; and (b) a sidewall of the opening and Si facing the opening.
A step of forming a Si-based material thin layer on the system wiring layer portion, and then forming an oxide layer on the surface of the Si-based material thin layer;
(C) A step of forming a metal layer on the surface of the Si-based material thin layer and silicidizing the metal layer, (d) a step of removing the unreacted metal layer, and (e) a formed metal silicide layer. And an annealing step of performing a high-temperature annealing treatment. By the step of forming the metal silicide layer, the region of the metal silicide layer near the Si-based material thin layer contains more oxygen than the region near the opening, and as a result, the metal silicide layer has high heat resistance. be able to.

In the method for forming the wiring connection portion of the semiconductor device according to the second aspect of the present invention, metal is formed in the portion of the Si-based wiring layer exposed in the opening between the step (a) and the step (b). It is desirable to form a barrier layer made of silicide. The step of forming the barrier layer is preferably a step of forming an oxide layer on the portion of the Si-based wiring layer exposed in the opening, and forming a metal layer on the surface of the oxide layer on the sidewall of the opening,
It is preferable to include a step of silicidizing the metal layer, a step of removing the unreacted metal layer, and an annealing step of subjecting the formed metal silicide layer to an annealing treatment at a high temperature. By the barrier layer forming step, a region of the barrier layer made of metal silicide in the vicinity of the Si wiring layer is
It contains more oxygen than the area near the opening, and as a result,
High heat resistance can be imparted to the barrier layer made of metal silicide.

Further, the above object can be achieved by the third aspect of the present invention having the following features. That is, the Si-based wiring layer exposed at the bottom of the opening formed in the insulating layer is electrically connected to another wiring portion.
The wiring connection portion of the semiconductor device according to the embodiment of FIG.
Alternatively, as shown in a schematic partial cross-sectional view of the structure in FIG. 2A, it is formed on or above the portion of the Si-based wiring layer exposed at least at the bottom of the opening and near the Si-based wiring layer. It is characterized by comprising a metal silicide layer in which the oxygen content of the region is higher than that of the region near the opening. The metal silicide layer may extend not only on the portion of the Si-based wiring layer exposed at the bottom of the opening but also on the Si-based wiring layer existing under the insulating layer.

[0025]

In the wiring connection portion of the semiconductor device according to the first aspect of the present invention, since the barrier layer is formed in the portion of the Si-based wiring layer facing the opening, the contact resistance is reduced.
A high barrier property can be obtained.

In the wiring connection portion of the semiconductor device according to the second aspect of the present invention, the thin layer of Si-based material is formed on the side wall of the opening and the portion of the Si-based wiring layer facing the opening,
Furthermore, since the metal silicide layer is formed on the surface of the Si-based material thin layer, it is particularly excellent in heat resistance. Moreover, since the wettability with the wiring material is excellent, the wiring material can be completely embedded in the opening.

In the wiring connection portion of the semiconductor device according to the third aspect of the present invention, in the metal silicide layer, the oxygen content rate in the region near the Si-based wiring layer is higher than the oxygen content rate in the region near the opening. It is characterized by having such a characteristic, and it can have especially excellent heat resistance.

[0028]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below based on embodiments with reference to the drawings.

(Example-1) Example-1 is an example in which the wiring connection portion of the semiconductor device and the method for forming the same according to the first and third aspects of the present invention are embodied. Below, FIG.
Each step will be described in detail with reference to FIG. 5, and the outline thereof is as follows.

[Step-100] to [Step-140] First, a Si wiring layer is formed between the insulating layers. For that purpose, first, the gate electrode region 22 and the source / drain regions 24 are formed on the semiconductor substrate 10 by the conventional method, and then the first insulating layer 26 is formed on the entire surface. Then the first
A thin film transistor (TFT) is formed on the insulating layer 26. In addition, a part 28A of the first polysilicon layer 28 formed for the TFT is provided between the insulating layers.
It becomes an i-system wiring layer. Next, the second insulating layer 40 is formed on the entire surface. [Step-150] After that, an opening penetrating the Si-based wiring layer is formed in the insulating layer. That is, the second insulating layer 40, Si
Opening 4 penetrating the system wiring layer 28A and the first insulating layer 26
Form 2. [Step-160] to [Step-180] Then, the opening 4
It is desirable to oxidize the portion 28B of the Si-based wiring layer 28A exposed at 2. Then, a barrier layer is formed on the portion of the Si-based wiring layer exposed in the opening. Preferably, the barrier layer comprises a titanium silicide layer.

Through these steps, as shown in the schematic partial cross-sectional view of the semiconductor device in FIG. 4B, the Si-based wiring layer 2 provided between the insulating layers 26 and 40.
A wiring connection portion of the semiconductor device for electrically connecting 8A to the other wiring portions 24 and 50 is formed. This wiring connection is
(A) Si-based wiring layer 2 formed on the insulating layers 26 and 40
8A, and the barrier layer 4 formed in (B) the portion 28B of the Si-based wiring layer facing this opening.
It consists of four. The barrier layer 44 is preferably made of a titanium silicide layer, and more preferably, the region near the Si wiring layer of the barrier layer 44 contains more oxygen than the region near the opening.

Further, by going through such steps,
As shown in FIG. 3B, the wiring connection of the semiconductor device in which the Si-based wiring layer 24 exposed at the bottom of the opening 42 formed in the insulating layer 26 is electrically connected to other wiring portions 28A and 50. Parts are formed. This wiring connection portion is formed on at least the portion of the Si-based wiring layer (source / drain region 24 in Example-1) exposed at the bottom of the opening, and the oxygen content in the region near the Si-based wiring layer is high. It is composed of the metal silicide layer 46 having a higher oxygen content rate in the region near the opening.

[Step-100] First, the element isolation region 12 is formed in the semiconductor substrate 10 by a conventional method. Next, the entire surface of the semiconductor substrate 10 is thermally oxidized to form a gate oxide film 14 having a film thickness of 12 nm. The conditions for forming the gate oxide film 14 can be, for example, used gas: H ₂ / O ₂ = 6/4 liters / minute Temperature: 850 ° C.

[Step-110] After that, the semiconductor substrate 10
Forming a gate electrode region. Therefore, the polysilicon layer 16 is deposited on the entire surface of the semiconductor substrate 10 to a thickness of 200 nm by, for example, the CVD method. The conditions of this deposition are, for example, used gas: SiH ₄ / PH ₃ / H ₂ = 500 / 0.35 /
The temperature may be 50 sccm, the pressure may be 580 ° C, and the pressure may be 79.8 Pa. Further, a WSi ₂ layer 18 is deposited to 100 nm on the polysilicon layer 16 by, for example, the CVD method. The deposition can be performed, for example, under the following conditions. Gas used: WF ₆ / SiH ₄ / He = 10/1000/3
60 sccm Temperature: 360 ° C Pressure: 26.6 Pa After that, resist patterning is performed and the polysilicon layer 16 and the WSi ₂ layer 18 are dry-etched. The conditions of dry etching can be, for example, used gas: C ₂ Cl ₃ F ₃ / SF ₆ = 65/5 sccm microwave power: 100 W RF power: 100 W pressure: 1.33 Pa. Next, in order to form an LDD structure, after ion-implanting the regions where the source / drain regions are to be formed, sidewalls 20 are formed on the sidewalls of the polysilicon layer 16 and the WSi ₂ layer 18. Thus, the gate electrode region 22 including the gate oxide film 14, the polysilicon layer 16, the WSi ₂ layer 18, and the sidewall 20 is formed. Then, ion implantation is performed to form the source / drain regions 24. Ion implantation can be performed, for example, under the following conditions. For NMOS: As ⁺ 50 keV 5 × 10 ¹⁵ /
cm ² PMOS: BF ₂ ⁺ 20 keV 3 × 10 ¹⁵ /
The process of cm ² or more is based on a general method for forming a semiconductor element. In Example-1, the lower wiring layer to be connected is the source / drain region 24.

[Step-120] Next, a first insulating layer 26 made of SiO ₂ and having a thickness of 500 nm is deposited on the entire surface by, eg, CVD. The CVD conditions are, for example, used gas: SiH ₄ / O ₂ / N ₂ = 250/250/10
The pressure may be 0 sccm, the pressure may be 13.3 Pa, and the temperature may be 420 ° C. In this way, the semiconductor element whose schematic partial cross-sectional view is shown in FIG.

[Step-130] Next, the first insulating layer 2
A thin film transistor (TFT) is formed on the substrate 6. Therefore, first, a thickness of 300 nm is formed on the first insulating layer 26.
The first polysilicon layer 28 is formed by the CVD method under the following conditions, for example. Gas used: SiH ₄ / PH ₃ / H ₂ = 500 / 0.35 /
50 sccm Temperature: 580 ° C. Pressure: 79.8 Pa A part 28A of the first polysilicon layer 28 becomes a Si-based wiring layer provided between the insulating layers.

Then, in order to form a TFT gate oxide film 32 having a thickness of 16 nm, the first polysilicon layer 28 is formed.
Oxidize the surface of. The conditions for forming the TFT gate oxide film 32 may be, for example, used gas: H ₂ / O ₂ = 6/4 liters / minute Temperature: 850 ° C. Then, a second polysilicon layer 34 having a thickness of 200 nm and doped with phosphorus for the gate electrode is formed.
Is formed on the TFT gate oxide film 32 by the CVD method under the following conditions, for example. Gas used: SiH ₄ / PH ₃ / H ₂ = 500 / 0.35 /
50 sccm Temperature: 580 ° C. Pressure: 79.8 Pa After that, resist patterning is performed and the TFT gate electrode portion 36 is completed by dry etching. The conditions of dry etching can be, for example, used gas: C ₂ Cl ₃ F ₃ / SF ₆ = 65/5 sccm microwave power: 100 W RF power: 100 W pressure: 1.33 Pa. Then, ion implantation is performed to form the source / drain regions 38 for the TFT. The ion implantation conditions are, for example, in the case of NMOS: As ⁺ 50 keV 5 × 10 ¹⁵ /
cm ² PMOS: BF ₂ ⁺ 20 keV 3 × 10 ¹⁵ /
It can be cm ² . In this way, the TFT is completed (see FIG. 3B).

[Step-140] Next, a second insulating layer 40 made of SiO ₂ and having a thickness of 500 nm is deposited on the entire surface by, eg, CVD. The CVD conditions are, for example, used gas: SiH ₄ / O ₂ / N ₂ = 250/250/10
The pressure may be 0 sccm, the pressure may be 13.3 Pa, and the temperature may be 420 ° C. Thus, the Si-based wiring layer 28A formed of a part of the first polysilicon layer 28 provided between the two insulating layers (the first insulating layer 26 and the second insulating layer 40) is formed.

[Step-150] Next, by performing resist patterning and dry etching,
The opening 42 is formed. The dry etching conditions can be, for example, used gas: C ₄ F ₈ = 50 sccm RF power: 1200 W pressure: 2 Pa. The opening 42 is formed in the second insulating layer 4
0, the Si-based wiring layer 28A, and the first insulating layer 26, and the bottom of the opening 42 extends to the source / drain region 24 formed in the semiconductor substrate 10 (FIG. 3C). reference).

[Step-160] Next, it is preferable to oxidize the entire surface. Oxidation treatment conditions can be, for example, used gas: O ₂ = 10 liters / minute, temperature: 850 ° C. time: 5 minutes. As a result, the portion 28B of the Si-based wiring layer 28A exposed in the opening 42 is oxidized to form the oxide layer 30 having a thickness of 3 nm (see FIG. 4A). Further, the surface of the source / drain region 24 formed on the semiconductor substrate 10 is also oxidized and the oxide layer 24 having a thickness of 3 nm is formed.
A is formed. This step is not always necessary. However, in order to stabilize the titanium silicide layer formed in the subsequent steps and to have high heat resistance, it is desirable to perform oxidation treatment.

[Step-170] Next, for example, Ti is deposited on the entire surface by a sputtering method. At this time, the semiconductor substrate 6
Hold at about 00 ° C. The sputtering conditions may be, for example, used gas: Ar = 40 sccm, sputter power: 1 kW, pressure: 0.04 Pa, and depositing 30 nm on the second insulating layer 40. Since the semiconductor substrate is held at about 600 ° C., Ti is the Si of the portion 28B of the Si-based wiring layer 28A exposed in the opening 42 and the Si of the source / drain region 24 exposed in the bottom of the opening 42. React with each other and diffuse into the opening. Since the Ti atoms flow in the opening, the coverage of Ti is good, the Ti is not overhanged, and the Ti layer is uniformly formed on the side wall and the bottom of the opening.

Ti reacts with the Si of the portion 28B of the Si-based wiring layer 28A exposed in the opening 42 through the oxide layer 30, if the oxide layer 30 is formed, and the Si-based wiring layer 28A. A TiSi _x layer is formed on the portion 28B of the. Further, Ti reacts with Si of the source / drain region 24 exposed at the bottom of the opening 42 through the oxide layer 24A when the oxide layer 24A is formed, and at the bottom of the opening 42, Ti reacts. A TiSi _x layer is formed.

In some cases, the semiconductor substrate is heated to 600 ° C.
After not depositing Ti, the Ti is deposited in the opening 42 including the portion 28B of the Si-based wiring layer 28A exposed in the opening 42 and the source / drain region 24 exposed in the bottom of the opening 42. By performing a heat treatment at about 650 ° C., a Ti to TiSi _X layer is deposited on the portion 28B of the Si-based wiring layer 28A exposed in the opening 42 and on the source / drain region 24 exposed at the bottom of the opening 42. Can also be formed.

[Step-180] Next, the semiconductor substrate is immersed in ammonia hydrogen peroxide (NH ₄ OH: H ₂ O ₂ : H ₂ O = 1: 2: 2) for 10 minutes to remove unreacted Ti. . After that, the TiSi _x layer is annealed in an inert gas such as N ₂ at 900 ° C. for 30 seconds, and the TiSi _x layer is stabilized with low resistance.
The iSi ₂ layers 44 and 46 are formed. Thus, TiSi is formed in the portion 28B of the Si-based wiring layer 28A exposed in the opening 42.
_A barrier layer consisting of _two layers 44 is formed. Further, a barrier layer made of the TiSi ₂ layer 46 is also formed on the bottom of the opening 42 (see FIG. 4B). [Step-160]
When the step of forming the oxide layer is performed, the region of the formed barrier layer near the Si wiring layer contains more oxygen than the region near the opening, and the barrier layer has excellent heat resistance. Can be granted. In addition, the formed opening 42
Of the titanium silicide layer 46 formed at the bottom of the
The region near the drain region contains more oxygen than the region near the opening, so that the titanium silicide layer 46 can be provided with excellent heat resistance. Incidentally, FIG. 6 (A)
15B and 15B show SIMS analysis results and AES analysis results showing the distribution state of oxygen in the titanium silicide layer.

[Step-190] Next, the barrier metal layer 48 made of, for example, Ti and the upper wiring layer 50 made of aluminum are formed (see FIG. 5). The barrier metal layer 48 (thickness 30 nm) can be formed by, for example, a sputtering method, and the formation conditions thereof are, for example, used gas: Ar = 100 sccm, sputtering power: 4 kW, pressure: 0.04 Pa, temperature: 600 ° C. You can Upper wiring layer 50 (film thickness 500n
m) can be formed by, for example, a high temperature aluminum sputtering method, and the forming conditions thereof can be, for example, used gas: Ar = 100 sccm, sputtering power: DC 22.5 kW, pressure: 0.04 Pa, temperature: 500 ° C. . Thereafter, resist patterning is performed and dry etching is performed to remove the upper wiring layer 50 and the barrier metal layer 48 made of unnecessary aluminum and deposited on the second insulating layer 40, thereby forming an upper wiring. After that, the semiconductor device is completed by going through a normal process. The dry etching can be performed under the following conditions using, for example, an RF application type ECR etcher. Gas used: BCl ₃ / Cl ₂ = 60/90 sccm Microwave power: 1 kW RF power: 50 W Pressure: 21.3 Pa Thus, the Si-based wiring layer 28A made of polysilicon
Are electrically connected to the source / drain regions 24 and the upper wiring layer 50, which are lower wiring layers, through the wiring connection portion of the present invention. The lower wiring layer that is the source / drain region 24 is electrically connected to the Si-based wiring layer 28A and the upper wiring 50 through a wiring connecting portion made of a metal silicide layer, specifically, a titanium silicide layer 46. It

(Example-2) Example-2 is an example in which the wiring connection portion of the semiconductor device and the method for forming the same according to the second and third aspects of the present invention are embodied. Hereinafter, each step will be described in detail with reference to FIGS. 3 and 7, and the outline thereof is as follows.

[Step-200] First, Si is provided between the insulating layers.
A system wiring layer is formed. For that purpose, first, the gate electrode region 22 and the source / drain regions 24 are formed on the semiconductor substrate 10 by the conventional method, and then the first insulating layer 26 is formed on the entire surface. Then, a thin film transistor (TFT) is formed on the first insulating layer 26. A portion 28A of the first polysilicon layer 28 formed for the TFT
Serves as a Si-based wiring layer provided between the insulating layers. Next, after forming the second insulating layer 40 on the entire surface, an opening penetrating the Si-based wiring layer is formed in the insulating layer. That is, the opening 42 that penetrates the second insulating layer 40, the Si-based wiring layer 28A, and the first insulating layer 26 is formed. [Step-210] to [Step-220] Next, the opening 42
After the Si-based material thin layer 60 made of polysilicon is formed therein, an oxide layer 62 is formed on the surface of the Si-based material thin layer 60. [Step-230] to [Step-240] Next, the oxide layer 6
A silicide layer 64 is formed on the surface of 2. [Step-250] After that, the barrier metal layer 48 and the upper wiring layer 50 made of aluminum are formed.

Through these steps, as shown in the schematic partial cross-sectional view of the semiconductor device in FIG. 7C, the Si-based wiring layer 2 provided between the insulating layers 26 and 40.
A wiring connection portion of the semiconductor device for electrically connecting 8A to the other wiring portions 24 and 50 is formed. This wiring connection is
(A) Si-based wiring layer 2 formed on the insulating layers 26 and 40
8A, and (b) the side wall of the opening 42 and the portion 28 of the Si-based wiring layer 28A facing the opening.
Si based material thin layer 60 formed on B, and (c) silicide layer 6 formed on the surface of this Si based material thin layer 60.
It consists of four.

Further, by going through such steps,
As shown in the schematic partial cross-sectional view of the semiconductor device in FIG. 7C, the Si-based wiring layer 24 exposed at the bottom of the opening 42 formed in the insulating layer 26 is connected to the other wiring portions 28A, 50. A wiring connection portion of the semiconductor device electrically connected to is formed.
This wiring connection portion is formed at least above the portion of the Si-based wiring layer exposed at the bottom of the opening, and the oxygen content in the region near the Si-based wiring layer is higher than the oxygen content in the region near the opening. , A metal silicide layer 64.

[Step-200] First, the element isolation region 12 is formed in the semiconductor substrate 10 by a conventional method. Next, the entire surface of the semiconductor substrate 10 is thermally oxidized to form a gate oxide film 14 having a film thickness of 12 nm. After that, the gate oxide film 14, the polysilicon layer 16, the WSi ₂ layer 18, the sidewall 2
A gate electrode region 22 of 0 is formed on the semiconductor substrate 10. Then, the source / drain regions 24 are formed. Further, the first insulating layer 26 is deposited on the entire surface. Then, a thin film transistor (TF) is formed on the first insulating layer 26.
T) is formed. Then, the second insulating layer 40 is deposited on the entire surface. Thus, two insulating layers (first insulating layer 26
And a second insulating layer 40), a Si-based wiring layer 28A formed of a part of the first polysilicon layer 28 is formed. Then, the opening 42 is formed. Opening 42
Penetrates the second insulating layer 40, the Si-based wiring layer 28A, and the first insulating layer 26, and the bottom of the opening 42 extends to the source / drain region 24 formed in the semiconductor substrate 10. . The above steps are the same as in Example-1 [Step-100].
To [Step-150], and detailed description thereof will be omitted. In this way, the semiconductor element whose schematic partial cross-sectional view is shown in FIG.

[Step-210] This step is different from Example-1. In this step, a polysilicon layer having a thickness of 50 nm is formed on the entire surface including the inside of the opening 42. The conditions for forming the polysilicon layer are, for example, using gas: SiH ₄ / He / N ₂ = 100/400/20
The temperature may be 0 sccm, 610 ° C., and the pressure may be 70 Pa. Then, the entire polysilicon layer is etched back to leave the Si-based material thin layer 60 made of polysilicon only in the opening 42 (see FIG. 7A).
The conditions of the etch back are, for example, used gas: C ₂ Cl ₃ F ₃ / SF ₆ = 40/30 sc
cm Microwave power: 700 W RF power: 50 W Pressure: 1.33 Pa can be used. As a result, the side wall of the opening 42, the portion 2 exposed in the opening 42 of the Si-based wiring layer 28A.
8B and the source / drain region 24 at the bottom of the opening 42, a Si-based material thin layer 60 is formed.

[Step-220] Next, the entire surface is oxidized. The processing conditions can be, for example, used gas: O ₂ = 10 liters / minute, temperature: 850 ° C. time: 5 minutes. As a result, a 3 nm-thick oxide layer 6 is formed on the surface of the Si-based material thin layer 60 made of polysilicon.
2 is formed (see FIG. 7B).

[Step-230] Next, for example, Ti is deposited on the entire surface by a sputtering method. At this time, the semiconductor substrate 6
Hold at about 00 ° C. The sputtering conditions may be, for example, used gas: Ar = 40 sccm, sputter power: 1 kW, pressure: 0.04 Pa, and depositing 30 nm on the second insulating layer 40. Since the semiconductor substrate is held at about 600 ° C., Ti is the Si formed in the opening 42.
TiS reacts with Si of the Si-based material thin layer 60 one after another through the oxide film 62 formed on the surface of the system-based thin layer 60 to form TiS.
While becoming i _X , it diffuses into the Si-based material thin layer. As a result, coverage of TiSi _X is good, TiSi _X
TiSi _X without any overhang shape
The layer is evenly formed on the sidewalls and bottom of the opening.

In some cases, the semiconductor substrate is heated to 600 ° C.
After depositing Ti on the oxide film 62 without holding it to a certain degree,
It is also possible to form a TiSi _x layer on the Si-based material thin layer by performing a heat treatment at about 650 ° C.

[0055] [Step-240] Next, ammonia hydrogen peroxide _{(NH 4 OH: H 2 O} 2: H 2 O = 1: 2: 2) The semiconductor substrate was immersed for 10 minutes in, to remove unreacted Ti . After that, the TiSi _x layer is annealed in an inert gas such as N ₂ at 900 ° C. for 30 seconds, and the TiSi _x layer is stabilized with low resistance.
The iSi ₂ layer 64 is formed. Thus, the Si in the opening 42 is
A silicide layer 64 made of TiSi ₂ is formed on the surface of the thin base material layer 60 (see FIG. 7C).

[Step-250] Next, for example, a barrier metal layer 48 made of Ti and an upper wiring layer 50 made of aluminum are formed. This step can be performed in the same manner as in [Step-190] of Example-1, and detailed description thereof will be omitted. Thus, Si made of polysilicon
The system wiring layer 28A includes the source / drain regions 24 and the upper wiring layer 5 which are lower wiring layers via the wiring connection portion of the present invention.
Electrically connected to 0. Due to the formation process of the silicide layer 64, the region of the silicide layer near the Si-based material thin layer and the source / drain regions contains more oxygen than the region near the openings, and as a result, the silicide layer has high heat resistance. Can be given. Further, the lower wiring layer which is the source / drain region 24 is electrically connected to the Si-based wiring layer 28A and the upper wiring 50 through a wiring connecting portion made of a metal silicide layer, specifically, a titanium silicide layer 64. It

(Example-3) Example-3 is an example in which the wiring connecting portions of the semiconductor device according to the first and second aspects of the present invention and the forming method thereof are combined. Hereinafter, FIG. 3 and FIG.
Each step will be described in detail with reference to FIGS. 8A and 8B, and the outline thereof is as follows.

[Step-300] First, Si is formed between the insulating layers.
A system wiring layer is formed. For that purpose, first, the gate electrode region 22 and the source / drain regions 24 are formed on the semiconductor substrate 10 by the conventional method, and then the first insulating layer 26 is formed on the entire surface. Then, a thin film transistor (TFT) is formed on the first insulating layer 26. A portion 28A of the first polysilicon layer 28 formed for the TFT
Serves as a Si-based wiring layer provided between the insulating layers. Next, after forming the second insulating layer 40 on the entire surface, an opening penetrating the Si-based wiring layer is formed in the insulating layer. That is, the opening 42 that penetrates the second insulating layer 40, the Si-based wiring layer 28A, and the first insulating layer 26 is formed. [Step-320] to [Step-340] Next, the opening 4
It is desirable to oxidize the portion 28B of the Si-based wiring layer 28A exposed at 2. Then, a barrier layer is formed on the portion of the Si-based wiring layer exposed in the opening. Preferably, the barrier layer comprises a titanium silicide layer. [Step-350] to [Step-360] Next, the opening 42
After the Si-based material thin layer 60 made of polysilicon is formed therein, an oxide layer 62 is formed on the surface of the Si-based material thin layer 60. [Step-370] to [Step-380] Next, the silicide layer 64 is formed on the surface of the Si-based material thin layer 60, more specifically, on the surface of the oxide layer 62. [Step-390] After that, the barrier metal layer 48 and the upper wiring layer 50 made of aluminum are formed.

Through these steps, as shown in the schematic partial cross-sectional view of the semiconductor device in FIG. 8C, the Si-based wiring layer 2 provided between the insulating layers 26 and 40.
A wiring connection portion of the semiconductor device for electrically connecting 8A to the other wiring portions 24 and 50 is formed. This wiring connection is
(A) Si-based wiring layer 2 formed on the insulating layers 26 and 40
8A, and (b) the side wall of the opening 42 and the portion 28 of the Si-based wiring layer 28A facing the opening.
Si based material thin layer 60 formed on B, and (c) silicide layer 6 formed on the surface of this Si based material thin layer 60.
4 and (4) a silicide layer 44 formed on the portion 28B of the Si-based wiring layer 28A facing the opening.

[Step-300] First, the element isolation region 12 is formed in the semiconductor substrate 10 by the conventional method. Next, the entire surface of the semiconductor substrate 10 is thermally oxidized to form a gate oxide film 14 having a film thickness of 12 nm. Then, the gate oxide film 14, the polysilicon layer 16, the WSi ₂ layer 18, the sidewall 2
A gate electrode region 22 of 0 is formed on the semiconductor substrate 10. Then, the source / drain regions 24 are formed. Then, the first insulating layer 26 is deposited on the entire surface. Then, a thin film transistor (TF) is formed on the first insulating layer 26.
T) is formed. Further, the second insulating layer 40 is deposited on the entire surface. Thus, the Si-based wiring layer 28A formed of a part of the first polysilicon layer provided between the two insulating layers (the first insulating layer 26 and the second insulating layer 40) is formed. Then, the opening 42 is formed. The opening 42 is formed by the second insulating layer 40, the Si-based wiring layer 28A, the first insulating layer 2
6 and the bottom of the opening 42 is formed on the semiconductor substrate 10
To the source / drain regions 24 formed in the. The above steps are from [Step-100] of Example-1.
This can be the same as in [Step-150], and detailed description thereof will be omitted. In this way, the semiconductor element whose schematic partial cross-sectional view is shown in FIG.

[Step-320] Next, it is desirable to oxidize the entire surface. This step can be performed in the same manner as in [Step-160] of Example-1. As a result, the portion 2 of the Si-based wiring layer 28A exposed in the opening 42 is exposed.
8B is oxidized to form an oxide layer 30 having a thickness of 3 nm. In addition, the surface of the source / drain region 24 formed on the semiconductor substrate 10 is also oxidized, and the oxide layer 24 having a thickness of 3 nm is formed.
A is formed (see FIG. 4A).

[Step-330] Next, for example, Ti is deposited on the entire surface by a sputtering method. At this time, the semiconductor substrate 6
Hold at about 00 ° C. This step can be the same as [Step-170] of Example-1. As a result, Ti is added to the Si-based wiring layer 28 exposed in the opening 42.
When the oxide layer 30 is formed, it reacts with Si in the A portion 28B through the oxide layer 30, and the Si-based wiring layer 28
A TiSi _x layer is formed on the A portion 28B. Also, T
i reacts with Si of the source / drain region 24 exposed at the bottom of the opening 42 through the oxide layer 24A when the oxide layer 24A is formed, and at the bottom of the opening 42, a TiSi _X layer is formed. Is formed.

[Step-340] Next, the semiconductor substrate is immersed in ammonia hydrogen peroxide (NH ₄ OH: H ₂ O ₂ : H ₂ O = 1: 2: 2) for 10 minutes to remove unreacted Ti. . After that, the TiSi _x layer is annealed in an inert gas such as N ₂ at 900 ° C. for 30 seconds, and the TiSi _x layer is stabilized with low resistance.
The iSi ₂ layers 44 and 46 are formed. Thus, TiSi is formed in the portion 28B of the Si-based wiring layer 28A exposed in the opening 42.
_A barrier layer consisting of _two layers 44 is formed. Further, the TiSi ₂ layer 46 is also formed on the bottom of the opening 42 (see FIG. 4B). This step is the same as that of [Step-18 in Example-1].
0].

[Step-350] Next, a polysilicon layer having a thickness of 50 nm is formed on the entire surface including the inside of the opening 42.
After that, the polysilicon layer is entirely etched back to form the Si-based material thin layer 6 made of polysilicon only in the opening 42.
Leave 0 (see FIG. 8A). As a result, the TiSi ₂ layer 46 on the side wall of the opening 42, on the portion 28B exposed in the opening of the Si-based wiring layer 28A, and on the bottom of the opening 42 is formed.
A thin layer 60 of Si-based material is formed on the upper surface. This step can be similar to [Step-210] of Example-2.

[Step-360] Next, an oxidation treatment is applied to the entire surface. As a result, a 3 nm-thick oxide layer 62 is formed on the surface of the Si-based material thin layer 60 made of polysilicon (see FIG. 8B). This step can be performed in the same manner as in [Step-220] of Example-2.

[Step-370] Next, for example, Ti is deposited on the entire surface by a sputtering method. At this time, the semiconductor substrate 6
Hold at about 00 ° C. Since the semiconductor substrate is held at about 600 ° C., Ti is contained in the Si-based material thin layer 60 through the oxide film 62 formed on the surface of the Si-based material thin layer 60 formed in the opening 42. Reacts with Si one after another, T
While becoming iSi _x , it diffuses into the thin layer of Si-based material.
As a result, the coverage of TiSi _x is good, and the Ti
Si _X has no overhang shape, and Ti
A Si _x layer is uniformly formed on the sidewalls and bottom of the opening.
This step can be performed in the same manner as in [Step-230] of Example-2.

[Step-380] Next, the semiconductor substrate is immersed in ammonia hydrogen peroxide (NH ₄ OH: H ₂ O ₂ : H ₂ O = 1: 2: 2) for 10 minutes to remove unreacted Ti. . After that, the TiSi _x layer is annealed in an inert gas such as N ₂ at 900 ° C. for 30 seconds, and the TiSi _x layer is stabilized with low resistance.
The iSi ₂ layer 64 is formed. Thus, the Si in the opening 42 is
A silicide layer 64 made of TiSi ₂ is formed on the surface of the thin base material layer 60 (see FIG. 8C). This step can be performed in the same manner as in [Step-240] of Example-2.

[Step-390] Next, a barrier metal layer 48 made of, for example, Ti and an upper wiring layer 50 made of aluminum are formed. This step can be performed in the same manner as in [Step-190] of Example-1, and detailed description thereof will be omitted. Thus, Si made of polysilicon
The system wiring layer 28A includes the source / drain regions 24 and the upper wiring layer 5 which are lower wiring layers via the wiring connection portion of the present invention.
Electrically connected to 0. When the step of forming an oxide layer in [step-320] is performed, the region of the formed barrier layer near the Si wiring layer contains more oxygen than the region near the opening, and Excellent heat resistance can be imparted to the layer. Further, due to the step of forming the silicide layer 64, the region of the silicide layer near the Si-based material thin layer and the source / drain regions contains more oxygen than the region near the openings, and as a result, the silicide layer has high heat resistance. It is possible to impart sex.

Although the present invention has been described based on the preferred embodiments, the present invention is not limited to these embodiments. As the lower wiring layer, the source / drain region has been described as an example, but the method of the present invention can be applied to various wiring layers such as a wiring layer made of a semiconductor material or a metal formed below the gate electrode portion, contact hole or via hole. Can be applied.

As a wiring material for filling the upper wiring layer or the opening, a metal such as aluminum alloy, Cu, Ag, W or Mo, polysilicon, or the like is used instead of aluminum.
Semiconductor materials such as amorphous silicon and single crystal silicon can be used. Ti as a barrier metal layer
Not only TiN, Ti / TiN, Ti / TiN / T
i, TiSi ₂ / TiN, TiON, Ti / TiON,
TiSi ₂ / TiON, TiW, TiB, ZrN,
Refractory metals such as W and Mo and various silicides such as MoSi ₂ and WSi ₂ can be used.

The materials, conditions, numerical values, etc. used in each step are merely examples, and can be changed as appropriate. In addition to TiSi ₂ , various silicides such as Co, nitrides such as Ti, refractory metals such as Ti, Ni, W and Mo, noble metals, transition metals and semiconductor materials can be used as the barrier layer.

As the metal silicide layer formed on the Si-based material thin layer, in addition to TiSi ₂ , W, Mo, Ni, C
Various silicides such as o can be used.

The barrier layer or the silicide layer is formed by
Not only the sputtering method but also the EB vapor deposition method, the CVD method or the like can be used.

As the insulating layer, in addition to SiO ₂ , SiN
, PSG, BPSG, BSG, AsSG, PbSG,
SbSG, SOG, SiON, etc. can be used.

As the Si-based wiring layer, amorphous silicon or epitaxial silicon can be used in addition to polysilicon. The method for forming the Si-based wiring layer is C
Other than VD, a sputtering method can be used. Si
The system wiring layer has been described by exemplifying the one for the TFT, but the invention is not limited to this and the present invention can be applied to various Si system wiring layers.

[0076]

In the wiring connecting portion of the semiconductor device according to the first aspect of the present invention, the barrier layer faces the opening portion of Si.
Since it is formed in the system wiring layer, it is possible to reduce the contact resistance between the Si system wiring layer and the wiring material when the wiring material is embedded in the opening in a later step. Further, it is possible to prevent the penetration of the wiring material into the Si-based wiring layer with high reliability.

In the wiring connection portion of the semiconductor device according to the second aspect of the present invention, the thin layer of Si-based material is formed on the side wall of the opening and on the portion of the Si-based wiring layer facing the opening,
Furthermore, since the metal silicide layer is formed on the surface of the Si-based material thin layer, the contact resistance between the Si-based wiring layer and the wiring material can be reduced when the wiring material is embedded in the opening in a later step. . Further, it is possible to prevent the penetration of the wiring material into the Si-based wiring layer with high reliability. Since this metal silicide layer is formed on the Si-based material thin layer, it is particularly excellent in heat resistance and excellent in wettability with the wiring material, so that the wiring material can be completely embedded in the opening. .

In the wiring connection portion of the semiconductor device according to the third aspect of the present invention, in the metal silicide layer, the oxygen content rate in the region near the Si-based wiring layer is higher than the oxygen content rate in the region near the opening. With such a feature, when the wiring material is embedded in the opening in a later step, the contact resistance between the Si-based wiring layer and the wiring material can be reduced, and the Si-based wiring material can be used. Not only can penetration into the wiring layer be prevented with high reliability, but this metal silicide layer is also particularly excellent in heat resistance and excellent in wettability with the wiring material.

[Brief description of drawings]

FIG. 1 is a schematic partial cross-sectional view showing an outline of the structure of a wiring connection portion of a semiconductor device according to first and third aspects of the present invention.

FIG. 2 is a schematic partial cross-sectional view showing the outline of the structure of the wiring connection portion of the semiconductor device according to the second aspect and the third aspect of the present invention.

FIG. 3 is a schematic partial cross-sectional view of a semiconductor element for explaining each step of the method for forming the wiring connection portion of the semiconductor device according to the first aspect of the present invention.

FIG. 4 is a schematic partial cross-sectional view of the semiconductor element, for explaining each step of the method for forming the wiring connection portion, following FIG. 3;

FIG. 5 is a schematic partial cross-sectional view of the semiconductor element, for explaining each step of the method for forming the wiring connection portion, following FIG. 4;

FIG. 6 is a graph showing SIMS analysis results and AES analysis results showing a distribution state of oxygen in a titanium silicide layer.

FIG. 7 is a schematic partial cross-sectional view of a semiconductor element for explaining a step of a method for forming a wiring connection portion of a semiconductor device according to a second aspect of the present invention.

FIG. 8 is a schematic partial cross-sectional view of a semiconductor element for explaining each step in a preferred embodiment of a method for forming a wiring connection portion of a semiconductor device according to a second aspect of the present invention.

FIG. 9 is a diagram for explaining each step of a conventional so-called plug-in method.

[Explanation of symbols]

10 Semiconductor Substrate 12 Element Isolation Region 14 Gate Oxide Film 16 Polysilicon Layer 18 WSi ₂ Layer 20 Sidewall 22 Gate Electrode Region 24 Source / Drain Region 24A Oxide Layer 26 First Insulating Layer 28 Polysilicon Layer 28A Si-based Wiring Layer 28B Portion of Si-based wiring layer exposed in opening 30 Oxide layer 32 TFT gate oxide film 34 Polysilicon layer 36 TFT gate electrode part 38 TFT source / drain region 40 Second insulating layer 42 Opening 44 TiSi ₂ Layer 46 TiSi ₂ layer 48 Barrier metal layer 50 Upper wiring layer 60 Si-based material thin layer 62 Oxide layer 64 Silicide layer

Claims (10)

[Claims] 1. A wiring connecting portion of a semiconductor device for electrically connecting an Si-based wiring layer provided between insulating layers to another wiring portion, comprising: A wiring connection portion of a semiconductor device, comprising: an opening penetrating the Si-based wiring layer; and (b) a barrier layer formed in a portion of the Si-based wiring layer facing the opening. 2. The wiring connection portion of the semiconductor device according to claim 1, wherein the barrier layer is made of a metal silicide layer. 3. The wiring connecting portion of the semiconductor device according to claim 2, wherein the region of the metal silicide layer near the Si wiring layer contains more oxygen than the region near the opening. . 4. A wiring connecting portion of a semiconductor device for electrically connecting an Si-based wiring layer provided between insulating layers to another wiring portion, the wiring connecting portion being formed on the insulating layer and comprising: An opening penetrating the Si-based wiring layer; (b) a Si-based material thin layer formed on a side wall of the opening and a portion of the Si-based wiring layer facing the opening; A wiring connection portion of a semiconductor device, comprising a metal silicide layer formed on the surface of a thin material layer. 5. The wiring connecting portion according to claim 4, further comprising a barrier layer formed of a metal silicide formed in a portion of the Si-based wiring layer facing the opening. 6. A wiring connecting portion of a semiconductor device for electrically connecting a Si wiring layer exposed at the bottom of an opening formed in an insulating layer to another wiring portion, the wiring connecting portion being exposed at least at the bottom of the opening. A semiconductor device, which is formed on a portion of the Si-based wiring layer and is formed of a metal silicide layer in which an oxygen content in a region near the Si-based wiring layer is higher than an oxygen content in a region near the opening. Wiring connection part. 7. A method for forming a wiring connection portion of a semiconductor device, which comprises electrically connecting an Si-based wiring layer provided between insulating layers to another wiring portion, comprising: Formation of a wiring connection part, which comprises: a step of forming an opening penetrating the wiring layer in the insulating layer; and (b) a step of forming a barrier layer in a portion of the Si-based wiring layer exposed in the opening part. Method. 8. The barrier layer is made of a metal silicide layer, and the step of forming the barrier layer includes the step of: (b-1) forming an oxide layer in a portion of the Si-based wiring layer exposed in the opening; (B-2) a step of forming a metal layer on the surface of the oxide layer on the side wall of the opening and siliciding the metal layer; (b-3) a step of removing the unreacted metal layer; The method of forming a wiring connection part according to claim 7, further comprising: an annealing step of subjecting the formed metal silicide layer to an annealing treatment at a high temperature. 9. A method for forming a wiring connection portion of a semiconductor device, comprising electrically connecting an Si-based wiring layer provided between insulating layers to another wiring portion, the method comprising: A step of forming an opening penetrating the wiring layer in the insulating layer, and (b) forming a Si-based material thin layer on the sidewall of the opening and on the portion of the Si-based wiring layer facing the opening, and then A step of forming an oxide layer on the surface of the Si-based material thin layer; (c) a step of forming a metal layer on the surface of the Si-based material thin layer and siliciding the metal layer; A method for forming a wiring connection portion, which comprises: a step of removing the metal layer; and (e) an annealing step of subjecting the formed metal silicide layer to an annealing treatment at a high temperature. 10. The barrier layer made of metal silicide is formed between the steps (a) and (b) in the portion of the Si-based wiring layer exposed in the opening. Method for forming wiring connection part.