JP3608515B2 - Wiring structure and MOS transistor in semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a wiring structure and a wiring forming method in a semiconductor device, and a MOS transistor.
[0002]
[Prior art]
As semiconductor devices are highly integrated, the junction depth is becoming shallower. When the dimensional rule of the semiconductor device is at a level of 0.1 μm, the sheet resistance of the junction region becomes 1 kΩ / □ or more, which causes a problem that the response speed of the semiconductor element becomes slow. One method for solving this problem is to form CoSi on the surface of the source / drain region formed in the semiconductor substrate.₂TiSi₂There is a method of forming a silicide such as.
[0003]
In order to electrically connect the source / drain regions and the upper wiring layer, it is necessary to form connection holes. After forming an insulating layer covering the source / drain region, the connection hole forms an opening in the insulating layer above the source / drain region, forms a barrier layer on the insulating layer including the opening, and The metal wiring material is deposited on the barrier layer to fill the opening with the barrier layer and the metal wiring material. The barrier layer is formed to suppress a reaction between the source / drain regions and the metal wiring material in the opening.
[0004]
As the dimensional rule of the semiconductor device becomes finer, the diameter of the connection hole tends to become finer. As a result, there is a problem that the coverage of the barrier layer in the opening is lowered, and the barrier property of the barrier layer is lowered.
[0005]
Here, an outline of a conventional semiconductor device manufacturing process will be briefly described with reference to FIG.
[0006]
[Step-10]
An element isolation region 12 and a gate electrode 14 are formed on the semiconductor substrate 10 by a conventional method.
[0007]
[Step-20]
Ion implantation is performed to form an LDD (Lightly-Doped Drain) structure, and then a gate sidewall 16 is formed, and then ion implantation is performed to form a lower-layer conductor region 18 composed of source / drain regions (FIG. 6 ( A)).
[0008]
[Step-30]
In order to reduce the sheet resistance of the lower conductor region 18 composed of source / drain regions, CoSi is formed on the surface of the lower conductor region 18.₂A silicide layer 100 is formed (see FIG. 6B). For this purpose, a Co layer is formed on the entire surface, and then heat treatment is performed to react Si in the lower conductor region 18 with Co in the Co layer.₂Layer 100 is formed. The unreacted Co layer is selectively removed with hydrochloric acid / hydrogen peroxide.
[0009]
[Step-40]
Thereafter, an insulating layer 22 is formed on the entire surface, and an opening 24 is formed above the lower conductor region 18 (see FIG. 6C).
[0010]
[Step-50]
Next, a barrier layer (consisting of a Ti layer / TiN layer from the bottom) 102 is formed on the insulating layer 22 including the opening 24 by sputtering, for example, and a tungsten layer 104 is further deposited on the entire surface by CVD. Then, the tungsten layer 104 and the barrier layer 102 on the insulating layer 22 are selectively removed to form a connection hole 28 made of a tungsten plug in the opening 24 (see FIG. 7A). Next, from the bottom, a Ti layer / TiON layer / Al—Si layer is deposited on the entire surface by sputtering, and then these layers are patterned to form wiring 106 (see FIG. 7B). . Reference numeral 106A indicates a Ti layer / TiON layer.
[0011]
In the above process, since the barrier layer 102 formed in the opening 24 is formed by the sputtering method, the coverage of the barrier layer 102 in the opening 24 becomes very poor as the aspect ratio of the opening 24 increases. . As a result, the thickness of the barrier layer 102 at the bottom of the opening 24 is reduced. For this reason, when depositing the tungsten layer 104 by the CVD method, the source gas for CVD (WF₆) Erodes the barrier layer 102 by fluorine contained therein, and further corrodes the lower conductor region (source / drain region) 18 with fluorine. As a result, there arises a problem that the junction leakage increases.
[0012]
As a method for solving the coverage problem of the barrier layer 102 in the opening 24, formation of a barrier layer composed of a Ti layer / TiN layer by a CVD method can be mentioned. When the CVD method is used, the coverage problem of the barrier layer 102 at the bottom of the opening 24 can be solved. However, since the TiN layer formed by the CVD method is polycrystalline, when a high temperature heat treatment such as a later diffusion process or annealing process is performed on the semiconductor substrate, the TiN grain boundary part is corroded by fluorine, There is a problem that the metal wiring material in the connection hole 28 diffuses in the TiN grain boundary portion and corrodes the semiconductor substrate. That is, it cannot be said that the polycrystalline TiN layer has a sufficient barrier property.
[0013]
In order to solve the problem caused by the polycrystallinity of the TiN layer, the present applicant has proposed to epitaxially grow a single crystal TiN layer directly on a silicon semiconductor substrate (see Japanese Patent Application No. 5-69197).
[0014]
[Problems to be solved by the invention]
However, even if a single crystal TiN layer is simply formed on a silicon semiconductor substrate, it is difficult to obtain a good electrical ohmic junction. This is because there is a natural oxide film on the semiconductor substrate, and even if a TiN layer is formed on the natural oxide film, the TiN layer cannot reduce the natural oxide film, so that electrical conduction is difficult to take. To do. Further, when the natural oxide film remains, there is a problem that the TiN layer is difficult to epitaxially grow on the semiconductor substrate.
[0015]
Examples of methods for solving these problems include the following methods. That is, before forming the TiN layer, the natural oxide film is reduced with hydrogen plasma. This removes the natural oxide film and exposes the clean surface of the silicon semiconductor substrate. Thereafter, a CVD source gas is introduced to form a TiN layer by a CVD method.
[0016]
However, as a problem in this method, the surface of the silicon semiconductor substrate is exposed to a hydrogen plasma treatment as a pretreatment before the formation of the TiN layer. As a result, hydrogen atoms enter the silicon crystal, crystal defects occur in the silicon crystal, and junction leakage increases.
[0017]
Further, when a TiN layer is formed on a silicon semiconductor substrate by a CVD method, the surface of the silicon semiconductor substrate is exposed to nitrogen plasma, so that a thin SiN film is formed on the surface of the silicon semiconductor substrate and the contact resistance increases. There is also.
[0018]
Furthermore, in this method, it is a condition that the silicon surface is exposed on the surface of the source / drain region. Therefore, a silicide layer cannot be formed on the surface of the source / drain region in order to reduce the sheet resistance of the source / drain region as described above. That is, there is a problem that a single crystal TiN layer cannot be formed on the silicide layer.
[0019]
Accordingly, an object of the present invention is to reduce the sheet resistance of the lower conductor region, to suppress an increase in contact resistance and junction leakage, and to provide a wiring structure in a semiconductor device excellent in barrier properties and a method for forming the same And to provide a MOS transistor.
[0020]
[Means for Solving the Problems]
The above purpose is to connect a lower conductor region formed on the semiconductor substrate, an upper wiring layer formed on an insulating layer covering the lower conductor region, and a connection hole for electrically connecting the lower conductor region and the upper wiring layer. A wiring structure in a semiconductor device comprising:
From the semiconductor substrate side, single crystal CoSi is formed at the bottom of the connection hole.₂This can be achieved by the wiring structure of the present invention characterized in that a layer and a single crystal TiN layer are formed.
[0021]
In the wiring structure of the present invention, the semiconductor substrate is preferably made of a silicon semiconductor substrate. The orientation of the silicon semiconductor substrate is preferably (100).
[0022]
Alternatively, the above purpose is to electrically connect the lower conductor region formed on the semiconductor substrate, the upper wiring layer formed on the insulating layer covering the lower conductor region, and the lower conductor region and the upper wiring layer. A wiring formation method for forming a wiring structure in a semiconductor device, comprising a connection hole that comprises:
At least at the bottom of the connection hole, single crystal CoSi₂A step of epitaxially growing the layer, and single crystal CoSi₂This can be achieved by the wiring forming method of the present invention including the step of epitaxially growing a single crystal TiN layer on the layer.
[0023]
In the wiring formation method of the present invention, the degree of vacuum of the atmosphere before epitaxial growth of the single crystal TiN layer is 1.3 × 10^-5It is desirable that it is Pa or less. Furthermore, before epitaxially growing the single crystal TiN layer, the single crystal CoSi₂It is preferable to include a step of removing the natural oxide film formed on the layer surface by hydrogen plasma treatment.
[0024]
Further, the above object is to electrically connect the source / drain regions formed on the semiconductor substrate, the upper wiring layer formed on the insulating layer covering the source / drain regions, and the source / drain regions and the upper wiring layer. A MOS transistor having a wiring structure comprising a connection hole to be electrically connected,
A single crystal CoSi is formed on the bottom of the connection hole from the semiconductor substrate side.₂This can be achieved by the MOS transistor of the present invention characterized in that a layer and a single crystal TiN layer are formed.
[0025]
In the present invention, at least the bottom of the connection hole has a single crystal CoSi.₂The layer is formed, and the sheet resistance of the lower conductor region can be reduced. Single crystal CoSi₂On the layer, a single crystal TiN layer having excellent barrier properties is formed. When the natural oxide film is removed by hydrogen plasma treatment before the TiN layer is formed, CoSi₂Since the layer is formed, entry of hydrogen atoms into the silicon crystal can be suppressed. Furthermore, when the TiN layer is formed, the surface of the silicon semiconductor substrate is not exposed to nitrogen plasma, and the formation of the SiN film can be prevented.
[0026]
Conventionally, CoSi₂Is known to grow epitaxially on a (111) silicon semiconductor substrate. However, (100) silicon semiconductor substrates are often used in the production of ordinary MOS transistors. (100) CoSi on a silicon semiconductor substrate₂Is epitaxially grown, two layers of Co layer / Ti layer are formed in advance on the semiconductor substrate. After that, when heat treatment is applied to these two layers, single crystal CoSi₂A layer / Si structure can be obtained. At this time, single crystal CoSi₂The surface of the layer is TiO_xA layer is formed.
[0027]
This single crystal CoSi₂In order to epitaxially grow a single crystal TiN layer on the layer, hydrogen plasma treatment is performed in an apparatus for forming a TiN layer, and single crystal CoSi is formed.₂TiO on the surface of the layer_xNeed to be reduced and removed. Subsequently, a single crystal TiN layer / single crystal CoSi layer is formed by continuously forming a single crystal TiN layer by a CVD method.₂A layer / Si structure can be obtained.
[0028]
Here, in order to epitaxially grow the single crystal TiN layer, the degree of vacuum before film formation is also an important factor. According to the gas kinetic theory, the unit area (1 cm) in the atmosphere of temperature T ° K and pressure P (torr)²) The number N of molecules having a molecular weight of M colliding every second is
N = 2.89 × 10²²P (MT)^-1/2cm^-2s^-1  ... Formula (1)
It can be expressed as
[0029]
The degree of vacuum before introducing the CVD source gas in the chamber of the single crystal TiN layer deposition apparatus is 0.133 Pa (1 × 10 6^-3In the case of torr), from the equation (1), for example, at room temperature (25 ° C.), oxygen molecules are converted into 1 cm of silicon²3.0 × 10¹⁷Collisions per second.
[0030]
The intermolecular distance is about 0.24 nm (interatomic distance + atomic diameter). Therefore, the unit area (1 cm²) (0.01 / 0.24 × 10 per layer)^-9)²= 1.74 × 10¹⁵Piece / cm²There are oxygen molecules. All of the oxygen molecules that collide with the semiconductor substrate are single crystal CoSi₂Assuming adsorption on the surface of the layer, 1.74 × 10^{1 5}/3.0×10¹⁷= One oxygen molecule layer is formed in about 0.0058 seconds.
[0031]
If 10 layers of TiN are grown in 1 minute, it is necessary to keep the surface of the semiconductor substrate clean during this period. For this purpose, it is necessary to keep the chamber of the film forming apparatus at a vacuum level that does not form one oxygen molecule layer on the surface of the semiconductor substrate for 1 minute or longer. In other words, it is necessary to set the time required for forming one oxygen molecular layer to 1 minute or more. From formula (1), 2.9 × 10 per second¹³Oxygen molecules of 1 piece / second or less are single crystal CoSi₂A degree of vacuum is required to strike the layer. That is, 1.3 × 10^-5A single crystal TiN layer can be formed on a clean semiconductor substrate surface if the degree of vacuum is maintained at Pa or lower.
[0032]
【Example】
Hereinafter, the present invention will be described based on examples with reference to the drawings. In Example 1, a single crystal TiN layer is formed at the bottom of the connection hole by an epitaxial growth method. In Example 2 and Example 3, a single crystal TiN layer is formed in the source / drain region by an epitaxial growth method.
[0033]
Example 1
Example 1 is an example in which the wiring structure and wiring forming method of the present invention are applied to the manufacture of a MOS transistor.
[0034]
As shown in the schematic partial cross-sectional view of FIG. 1, the wiring structure of the first embodiment has a lower conductor region 18 formed on the semiconductor substrate 10 and insulating layers 22 </ b> A and 22 </ b> B covering the lower conductor region 18. The upper wiring layer 32 is formed, and the connection hole 28 that electrically connects the lower conductor region 18 and the upper wiring layer 32 is formed. A single crystal CoSi is formed on the bottom of the connection hole 28 from the semiconductor substrate side.₂The layer 20 and the single crystal TiN layer 26 are formed. Specifically, the lower conductor region 18 is a source / drain region. The semiconductor substrate 10 is made of a silicon semiconductor substrate, and its orientation is (100). In FIG. 1, reference numeral 12 is an element isolation region, reference numeral 14 is a gate electrode, and reference numeral 30 is a barrier layer.
[0035]
A method of forming the wiring structure of the first embodiment shown in FIG. 1 will be described below with reference to FIGS.
[0036]
[Step-100]
First, an element isolation region 12 and a gate electrode 14 are formed on a silicon semiconductor substrate 10 having an orientation (100) based on a conventional method. Next, ion implantation is performed to form an LDD structure. Thereafter, in order to form the gate sidewall 16, the entire surface is made of SiO.₂A film is formed by a CVD method. SiO₂The film formation conditions can be set as follows, for example.
Gas used: SiH₄/ O₂/ N₂= 250/250 / 100sccm
Temperature: 420 ° C
Pressure: 13.3Pa
Film thickness: 0.25 μm
[0037]
Then, for example, SiO under the following conditions₂The entire surface of the film is etched back to form gate sidewalls 16 on the sidewalls of the gate electrode 14.
Gas used: C₄F₈= 50sccm
RF power: 1200W
Pressure: 2Pa
[0038]
Next, impurity ion implantation for forming the source / drain regions is performed under the following conditions, for example, to form the lower conductor region 18 composed of the source / drain regions (see FIG. 2A).
[In the case of N channel formation]
Ion species: As 20 KeV 5 × 10¹⁵/ Cm²
[In the case of P channel formation]
Ion species: BF₂  20 KeV 3 × 10¹⁵/ Cm²
[0039]
[Step-110]
Next, single crystal CoSi is formed on the surface of the lower conductor region 18 composed of the source / drain regions.₂Layer 20 is formed. For this purpose, first, a Ti layer having a thickness of 5 nm is formed on the entire surface by sputtering, for example, under the following conditions.
Process gas: Ar = 100 sccm
Power: 1kW
Deposition temperature: 150 ° C
Pressure: 0.47Pa
[0040]
Further, a Co layer is continuously formed by sputtering, for example, under the following conditions.
Process gas: Ar = 100 sccm
Power: 3kW
Deposition temperature: 150 ° C
Pressure: 0.47Pa
[0041]
Thereafter, single-crystal CoSi is formed from the Co layer by silicidation₂In order to form the layer 20, heat treatment is performed. The heat treatment condition is, for example, 600 ° C. × 60 seconds in an atmosphere of nitrogen gas (1 atm). As a result, Co and Si in the semiconductor substrate react to produce CoSi._XIs formed. Thereafter, unreacted Ti and Co are selectively removed by immersing the entire semiconductor substrate in a mixed solution of hydrochloric acid, hydrogen peroxide solution and pure water for 10 minutes. Thereafter, for example, heat treatment is performed at 850 ° C. for 60 seconds in an atmosphere of nitrogen gas (1 atm) to obtain CoSi._XStable CoSi₂And Thus, CoSi is formed on the surface of the lower conductor region 18 composed of the source / drain regions.₂A layer 20 is formed (see FIG. 2B). CoSi₂When the layer 20 is formed, the surface thereof has TiO_xA natural oxide film (not shown) is formed, and this natural oxide film is removed by a subsequent hydrogen plasma treatment process.
[0042]
[Step-120]
Then, the entire surface is SiO₂An insulating layer 22A made of, for example, is formed by a CVD method using TEOS. The formation conditions of the insulating layer 22A are, for example,
Gas used: TEOS = 50sccm
Pressure: 40Pa
Temperature: 720 ° C
Film thickness: 400nm
It can be. Further, an insulating layer 22B made of BPSG is formed on the insulating layer 22A under the following conditions, for example.
Gas used: SiH₄/ PH₃/ B₂H₆/ O₂/ N₂= 80/7/7/1000 / 32000sccm
Temperature: 400 ° C
Pressure: 1.0 × 105 Pa
Film thickness: 500nm
[0043]
Next, after heat treatment is performed to planarize the surface of the insulating layer, resist patterning is performed on the insulating layers 22A and 22B, and then openings 24 are formed in the insulating layers 22A and 22B by dry etching (see FIG. C)). The dry etching conditions can be set as follows, for example.
Gas used: C₄F₈= 50sccm
RF power: 1200W
Pressure: 2Pa
[0044]
Thereafter, ion implantation is performed to form a junction region. The conditions for ion implantation are exemplified below.
[When N-channel is formed]
Ion species: As 20 KeV 5 × 10¹⁵/ Cm²
[When forming P channel]
Ion species: BF₂  20 KeV 3 × 10¹⁵/ Cm²
Next, activation annealing at 1050 ° C. × 5 seconds is performed.
[0045]
[Step-130]
Next, a single crystal TiN layer 26 is formed at the bottom of the opening 24. For this purpose, first, the substrate subjected to the processes up to [Step-110] is carried into an ECRCVD apparatus. Here, in the ECRCVD apparatus, the degree of vacuum in the atmosphere before epitaxially growing the single crystal TiN layer is 1.3 × 10 6.^-5Use an apparatus with a pressure equal to or lower than Pa. After carrying the substrate into the ECRCVD apparatus, the CoSi exposed at the bottom of the opening 24₂The natural oxide film or the like existing on the surface of the layer 20 is reduced and removed by, for example, hydrogen plasma treatment under the following conditions.
Gas used: H₂/ Ar = 26 / 60sccm
Microwave power: 2.8kW
[0046]
Next, the single crystal TiN layer 26 is formed by ECRCVD. The formation conditions of the single crystal TiN layer 26 can be set as follows, for example. In the first film formation stage, single crystal CoSi is used.₂TiN nuclei are formed on the surface of the layer 20, and single crystal TiN is grown from the nuclei in the second film formation stage. In the first film formation stage, it is desirable to epitaxially grow single crystal TiN at a growth rate of 10 monolayers / minute or less. By providing the first film formation step, the growth rate of the single crystal TiN layer in the second film formation step can be increased.
[Conditions for the first film formation stage]
Gas used: TiCl₄/ H₂/ N₂= 2 / 2.6 / 0.8 sccm
Temperature: 750 ° C
Film thickness: 0.5nm
Pressure: 6.6 × 10^-4Pa
Microwave power: 2.8kW
[Conditions for the second film formation stage]
Gas used: TiCl₄/ H₂/ N₂= 20/26 / 8sccm
Temperature: 750 ° C
Film thickness: 70nm
Pressure: 0.12 Pa
Microwave power: 2.8kW
As a result, an epitaxially grown single crystal TiN layer 26 is formed on the entire surface of the insulating layer 22B including the bottom of the opening 24 (see FIG. 3A). In Example 1, it is desirable that the temperature during film formation in the first film formation stage is 700 to 1250 ° C. Note that, depending on the formation conditions of the single crystal TiN layer, the single crystal TiN layer 26 may not be completely epitaxially grown on the insulating layer 22B, but the object of the present invention can be sufficiently achieved, so that it does not matter.
[0047]
[Step-140]
Thereafter, a metal wiring material is embedded in the opening 24 to form the connection hole 28. In Example 1, tungsten (W) was used as the metal wiring material. That is, for example, tungsten is deposited on the single crystal TiN layer 26 by the CVD method under the following conditions. The thickness of the tungsten layer on the insulating layer 22B was 400 nm.
Gas used: WF₆/ H₂= 95 / 550sccm
Temperature: 450 ° C
Pressure: 1.1 × 104 Pa
[0048]
Next, etch back is performed to remove the tungsten layer and the single crystal TiN layer 26 on the insulating layer 22 </ b> B, leaving the tungsten layer and the single crystal TiN layer 26 only in the opening 24. Thus, the connection hole 28 is completed (see FIG. 3B). The etch back conditions are exemplified below.
Gas used: SF₆= 50sccm
Microwave power: 850W
RF power: 150W
Pressure: 1.33Pa
[0049]
[Step-150]
Thereafter, the barrier layer 30 and the upper wiring layer 32 are formed by sputtering. In Example 1, the barrier layer 30 has a two-layer structure of Ti layer (thickness 30 nm) / TiON layer (thickness 70 nm) from the bottom. The upper wiring layer 32 is made of Al-1% Si (thickness 500 nm). The sputtering conditions for each layer are exemplified below.
[Ti film forming conditions]
Process gas: Ar = 100 sccm
Power: 4kW
Deposition temperature: 150 ° C
Pressure: 0.47Pa
[TiON deposition conditions]
Process gas: Ar / N₂-6% O₂= 40 / 70sccm
Power: 5kW
Pressure: 0.47Pa
[Al-1% Si film formation conditions]
Process gas: Ar = 40 sccm
Power: 22.5kW
Deposition temperature: 150 ° C
Pressure: 0.47Pa
[0050]
Thereafter, resist patterning and dry etching are performed to form the upper wiring layer 32 and the barrier layer 30 in a desired wiring pattern shape. The conditions for dry etching are exemplified below.
Gas used: BCl₃/ Cl₂= 60 / 90sccm
Microwave power: 1000W
RF power: 50W
Pressure: 0.016Pa
[0051]
Thus, the wiring structure shown in FIG. 1 can be formed. On the surface of the lower conductor region 18 composed of the source / drain regions, single crystal CoSi₂The layer 20 is formed, and the lower sheet resistance of the lower conductor region 18 can be reduced. Single crystal CoSi₂On the layer 20, a single crystal TiN layer 26 having excellent barrier properties is formed. When the natural oxide film or the like is removed by hydrogen plasma treatment before forming the single crystal TiN layer 26, the CoSi₂Since the layer 20 is formed, hydrogen atoms can be prevented from entering the silicon crystal. Furthermore, when the single crystal TiN layer 26 is formed, the surface of the silicon semiconductor substrate is not exposed to nitrogen plasma, and the formation of the SiN film can be prevented.
[0052]
(Example 2)
In the first embodiment, the single crystal TiN layer 26 has a single crystal CoSi layer at the bottom of the opening 24.₂In contact with layer 20. On the other hand, in Example 2, the single crystal TiN layer is a single crystal CoSi.₂Over the entire layer is formed. In Example 1, the connection hole 28 was formed by burying tungsten in the opening 24. On the other hand, in Example 2, when the upper wiring layer is formed by sputtering of an aluminum-based wiring material, the opening 24 is filled with the aluminum-based wiring material and the connection hole 28 is formed.
[0053]
[Step-200]
First, an element isolation region 12 and a gate electrode 14 are formed on a silicon semiconductor substrate 10 having an orientation (100) based on a conventional method, followed by formation of an LDD structure, formation of a gate sidewall 16, source / drain The lower conductor region 18 composed of the region is formed. These formation conditions can be the same as those in [Step-100] in Example 1.
[0054]
[Step-210]
Next, single crystal CoSi is formed on the surface of the lower conductor region 18 composed of the source / drain regions.₂Layer 20 is formed. This step may be the same as [Step-110] in the first embodiment.
[0055]
[Step-220]
Then single crystal CoSi₂A single crystal TiN layer 40 is formed on the layer 20. For this purpose, first, the hydrogen plasma treatment described in [Step-130] of Example 1 is performed to obtain single crystal CoSi.₂The natural oxide film formed on the surface of the layer 20 is removed. Next, the single crystal TiN layer 40 is formed into a single crystal CoSi by ECRCVD.₂It is selectively formed only on the layer 20. By making the temperature at the time of film formation lower than [Step-130] of Example 1, the single crystal TiN layer 40 becomes single crystal CoSi.₂It is selectively formed only on the layer 20. It is desirable to further promote TiN single crystallization by applying a substrate bias during film formation. The formation conditions of the single crystal TiN layer 40 can be set as follows, for example. In the first film formation stage, CoSi₂TiN nuclei are formed on the surface of the layer 20, and single crystal TiN is grown from the nuclei in the second film formation stage.
[Conditions for the first film formation stage]
Gas used: TiCl₄/ H₂/ N₂= 2 / 2.6 / 0.8 sccm
Temperature: 300 ° C
Film thickness: 0.5nm
Pressure: 6.6 × 10^-4Pa
Microwave power: 2.8kW
[Conditions for the second film formation stage]
Gas used: TiCl₄/ H₂/ N₂= 20/26 / 8sccm
Temperature: 300 ° C
Film thickness: 70nm
Pressure: 0.12 Pa
Microwave power: 2.8kW
Thus, the epitaxially grown single crystal TiN layer 40 is converted into a single crystal CoSi.₂It is formed on the layer 20 (see FIG. 4A). A polycrystalline TiN layer 40A is formed on the gate electrode 14. Further, the TiN layer is not formed on the element isolation region 12 under the above film formation conditions.
[0056]
[Step-230]
Next, as in [Step-120] of Example 1, after forming insulating layers 22A and 22B on the entire surface, openings 24 are formed in the insulating layers 22A and 22B (see FIG. 4B). Ion implantation is performed to form a junction region, and activation annealing is performed at 1050 ° C. for 5 seconds.
[0057]
[Step-240]
Next, a base layer 42 made of Ti having a thickness of 30 nm is formed on the insulating layer 22B including the opening 24 by sputtering, and subsequently, Al-1% Si is formed on the base layer 42 by high-temperature aluminum sputtering. An upper wiring layer 44 having a thickness of 500 nm is formed. The formation conditions of the underlayer 42 and the upper wiring layer 44 can be set as follows, for example.
[Underlayer formation conditions]
Process gas: Ar = 100 sccm
Power: 4kW
Deposition temperature: 150 ° C
Pressure: 0.47Pa
[Formation conditions for upper wiring layer]
Process gas: Ar = 40 sccm
Power: 22.5kW
Deposition temperature: 500 ° C
Pressure: 0.47Pa
[0058]
Thereafter, similarly to [Step-150] of Example 1, resist patterning and dry etching are performed to form the upper wiring layer 44 and the underlying layer 42 in a desired wiring pattern shape.
[0059]
(Example 3)
The third embodiment is a modification of the second embodiment. In the second embodiment, the single crystal TiN layer 40 is selectively formed as a single crystal CoSi.₂Formed on layer 20. In Example 3, single crystal CoSi₂A TiN layer is formed on the entire surface of the semiconductor substrate including the layer, and then single crystal CoSi₂The other part of the TiN layer is removed, leaving the single crystal TiN layer on the layer and the single crystal TiN layer used as the wiring part.
[0060]
[Step-300]
First, an element isolation region 12 and a gate electrode 14 are formed on a silicon semiconductor substrate 10 having an orientation (100) based on a conventional method, followed by formation of an LDD structure, formation of a gate sidewall 16, source / drain The lower conductor region 18 composed of the region is formed. These formation conditions can be the same as those in [Step-100] in Example 1.
[0061]
[Step-310]
Next, single crystal CoSi is formed on the surface of the lower conductor region 18 composed of the source / drain regions.₂Layer 20 is formed. This step may be the same as [Step-110] in the first embodiment.
[0062]
[Step-320]
Then single crystal CoSi₂A single crystal TiN layer 40 is formed on the layer 20. Single crystal CoSi₂A single crystal TiN layer 40A is also formed in a region other than the layer. For this purpose, first, the hydrogen plasma treatment described in [Step-130] of Example 1 is performed to obtain single crystal CoSi.₂The natural oxide film formed on the surface of the layer 20 is removed. Next, single crystal CoSi is formed by ECRCVD method.₂A single crystal TiN layer 40 is formed on the layer 20, and a single crystal TiN layer 40A is also formed in other regions. Depending on the formation conditions of the single crystal TiN layer, the single crystal TiN layer 40A may not be completely epitaxially grown on another region (for example, the element isolation region 12), but the object of the present invention can be sufficiently achieved. So there is no problem.
[0063]
By making the temperature at the time of film formation higher than [Step-220] of Example 2, the single crystal TiN layer 40 becomes single crystal CoSi.₂The single crystal TiN layer 40A is formed on the layer 20 and also in other regions. It is desirable to further promote TiN single crystallization by applying a substrate bias during film formation. The formation conditions of the TiN layers 40 and 40A can be set as follows, for example. In the first film formation stage, CoSi₂TiN nuclei are formed on the surface of the layer 20 and the like, and a single crystal TiN layer is grown from the nuclei in the second film formation stage.
[Conditions for the first film formation stage]
Gas used: TiCl₄/ H₂/ N₂= 2 / 2.6 / 0.8 sccm
Temperature: 750 ° C
Film thickness: 0.5nm
Pressure: 6.6 × 10^-4Pa
Microwave power: 2.8kW
Substrate RF bias: -50W
[Conditions for the second film formation stage]
Gas used: TiCl₄/ H₂/ N₂= 20/26 / 8sccm
Temperature: 750 ° C
Film thickness: 70nm
Pressure: 0.12 Pa
Microwave power: 2.8kW
Substrate RF bias: -50W
As a result, the epitaxially grown single crystal TiN layer 40 is converted into a single crystal CoSi.₂A single crystal TiN layer 40A is formed on the layer 20 and in other regions.
[0064]
[Step-330]
Thereafter, unnecessary single crystal TiN layer 40A is removed by dry etching after resist patterning, leaving single crystal TiN layer 40A necessary as a wiring portion. The dry etching conditions can be set as follows, for example.
Gas used: BCl₃/ Cl₂= 60 / 90sccm
Power: 50W
Pressure: 2Pa
[0065]
[Step-340]
Next, as in [Step-120] of Example 1, after forming insulating layers 22A and 22B on the entire surface, openings 24 are formed in insulating layers 22A and 22B, and ion implantation is performed to form a junction region. Then, activation annealing at 1050 ° C. × 5 seconds is performed.
[0066]
[Step-350]
Next, as in [Step-240] of Example 2, a 30 nm-thick underlayer 42 made of Ti is formed on the insulating layer 22B including the opening 24 by sputtering, followed by high-temperature aluminum sputtering. Then, an upper wiring layer 44 made of Al-1% Si and having a thickness of 500 nm is formed on the base layer 42. Thereafter, similarly to [Step-150] of Example 1, resist patterning and dry etching are performed to form the upper wiring layer 44 and the underlying layer 42 in a desired wiring pattern shape. In this way, a wiring structure having a schematic partial cross-sectional view shown in FIG. 5 can be formed.
[0067]
As mentioned above, although this invention was demonstrated based on the preferable Example, this invention is not limited to these Examples. Various conditions and numerical values described in the embodiments are examples and can be changed as appropriate.
[0068]
The insulating layers 22A and 22B are made of SiO.₂In addition to the combination of BPSG and BPSG, a known insulating material such as PSG, BSG, AsSG, PbSG, SbSG, or SiN, or a combination of these insulating materials can be used. Examples of the aluminum-based wiring material include pure Al or Al alloys such as Al-Si-Cu, Al-Cu, and Al-Ge, in addition to Al-1% Si.
[0069]
The connection hole forming method in the first embodiment can be replaced with the connection hole forming method described in the second embodiment. That is, in Example 1, after the single crystal TiN layer 26 is formed, the upper wiring layer 32 made of Al-1% Si and having a thickness of 500 nm is formed on the single crystal TiN layer 26 by high temperature aluminum sputtering. The upper wiring layer and the connection hole can be formed.
[0070]
Various layers can be formed by sputtering using various sputtering apparatuses such as a magnetron sputtering apparatus, a DC sputtering apparatus, an RF sputtering apparatus, an ECR sputtering apparatus, and a bias sputtering apparatus that applies a substrate bias. In addition to the ECRCVD apparatus, a CVD apparatus provided with a plasma generation source such as a thermal CVD apparatus, a plasma CVD apparatus, a helicon wave, or ICP (Inductively Coupled Plasma) can be used as the CVD apparatus. In addition to hydrogen plasma treatment, Ar sputter etching with reduced ion bias, such as IPC soft etching, can be employed for removing the natural oxide film.
[0071]
The wiring structure and the method for forming the wiring structure described in the first and second embodiments can be combined. That is, single crystal CoSi₂The single crystal TiN layer 40 may be formed on the surface of the layer 20, and the single crystal TiN layer 26 may also be formed at the bottom of the opening.
[0072]
The wiring structure of the present invention can also be applied to devices other than MOS transistors, such as bipolar transistors and CCDs.
[0073]
【The invention's effect】
In the present invention, single crystal CoSi is formed at the bottom of the opening.₂Since the layer is formed, the sheet resistance of the lower conductor region can be reduced, and the reaction between the lower conductor region and the wiring material in the connection hole can be prevented by the single crystal TiN layer. Further, since the single crystal TiN layer is formed at the bottom of the connection hole, the barrier property is remarkably improved.
[0074]
Moreover, since the natural oxide film and the like are removed and the single crystal TiN layer is subsequently formed, the single crystal CoSi₂The interface between the layer and the single crystal TiN layer is kept clean at the atomic level. Therefore, an ideal ohmic junction is obtained, and the contact resistance can be reduced.
[0075]
Furthermore, the surface of the semiconductor substrate is single crystal CoSi.₂Since the silicon surface is not exposed because it is covered with a layer, it is possible to suppress the occurrence of crystal defects in the semiconductor substrate even if a hydrogen plasma treatment is performed as a pretreatment before the formation of the single crystal TiN layer. Further, formation of the SiN film by nitrogen plasma can also be prevented.
[0076]
Further, conventionally, a polycrystalline TiN layer is patterned to form a wiring part. However, in the wiring structure of Example 3, the single crystal TiN layer 40A is used as the wiring part, so that the wiring resistance is reduced. be able to.
[Brief description of the drawings]
1 is a schematic partial cross-sectional view of a semiconductor device showing a wiring structure of Example 1. FIG.
FIG. 2 is a schematic partial cross-sectional view of a semiconductor element for explaining each step of the wiring forming method according to the first embodiment.
FIG. 3 is a schematic partial cross-sectional view of a semiconductor device for explaining each step of the wiring forming method of Example 1 following FIG. 2;
4 is a schematic partial cross-sectional view of a semiconductor element for explaining each step of a wiring forming method of Example 2. FIG.
5 is a schematic partial cross-sectional view of a semiconductor device showing a wiring structure of Example 1. FIG.
FIG. 6 is a schematic partial cross-sectional view of a semiconductor element for explaining each step of a conventional wiring forming method.
FIG. 7 is a schematic partial cross-sectional view of a semiconductor element for explaining each step of a conventional wiring forming method, following FIG. 6;
[Explanation of symbols]
10 Semiconductor substrate
12 Device isolation region
14 Gate electrode
16 Gate sidewall
18 Lower conductor area
20 Single crystal CoSi₂layer
22A, 22B Insulation layer
24 opening
26,40 single crystal TiN layer
28 Connection hole
30 Barrier layer
32, 44 Upper wiring layer
40A Wiring part consisting of single crystal TiN layer
42 Underlayer

Claims (4)

A lower conductor region formed on a semiconductor substrate, an upper wiring layer formed on an insulating layer covering the lower conductor region, and a connection hole for electrically connecting the lower conductor region and the upper wiring layer A wiring structure in a semiconductor device,
At the bottom of the connection hole, a single crystal CoSi ₂ layer and a single crystal TiN layer are formed from the semiconductor substrate side,
A wiring structure in a semiconductor device, characterized in that a TiN wiring portion extending from a single crystal TiN layer formed at the bottom of the connection hole and further comprising at least a part of single crystal TiN is further formed on a semiconductor substrate. . 2. The wiring structure in a semiconductor device according to claim 1, wherein the semiconductor substrate is a silicon semiconductor substrate. The wiring structure in a semiconductor device according to claim 2, wherein the orientation of the silicon semiconductor substrate is (100). A source / drain region formed in a semiconductor substrate, an upper wiring layer formed on an insulating layer covering the source / drain region, and a connection hole for electrically connecting the source / drain region and the upper wiring layer A MOS transistor having a wiring structure consisting of:
A single crystal CoSi ₂ layer and a single crystal TiN layer are formed at the bottom of the connection hole from the semiconductor substrate side,
A MOS transistor characterized in that a TiN wiring portion is further formed on a semiconductor substrate that extends from a single crystal TiN layer formed at the bottom of the connection hole and at least part of which is made of single crystal TiN .

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