JPH05144951A - Wiring formation method - Google Patents

Abstract

PURPOSE:To form a flat plug part when etching back a W layer (Blk-W layer) which is laminated on an adhesive layer by CVD method. CONSTITUTION:After a nitride layer 18 is formed on a surface of an SiO2 layer insulating film 17 by carrying out lamp annealing in NH3 atmosphere in a manufacturing process of a MOS-FET, contact holes 19, 20 are opened and an adhesive layer 23 is formed of a Ti layer 21 and a TiNX layer 22. When forming a following Blk-W layer (not illustrated in the figures), a wafer is heated at a high temperature; however, the nitride layer 18 blocks oxygen from the SiO2 layer insulating film 17 and prevents oxidation of a Ti layer 21. Since residue of Ti oxide does not remain when the adhesive layer 23 is etched back and an over etching time is reduced, it is possible to prevent erosion of the adhesive layer 23 inside the contact holes 19, 20 due to loading effect.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring forming method applied in the field of manufacturing semiconductor devices, and more particularly, to a wiring material layer deposited on an insulating film in a substantially flat manner via an adhesion layer for connection by etching back. The present invention relates to a method of preventing the generation of a residue resulting from the oxidation of an adhesion layer when forming a plug portion inside a hole and preventing the corrosion of the plug portion due to excessive overetching.

[0002]

2. Description of the Related Art As the integration and performance of semiconductor devices have increased as seen in VLSI, ULSI and the like in recent years, the proportion of the wiring portion on the device chip tends to increase. Multilayer wiring is now an indispensable technology in order to prevent a large increase in chip area. Conventionally, as a wiring forming method, forming an aluminum-based metal material layer by a sputtering method has been widely performed. However, in the situation where the multilayered wiring progresses as described above, and as a result, the surface step of the substrate and the aspect ratio of the connection hole increase, due to the lack of step coverage in the sputtering method, Poor connection between the upper layer wiring and the semiconductor substrate and connection failure between wirings have already become serious problems.

As a method for improving step coverage, a so-called metal plug technique has recently been proposed in which the inside of the connection hole is filled with a wiring material layer to form a plug portion. In this metal plug technology, as the aspect ratio of the connection hole increases, the resistance of the plug portion itself increases, which causes a problem of heat generation when a large current flows. Therefore, a low-resistance high-melting-point metal is used as the wiring material.

As a method of forming the plug portion, selective CVD
Method and blanket CVD method are known. Selective CVD
The method is a method of selectively depositing a metal only inside the connection hole while reducing a gas such as a metal fluoride or an organometallic compound by the lower layer wiring material. However, although quite good results have been obtained at the research level, there are drawbacks such as gradually decreasing selectivity or poor controllability when etching back an overgrowth portion commonly called a nail head, Contrary to the initial expectations, the current situation is that there is no prospect of introduction to mass production.

On the other hand, the blanket CVD method is a method in which a metal or an alloy is deposited on the entire surface of the substrate to flatten the substrate. Of course, an etch-back step is required to form the plug portion, but this is the method of interest because of the stability of the process and the relative ease with which connection holes of different depths can be filled. .. The most widely used material as the refractory metal forming the plug portion is tungsten (W). Therefore, W will be described as an example in the following specification. Also, blanket C
The W layer formed by the VD method will be abbreviated as Blk-W layer.

By the way, although the Blk-W layer is excellent in step coverage, there is a problem that it is inferior in adhesion to the underlying interlayer insulating film due to the difference in internal stress at the interface between different material layers. For example, the Journal of the Electrochemical Society (Jour
nal of the Electrochemica
l Society) Vol. 121, No. 2, 298-303
The page points out that the Blk-W layer formed on the silicon oxide interlayer insulating film by the CVD method has insufficient adhesion.

When forming a Blk-W layer,
It is necessary to prevent erosion of the substrate by WF ₆ of the source gas. Further, since the substrate is heated during the film formation, it is necessary to improve the barrier property for the lower layer wiring.

In order to solve these problems, it is effective to provide a TiN layer, a TiW layer, etc. as an adhesion layer which also serves as a barrier metal, prior to the formation of the wiring material layer. However, if these layers are directly formed on the lower layer wiring such as the impurity diffusion region, the contact resistance increases. Therefore, in practice, a salicide method (SALICIDE: self-aligned) in which a Ti layer having excellent ohmic properties is interposed as a base of the adhesion layer or the surface of the impurity diffusion region is silicidized in a self-aligned manner.
The application of silicide) is performed.
However, the latter side method has a problem in the selectivity of the formation region of the silicide film, and at present, the method of interposing the Ti layer is generally used.

[0009]

By the way, when the Blk-W layer is formed through the adhesion layer containing the Ti layer, in order to selectively form the plug portion inside the connection hole, the Blk-W layer is formed.
-It is necessary to sequentially etch back the W layer and the adhesion layer.
However, it is not always easy to control the etching so that the substrate is flattened after the etching back is completed,
It was often observed that the adhesion layer was greatly infiltrated along the side wall surface of the connection hole. This phenomenon will be described with reference to FIG.

Now, as shown in FIG. 9A, a contact hole 35 is opened in the SiO ₂ interlayer insulating film 34 on the silicon substrate 31 so as to face the impurity diffusion region 32.
Consider a case where the surface of the wafer is covered with an adhesion layer 38 formed by sequentially stacking a Ti layer 36 and a TiN layer 37. A TiSi _x (titanium silicide) layer 33 is formed in the surface layer portion of the impurity diffusion region 32 for the purpose of reducing sheet resistance and improving barrier properties.

Next, as shown in FIG. 9B, the Blk-W layer 3 is formed on the entire surface of the wafer by a blanket CVD method.
9 is deposited. When depositing the Blk-W layer 39,
The wafer is usually heated to 400 to 500 ° C., but this heating oxidizes a part of the Ti layer 36 to generate TiO _x (titanium oxide) 36 a. Oxygen in this oxidation reaction is supplied from the SiO ₂ interlayer insulating film 34. That is,
Since towards free energy of TiO _x than free energy of SiO ₂ is small, it is the Ti will pull out the oxygen of the SiO ₂ interlayer insulating film 34.

Next, the Blk-W layer 39 is etched back to finish when the surface of the adhesion layer 38 is exposed.
Furthermore, the etching conditions are switched to etch back the adhesion layer 38. The etching back of the adhesion layer 38 should normally be completed when the surface of the SiO ₂ interlayer insulating film 34 is exposed. However, it is difficult to etch TiO _x 3
Since 6a is attached, it is unavoidable to perform overetching more than normally required to remove it. As a result, the etching species are concentrated on the slightly exposed surface of the adhesion layer 38 inside the contact hole 35 due to the loading effect, and as shown in FIG.
The contact portion 40 is formed around the W plug 39a. The TiO _x 36a not only becomes an etching residue but also causes particle contamination. Further, the contact portion 40 deteriorates the flatness of the contact portion and adversely affects the step coverage and the electrical connection when forming the upper layer wiring with an Al-based material or the like.

Therefore, the present invention provides a wiring forming method capable of flatly filling a connection hole with a plug portion when etching back a wiring material layer deposited on an insulating film via an adhesion layer. With the goal.

[0014]

The wiring forming method of the present invention is proposed to achieve the above object. That is, in the wiring forming method according to the first invention of the present application, after the wiring material layer is deposited on the insulating film in which the connection hole is opened through the adhesion layer to substantially flatten the substrate, the wiring material layer and the wiring material layer are formed. A method of sequentially etching back the adhesion layer to form a plug portion inside the connection hole, which comprises forming an antioxidation layer for preventing oxidation of the adhesion layer on at least the upper surface of the insulating film. Characterize.

The wiring forming method according to the second invention of the present application is characterized in that the oxidation preventing layer is formed by depositing silicon nitride by a plasma CVD method.

Further, the wiring forming method according to the third invention of the present application is characterized in that the oxidation preventing layer is formed by surface nitriding treatment of the insulating film.

[0017]

According to the present invention, an oxidation preventing layer is formed on at least the upper surface of the insulating film so that the adhesion layer is not oxidized by the oxygen supply from the insulating film even when the wafer is heated to a high temperature during the formation of the wiring material layer. The point is to do. This antioxidant layer may be formed at an appropriate stage before the adhesion layer is formed. Thereby, even if the adhesion layer includes a material layer such as a Ti layer that is easily oxidized, a metal oxide that is difficult to be etched is not generated. Therefore, excessive over-etching is unnecessary, and it is possible to prevent the plug portion from touching inside the connection hole.

By the way, when etching back the wiring material layer, the only problem as an etching residue is the metal oxide formed on the upper surface of the insulating film. Therefore, in the present invention, the adhesion layer is oxidized on the upper surface. It is sufficient if the above is prevented. So in a practical process,
After forming the antioxidant layer on the insulating film, the connection hole is opened.

However, from the viewpoint of preventing the reaction between the adhesion layer and the antioxidant layer, the antioxidant layer may, of course, be interposed in all the regions where they are in contact with each other. In this case, it is sufficient to form the oxidation prevention layer on the entire surface of the base after opening the connection hole in the insulating film, and depending on the material of the oxidation prevention layer, there is a secondary merit that the barrier property is improved at the bottom surface of the connection hole. Obtainable. However, since the side wall surface of the connection hole is also covered with the antioxidant layer, the opening diameter of the contact hole is reduced depending on the method of forming the antioxidant layer.

The above is the basic idea of the three inventions of the present application. The second invention of the present application proposes formation of a silicon nitride (SiN _x ) layer by a plasma CVD method as a practical method of forming the above-mentioned oxidation preventing layer. Here, the reason why the plasma CVD method is applied is to reduce the internal stress of the formed antioxidant layer. Another known method for forming the SiN _x layer is the low pressure CVD method. However, the SiN _x layer formed by this method has a large internal stress and should be formed to have a sufficient thickness to fulfill the function of preventing oxidation. In that case, the wafer may be cracked or the antioxidant layer may be peeled off.

In the third invention of the present application, the oxidation preventing layer is formed by surface nitriding treatment of the insulating film. The composition of the antioxidant layer in this case is, for example, if the insulating film is SiO ₂ , and if this is treated in an NH ₃ atmosphere, SiN _x and S are added.
The composition is a mixture of iO _x N _y . According to the third invention, since the surface layer portion of the existing insulating film is modified, the thickness of the insulating film hardly increases and there is no concern that the aspect ratio of the connection hole increases.

By the way, as a technique similar to the present invention,
A technique of forming a SiN _x layer on an insulating film by a plasma CVD method is 1989 VMIC Conference.
Abstracts p. 129-135. In this case, the SiN _x layer suppresses the loading effect when etching back the Blk-W layer formed on the adhesion layer formed by sequentially stacking the Ti layer and the TiW layer, and the surface of the Blk-W layer. It is provided as a kind of buffer layer for preventing the unevenness from being transferred to the insulating film. This is because the etching rates of the Blk-W layer and the SiN _x layer due to F ^* (fluorine radical) are almost equal. However, in order to effectively use the SiN _x layer as a buffer layer, a film thickness of 0.3 μm is necessary.

On the other hand, the SiN _x layer in the present invention is for preventing the adhesion layer from being oxidized, and for this purpose, several hundred Å
It is sufficient that the film has a certain thickness. Therefore, there is no concern that the aspect ratio of the connection hole will significantly increase.

[0024]

EXAMPLES Specific examples of the present invention will be described below. Example 1 In this example, the first invention of the present application is applied, and after a SiN _x layer is formed as an antioxidant layer on the SiO ₂ interlayer insulating film by a plasma CVD method, a Ti / TiN _x system two-layer structure is formed. In this example, the Blk-W layer is formed via the adhesion layer and the plug portion is formed by etchback. This process is illustrated in Figure 1.
It will be described with reference to FIGS.

First, as shown in FIG. 1, an SiO ₂ interlayer insulating film 4 of about 0.6 is formed by a CVD method or the like on a silicon substrate 1 on which an impurity diffusion region 2 is formed as a lower layer wiring.
It was formed to a thickness of μm. Here, the impurity diffusion region 2
A TiSi _x layer 3 is formed on the surface layer of the above in order to reduce the sheet resistance and improve the barrier property. This Ti
The method for forming the Si _x layer 3 is the same as the conventional general SALICI.
The DE method may be used, but the applicant of the present application first discloses the method disclosed in Japanese Patent Laid-Open No. 260-260.
It is more preferable to adopt the method proposed in Japanese Patent No. 630. This is done by first removing the native oxide film on the silicon substrate, then forming a new thin SiO ₂ layer, and
This is a method of silicidation by stacking i layers and then performing heat treatment in an inert gas atmosphere. Regarding this process, the Applicant has adopted SITOX (= silici)
The term “dation through oxide” method is proposed. The TiSi _x layer 3 formed by the SITO X method has higher selectivity in the formation region than the TiSi _x layer formed by the conventional SALICIDE method, the film quality is extremely dense and uniform, the barrier property is excellent, and the sheet resistance is high even after high temperature annealing. It has many features that keep it low.

Then, the above-mentioned Si is formed by the plasma CVD method.
A SiN _x layer 5 was formed on the O ₂ interlayer insulating film 4 as an antioxidant layer to a thickness of about 0.05 μm. This film formation was performed according to normal conditions using SiN ₄ and NH ₃ as source gases.

Next, a resist mask (not shown) is formed according to a normal process, and the SiN _x layer 5 and the SiO ₂ interlayer insulating film 4 are dry-etched using the resist mask as a mask. As shown in the drawing, a contact hole 6 having an opening diameter of about 0.6 μm was opened facing the impurity diffusion region 2. A parallel plate type RIE (reactive ion etching) apparatus is used for this etching, and the conditions are, for example, CHF ₃ flow rate 80 SCCM, gas pressure 6.7 Pa (50 mTorr), RF power density 0.
It was set to 25 W / cm ² (13.56 MHz).

Next, as shown in FIG. 3, a Ti layer 7 and a TiN _x layer 8 were sequentially formed on the entire surface of the wafer to form an adhesion layer 9. Here, in order to form the Ti layer 7 and the TiN _x layer 8, a single-wafer sputtering apparatus is used.
By sequentially changing the composition of the gas supplied into the sputtering chamber equipped with the target, film formation was performed in a continuous process without exposing the wafer to the atmosphere.

First, as a pretreatment, microwave plasma cleaning / attachment attached to the above-mentioned single-wafer sputtering apparatus.
In the chamber, the native oxide film (not shown) covering the bottom of the contact hole 4 was removed. Subsequently, the wafer is transferred to a sputtering chamber under high vacuum, and as an example, the Ar flow rate is 100 SCCM and the gas pressure is 1.3 P.
a, a Ti target 7 was sputtered under the conditions of a wafer temperature of 150 ° C. and a target power of 4 kW to form a Ti layer 7 having a thickness of about 0.03 μm.

Next, as an example of conditions, Ar flow rate 40 SC
CM, N ₂ flow rate 70 SCCM, gas pressure 1.3 Pa, wafer temperature 150 ° C., target current 5 kW were switched to form a TiN _x layer 8 having a thickness of about 0.07 μm.

Next, as shown in FIG. 4, a Blk-W layer 10 was deposited on the entire surface of the wafer by a blanket CVD method. Here, the blanket CVD method uses SiH.
_It was carried out in a two-step process of nuclear growth by reducing ₄ (first step) and high-speed growth by reducing H ₂ (second step). The conditions of the first stage are, for example, WF ₆ flow rate 25 SCCM, SiH ₄
Flow rate 10 SCCM, gas pressure 10640 Pa (80 Tor
r), the wafer temperature is 475 ° C., and the second stage condition is, for example, WF ₆ flow rate 60SCCM, H ₂ flow rate 360SC.
CM, gas pressure 10640 Pa (80 Torr), and wafer temperature 475 ° C.

At this time, since the wafer is heated to a high temperature, a part of the Ti layer 7 on the side wall surface of the contact hole 6 is oxidized by the oxygen supply from the SiO ₂ interlayer insulating film 4, and TiO _x 7a is generated. Been formed. However, SiO
₂ SiN _x is formed on the upper surface of the interlayer insulating film 4 as an antioxidant layer.
Since the layer 5 was interposed, the Ti layer 7 was not oxidized.

Next, the Blk-W layer 10 was etched back to form a W plug 10a as shown in FIG. For this etch back, a parallel plate type plasma RIE apparatus is used. As an example, SF ₆ flow rate 30 SCCM, gas pressure 6.7 Pa (50 mTorr), RF power density 0.0
It was set to 8 W / cm ² (13.56 MHz). in this case,
Considering the flattening of the entire plug part, the W plug 1
It is desirable to finish the etch back at the time when the surface of 0a becomes almost the same height as the surface of the SiN _x layer 5.

Next, the adhesion layer 9 was etched back. The condition at this time is, as an example, a Cl ₂ flow rate of 30 SCCM, A
r Flow rate 20 SCCM, gas pressure 2 Pa (15 mTorr
r), RF power density 0.23 W / cm ² (13.56)
MHz). In this process, the SiO ₂ interlayer insulating film 4
Since no TiO _x is formed on the upper surface of the contact hole, over-etching is minimized and the contact hole 4
The adhesion layer 9 was not infiltrated inside the.
As a result, as shown in FIG. 6, the inside of the contact hole 6 could be buried almost flat with the plug portion P _{1 including the} Ti layer 7, the TiN _x layer 8 and the W plug 10a.

After that, an Al-1% Si layer or the like may be formed on the entire surface of the wafer according to a usual process, and the upper wiring may be completed by patterning.

Example 2 In this example, the second invention of the present application is applied, and after nitriding the surface of the SiO ₂ interlayer insulating film in an NH ₃ atmosphere, Ti / T
In this example, a Blk-W layer is formed via an iN _x- based two-layer structure adhesive layer and a plug portion is formed by etchback.
This process will be described with reference to FIG.

FIG. 7A shows a MOS having an LDD structure.
-Shows an intermediate state of the FET manufacturing process. That is, a gate electrode 14 made of a polycrystalline silicon layer is formed on a silicon substrate 11 in an element formation region defined by an element isolation region 12 via a gate oxide film 13, and a sidewall of the gate electrode 14 has a side wall. Wall 15
Are formed. The surface layer portion of the silicon substrate 11 is self-aligned with the source / source by two-step ion implantation using the gate electrode 14 and the sidewall 15 as a mask.
The drain region 16 is formed. The entire surface of the substrate is covered with a SiO ₂ interlayer insulating film 17 having a thickness of about 0.8 μm.

The above-mentioned wafer was subjected to lamp annealing in a 100% NH ₃ atmosphere at 1000 ° C. for 60 seconds to form a nitride layer 18 on the surface of the SiO ₂ interlayer insulating film 17. A typical reaction of this surface nitriding treatment is:
There are two possibilities. _{3SiO 2 + 4NH 3 → Si 3} N 4 + 6H 2 O 2SiO 2 + 2NH 3 → Si 2 ON 2 + 3H 2 O ie, H generated by the thermal decomposition of NH ₃ is SiO ₂
Silicon nitride or silicon oxynitride is generated by reducing the interlayer insulating film and bonding N to the broken Si bond (dangling bond) generated by the reduction.

Next, by patterning using a resist mask (not shown), an opening diameter of about 0.4 μm is formed in the SiO ₂ interlayer insulating film 17 as shown in FIG. 7B.
The contact holes 19 and 20 were opened. The etching conditions for the SiO ₂ interlayer insulating film 17 at this time are as described in the first embodiment. The nitride layer 18 and the SiO ₂ interlayer insulating film 17 can be etched at the same etching rate.

Furthermore, a layer thickness of about 0.03 μm is formed on the entire surface of the wafer.
m Ti layer 21 and a TiN _x layer 2 having a layer thickness of about 0.07 μm.
2 were sequentially laminated to form an adhesion layer 23. The film forming conditions for each layer at this time are also as described in Example 1.

Next, a Blk-W layer (not shown) was formed on the entire surface by a blanket CVD method. As an example of the blanket CVD method, the WF ₆ flow rate is 550 SCC.
M, H ₂ flow rate 6800SCCM, gas pressure 3990Pa
(30 Torr) and the wafer temperature was 400 ° C. At this time, the contact hole 19,
Part of the Ti layer is oxidized on the side wall surface of 20,
Although the TiO _x 21a as shown in (c) was formed, the oxidation reaction did not proceed because the nitride layer 18 exists on the upper surface of the SiO ₂ interlayer insulating film 17.

Next, the Blk-W layer was etched back. The condition at this time is, for example, SF ₆ flow rate 25
0 SCCM, O ₂ flow rate 50 SCCM, gas pressure 18 Pa
(135 mTorr), RF power density 2 W / cm
² (13.56 MHz). As a result, FIG.
The W plug 24 was formed as shown in FIG. Further, the adhesion layer 23 was etched back. The conditions at this time are, for example, a Cl ₂ flow rate of 50 SCCM and an Ar flow rate of 25.
SCCM, gas pressure 20Pa (150mTorr), RF
The power density was 2 W / cm ² (13.56 MHz).
As a result, the insides of the contact holes 19 and 20 are
The plug portion P ₂ composed of the Ti layer 21, the TiN _x layer 22, and the W plug 24 was buried substantially flat.

Example 3 This example is another example to which the second invention of the present application is applied, and the method of forming the adhesion layer is slightly changed from that of Example 2. This process will be described with reference to FIG. Reference numerals in FIG. 8 are partially common to those in FIG. 7. FIG. 8A shows an LDD.
In the process of manufacturing a MOS-FET having a structure, contact holes 19 and 20 are opened in the SiO ₂ interlayer insulating film 17 having a nitride layer 18 formed on the surface thereof, and a Ti layer having a thickness of about 0.03 μm is formed on the entire surface of the wafer. 25 shows a state in which 25 is formed. However, the Ti layer 25 may be slightly thicker than the Ti layer 21 in the second embodiment.

Next, 100% NH _{3 is} added to the above wafer.
RTA (rapid
Thermal annealing) processing was performed. This RTA processing,
That is, by the surface nitriding treatment, as shown in FIG.
The production of TiSi _x by the reaction with Ti and the production of TiN _x by the surface nitriding of the Ti layer 25 proceed at the same time.
The i _x / TiN _x layer 25b was formed. This TiSi _x
The / TiN _x layer 25b serves to reduce the sheet resistance and improve the barrier property. On the other hand, SiO ₂ interlayer insulating film 1
On the upper surface of No. 7 and the side wall surfaces of the contact holes 19 and 20, only the surface nitriding of the Ti layer 25 proceeded to form the TiN _x layer 25a. This TiN _x layer 25a
Were formed very uniformly. This is because the nitride layer 18 formed on the upper surface of the SiO ₂ interlayer insulating film 17 causes Ti
This is because the layer 25 is prevented from being oxidized.

Next, a Blk-W layer (not shown) was formed, and the Blk-W layer and the TiN _x layer 25a were sequentially etched back. Finally, as shown in FIG. 8 (c),
The contact holes 19 and 20 were buried substantially flat by the plug portion P _{3 including the} TiN _x layer 25a and the W plug 24.

Although the present invention has been described based on the three embodiments, the present invention is not limited to these embodiments. For example, in Example 1, the SiN _x layer was formed by the plasma CVD method as the anti-oxidation layer.
iN _x layer may also be further laminated. In this case, since the SiN _x layer having a low internal stress by the plasma CVD method serves as a base, SiN _{x having} a high internal stress by the low pressure CVD method is used.
Even if the layers are stacked, there is no inconvenience such as cracking of the wafer and peeling of the antioxidant layer.

When the surface layer portion of the impurity diffusion region is previously silicidized, it is effective to open the contact hole in the SiO ₂ interlayer insulating film and then perform surface nitriding treatment. In this case, the upper surface, the side wall surface and the surface of the silicide layer of the SiO ₂ interlayer insulating film are nitrided, and the barrier property of the surface of the silicide layer is particularly increased.

[0048]

As is apparent from the above description, in the wiring forming method of the present invention, an extremely simple technique of forming an antioxidant layer on an insulating film prior to forming an adhesion layer can be performed.
It is possible to prevent the generation of a residue at the time of etch back and the contact of the adhesion layer in the connection hole. Therefore, the base can be satisfactorily flattened by the metal plug, and reliable connection with the upper layer wiring can be achieved in a later step.

The present invention is extremely useful for manufacturing a semiconductor device designed according to a fine design rule and having a high degree of integration and high performance.

[Brief description of drawings]

FIG. 1 shows an example of application of the first invention of the present application in which SiO _{2 is used.}
It is a schematic sectional view showing a state in which SiN _x layer is formed by plasma CVD on the interlayer insulating film.

FIG. 2 is a schematic cross-sectional view showing a state in which a contact hole is opened by patterning the SiN _x layer and the SiO ₂ interlayer insulating film of FIG.

3 is a schematic cross-sectional view showing a state in which an adhesion layer composed of a Ti layer and a TiN _x layer is formed on the entire surface of the wafer of FIG.

4 is a schematic cross-sectional view showing a state in which a Blk-W layer is formed on the entire surface of the wafer in FIG. 3 by a blanket CVD method.

5 is a schematic cross-sectional view showing a state where the Blk-W layer of FIG. 4 is etched back.

FIG. 6 is a schematic cross-sectional view showing a state in which the contact layer of FIG. 5 is etched back and the contact holes are flatly filled in the plug portions.

FIG. 7 shows a second invention of the present application, a MOS having an LDD structure
FIG. 6 is a schematic cross-sectional view showing an example of a process applied to contact formation in a FET in the order of steps thereof;
(A) is a state in which a nitride layer is formed by surface nitriding treatment of the SiO ₂ interlayer insulating film, (b) is a state in which a contact hole is opened in the SiO ₂ interlayer insulating film and an adhesion layer is formed, (c) Form a Blk-W layer, and then form the Blk-W
The layers and the adhesion layer are etched back to show the state where the contact holes are flatly filled in the plug portions.

FIG. 8 shows a second invention of the present application, a MOS having an LDD structure.
FIG. 6 is a schematic cross-sectional view showing another example of the process applied to the contact formation in the FET in the order of the steps,
(A) is SiO ₂ having a nitride layer formed by surface nitriding treatment.
In the state where the contact hole is opened in the interlayer insulating film and the Ti layer is formed on the entire surface of the wafer, (b) shows that the Ti layer is changed into the TiN _x layer and the TiSi _x / TiN _x layer by the RTA treatment in the NH ₃ atmosphere. State, (c) is Bl
After forming the k-W layer, the Blk-W layer and the adhesion layer are etched back to show the state in which the contact hole is flatly filled with the plug portion.

FIG. 9 is a schematic cross-sectional view for explaining a problem in a conventional process, FIG. 9A shows a Ti layer and a TiN layer formed by covering a contact hole opened in a SiO ₂ interlayer insulating film.
_The state where the adhesion layer composed of _x layers is formed, (b) is Blk
In the state where the Ti layer is oxidized to form TiO _x during the formation of the -W layer, (c) shows a residue of TiO _x generated during the etchback of the Blk-W layer and the adhesion layer, and the adhesion layer is formed in the contact hole. Represents the touched state.

[Explanation of symbols]

1, 11 ・ ・ ・ Silicon substrate 2, 12 ・ ・ ・ Impurity diffusion region 3 ・ ・ ・ TiSi _x layer 4, 17 ・ ・ ・ SiO ₂ interlayer insulating film 5 ・ ・ ・ SiN _x layer (antioxidation layer) 6, 19 , 20 ... contact hole 7,21,25 ... Ti layer _{7a, 21a ··· TiO x 8,22,25a ···} TiN x layer 9,23 ... adhesion layer 10 ... Blk -W layer 10a, 24 ... W plugs 14 ... gate electrode 16 ... drain region 18 ... nitride layer 25b ··· TiSi _x / TiN _x layer

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location // H01L 21/318 B 8518-4M

Claims (3)

[Claims] 1. A wiring material layer is deposited on an insulating film in which a connection hole is opened via an adhesion layer to substantially flatten a substrate, and then the wiring material layer and the adhesion layer are sequentially etched back to perform the connection. A wiring forming method for forming a plug portion inside a hole, wherein an oxidation preventing layer for preventing oxidation of the adhesion layer is formed on at least an upper surface of the insulating film. 2. The wiring forming method according to claim 1, wherein the oxidation preventing layer is formed by depositing silicon nitride by a plasma CVD method. 3. The wiring forming method according to claim 1, wherein the oxidation prevention layer is formed by surface nitriding treatment of the insulating film.