KR100430589B1 - Cvd tungsten deposition method for contact plug - Google Patents
Cvd tungsten deposition method for contact plug Download PDFInfo
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- KR100430589B1 KR100430589B1 KR10-2002-0021209A KR20020021209A KR100430589B1 KR 100430589 B1 KR100430589 B1 KR 100430589B1 KR 20020021209 A KR20020021209 A KR 20020021209A KR 100430589 B1 KR100430589 B1 KR 100430589B1
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- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 title claims abstract description 73
- 239000010937 tungsten Substances 0.000 title claims abstract description 73
- 229910052721 tungsten Inorganic materials 0.000 title claims abstract description 73
- 238000000151 deposition Methods 0.000 title claims description 28
- 238000000034 method Methods 0.000 claims abstract description 20
- 238000002161 passivation Methods 0.000 claims abstract description 20
- 230000008021 deposition Effects 0.000 claims abstract description 16
- 230000006911 nucleation Effects 0.000 claims description 16
- 238000010899 nucleation Methods 0.000 claims description 16
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 8
- 229910052710 silicon Inorganic materials 0.000 claims description 8
- 239000010703 silicon Substances 0.000 claims description 8
- 239000002356 single layer Substances 0.000 claims description 8
- 238000011946 reduction process Methods 0.000 claims description 5
- 239000006227 byproduct Substances 0.000 claims description 4
- 238000004519 manufacturing process Methods 0.000 claims description 4
- 238000009792 diffusion process Methods 0.000 claims description 2
- 238000005530 etching Methods 0.000 claims 1
- 238000005137 deposition process Methods 0.000 abstract description 17
- 230000008569 process Effects 0.000 abstract description 13
- 230000008901 benefit Effects 0.000 abstract description 3
- 230000001934 delay Effects 0.000 abstract 1
- 238000005389 semiconductor device fabrication Methods 0.000 abstract 1
- 238000005229 chemical vapour deposition Methods 0.000 description 12
- 238000006722 reduction reaction Methods 0.000 description 7
- 230000009467 reduction Effects 0.000 description 6
- 239000010410 layer Substances 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 239000011800 void material Substances 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/32051—Deposition of metallic or metal-silicide layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
- H01L21/76876—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for deposition from the gas phase, e.g. CVD
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- Condensed Matter Physics & Semiconductors (AREA)
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- Manufacturing & Machinery (AREA)
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Abstract
본 발명에서는 반도체 소자 제조 공정 중 콘택 플러그 형성 공정에서 CVD 텅스텐 증착에 있어서, 가로세로비가 높게 설정되는 깊은 콘택홀에 대한 텅스텐 증착시에는 텅스텐 증착을 지연시키는 N2 패시베이션 막을 콘택홀 하단부로 갈수록 농도가 낮게 콘택홀내 증착시킨 후, 텅스텐 비아 필 막 형성을 진행함으로써, 텅스텐 비아 필 막이 N2 패시베이션 막이 먼저 식각되는 콘택홀 하단부에서부터 순차적으로 상단부로 증착되도록 제어하여 콘택홀내 텅스텐 비아 필 막이 고르게 증착되도록 하는 이점이 있다. 또한 상기 콘택홀내 증착되는 텅스텐의 비아 필 막의 스텝커버리지가 기준치 이하로 되는 경우에는 콘택홀의 깊이에 따라 N2 패시베이션 막 증착 공정과 텅스텐 비아 필 막 증착 공정을 반복 수행하도록 함으로써, 스텝커버리지가 일정 기준으로 유지될 수 있도록 하는 이점이 있다.In the present invention, in the CVD tungsten deposition in the contact plug forming process of the semiconductor device fabrication process, the concentration of N2 passivation film which delays tungsten deposition during the tungsten deposition to the deep contact hole where the aspect ratio is set to the lower portion of the contact hole becomes lower. After deposition in the contact hole, the tungsten via fill film is formed, thereby controlling the tungsten via fill film to be sequentially deposited from the bottom of the contact hole where the N2 passivation film is first etched to the top, thereby allowing the tungsten via fill film to be evenly deposited in the contact hole. . In addition, when the step coverage of the tungsten via fill film deposited in the contact hole is less than the reference value, the step coverage is maintained on a predetermined basis by repeatedly performing the N2 passivation film deposition process and the tungsten via fill film deposition process according to the depth of the contact hole. There is an advantage to this.
Description
본 발명은 반도체 장치의 텅스텐 콘택 플러그 형성 방법에 관한 것으로, 특히 VIA 및 콘택 플러그 생성을 위한 CVD(Chemical Vapor Deposition) 텅스텐 증착 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a tungsten contact plug in a semiconductor device, and more particularly, to a method of depositing a chemical vapor deposition (CVD) tungsten for producing VIA and contact plugs.
최근 들어 반도체 소자의 고집적화 경향에 따라 소자와 배선이 차지하는 평면적의 크기는 점차 줄어들고 있으며, 소자의 고집적화를 위한 반도체 소자의 입체화, 다층화에 따라 콘택홀의 깊이는 점점더 깊어져서 콘택홀 단면의 가로세로비(aspect ratio) 또한 증가하고 있다.Recently, the size of planar area occupied by devices and wirings is gradually decreasing according to the trend of high integration of semiconductor devices, and the depth of contact holes becomes deeper according to the three-dimensional and multi-layered semiconductor devices for high integration. The aspect ratio is also increasing.
상기와 같은 콘택홀에서의 가로세로비의 증가는 텅스텐 콘택 플러그 생성시에 도 1에서 도시된 바와 같은 보이드(Void)(100) 현상을 초래하여 통상적인 스퍼터링(Sputtering) 공정으로 콘택홀을 채우기 어렵게 되는 문제점이 있었다.Increasing the aspect ratio in the contact hole as described above causes voids (Void) 100 as shown in FIG. 1 when the tungsten contact plug is generated, making it difficult to fill the contact hole by a conventional sputtering process. There was a problem.
도 2는 종래 CVD 텅스텐 증착 공정을 도시한 처리 흐름도이다. 상기 도 1을 참조하면, CVD 텅스텐 증착을 위해서는 먼저 (S200)단계에서 텅스텐 증착 공정에서 사용되는 WF6 가스로 인한 콘택홀의 하지막인 베리어 티타늄 층의 손상을 방지시키며, 텅스텐 누클리에션(Nucleation) 막의 생성을 돕는 실리콘 모노레이어를 수 Å만큼 얇게 증착시킨다. 이어 (S202)단계에서 아래의 [화학식 1]에서와 같이 SiH4 환원을 통해 상기 실리콘 모노레이어(Mono layer) 위에 텅스텐 누클리에이션 막을 증착시킨다.2 is a process flow diagram illustrating a conventional CVD tungsten deposition process. Referring to FIG. 1, in order to deposit CVD tungsten, the barrier titanium layer, which is a base film of the contact hole, is prevented from being damaged by the WF6 gas used in the tungsten deposition process in step S200, and the tungsten nucleation film is removed. A thin silicon monolayer is deposited by several thin layers to aid in production. Subsequently, in step S202, a tungsten nucleation film is deposited on the silicon monolayer through SiH 4 reduction as shown in [Formula 1] below.
이는 후에 텅스텐 비아 필 막 증착 공정에서 H2 환원시 부산물로 생성되는 HF에 의한 콘택홀 하지막의 손상을 방지시키기 위한 것이다.This is to prevent damage to the underlying contact hole film by HF, which is produced as a by-product during H2 reduction in the tungsten via fill film deposition process.
그리고 (S204)단계에서 아래의 [화학식 2]에서와 같이 높은 스텝 커버리지를 가지는 H2환원을 통해 상기 누클리에이션 막 위에 텅스텐 비아 필 막을 증착시켜 콘택홀을 텅스텐으로 채움으로써 텅스텐 콘택 플러그를 생성하게 되는 것이다.In step S204, a tungsten via fill film is deposited on the nucleation film through H 2 reduction having a high step coverage as shown in [Formula 2] to fill a contact hole with tungsten to generate a tungsten contact plug. Will be.
그러나 상기한 바와 같은 종래 텅스텐 증착 방법으로는 7:1 이상의 고 가로세로비율의 콘택홀에서는 홀의 바닥과 측벽부의 텅스텐 증착이 취약할 수밖에 없으며, 이를 위해 종래에는 공정 온도를 낮추거나 공정 압력을 높이는 방법으로 스택킹 코이피션트(Stacking coefficient)를 낮추어줌으로써 높은 스텝 커버리지(Step coverage)를 이룰 수 있도록 제어하고 있으나, 상기와 같이 공정 온도나 공정 압력을 조절하는 방법은 장비의 특성상 한계가 있어서 고 비율의 가로세로비를 가지는 콘택홀의 텅스텐 증착 공정에서는 좋은 스텝 커버리지를 얻을 수 없는 문제점이 있었다.However, in the conventional tungsten deposition method as described above, the tungsten deposition of the bottom and sidewall portions of the holes is inevitably weak in the high aspect ratio contact holes, and the conventional method is to lower the process temperature or increase the process pressure. By controlling the stacking coefficient to reduce the high step coverage (Step coverage), but as described above, the method of controlling the process temperature or process pressure is limited due to the characteristics of the equipment has a high ratio In the tungsten deposition process of a contact hole having an aspect ratio, there is a problem in that good step coverage cannot be obtained.
따라서, 본 발명의 목적은 고 비율의 가로세로비를 가지는 콘택홀에서도 안정적인 텅스텐 콘택 플러그를 형성할 수 있도록 하는 CVD 텅스텐 증착 방법을 제공함에 있다.Accordingly, it is an object of the present invention to provide a CVD tungsten deposition method for forming a stable tungsten contact plug even in a contact hole having a high aspect ratio.
상술한 목적을 달성하기 위한 본 발명은 콘택 플러그 형성을 위한 CVD 텅스텐 증착 방법에 있어서, (a)콘택 플러그를 형성할 콘택홀내 텅스텐 누클리에이션 막이 안정적으로 성장할 수 있도록 실리콘 모노레이어를 증착시키는 단계와; (b)SIH4 환원 공정을 통해 상기 실리콘 모노레이어 위에 텅스텐 누클리션 막을 증착시키는 단계와; (c)상기 누클리션 막 위에 N2 패시베이션 막을 증착시켜 상기 콘택 플러그 형성을 위한 텅스텐 비아 필 막의 생성을 지연시키는 단계와; (d)H2 환원 공정을 통해 상기 누클리션 막 위로 텅스텐 비아 필 막을 증착시켜 콘택 플러그를 형성시키는 단계;를 포함하는 것을 특징으로 한다.The present invention for achieving the above object is a CVD tungsten deposition method for forming a contact plug, the method comprising the steps of: (a) depositing a silicon monolayer to stably grow a tungsten nucleation film in the contact hole to form a contact plug; ; (b) depositing a tungsten nucleation film on the silicon monolayer via a SIE4 reduction process; (c) depositing an N2 passivation film on the nucleation film to delay production of a tungsten via fill film for forming the contact plug; (d) depositing a tungsten via fill film on the nucleation film through an H 2 reduction process to form a contact plug.
도 1은 보이드 발생한 종래 콘택홀 단면 예시도,1 is an exemplary cross-sectional view of a void generation conventional contact hole;
도 2는 종래 CVD 텅스텐 증착 공정 처리 흐름도,2 is a flow chart of a conventional CVD tungsten deposition process;
도 3은 본 발명의 실시 예에 따른 CVD 텅스텐 증착 공정 처리 흐름도,3 is a flow chart of a CVD tungsten deposition process according to an embodiment of the present invention,
도 4는 본 발명의 실시 예에 따른 텅스텐 콘택 플러그 단면 예시도.4 is a cross-sectional view illustrating a tungsten contact plug according to an embodiment of the present invention.
이하, 첨부된 도면을 참조하여 본 발명에 따른 바람직한 실시 예의 동작을 상세하게 설명한다.Hereinafter, with reference to the accompanying drawings will be described in detail the operation of the preferred embodiment according to the present invention.
도 3은 본 발명의 실시 예에 따른 CVD 텅스텐 증착 공정을 도시한 처리 흐름도이다. 도 4는 상기 도 3의 공정 수순에 따라 적층된 콘택홀의 단면을 도시한 것이다. 특히, 본 발명에서는 N2 패시베이션(Passivation) 막을 이용하여 텅스텐 증착시 콘택홀의 하단부보다 콘택홀의 상단부에 먼저 텅스텐이 증착되는 것을 지연시킴으로써, 콘택홀내 상/하단부의 텅스텐 증착 비율을 조절할 수 있도록 하였다. 이하 상기 도 3 및 도 4를 참조하여 본 발명의 실시 예를 상세히 설명하기로 한다.3 is a process flow diagram illustrating a CVD tungsten deposition process in accordance with an embodiment of the present invention. 4 is a cross-sectional view of the contact holes stacked in accordance with the process of FIG. In particular, in the present invention, by delaying the deposition of tungsten at the upper end of the contact hole first than the lower end of the contact hole during tungsten deposition using an N2 passivation film, it is possible to control the upper and lower tungsten deposition ratio in the contact hole. Hereinafter, embodiments of the present invention will be described in detail with reference to FIGS. 3 and 4.
먼저 CVD 텅스텐 증착을 위해서 (S300)단계에서 텅스텐 증착 공정에서 사용되는 WF6 가스로 인한 콘택홀(400)의 하지막인 베리어 티타늄 층의 손상을 방지시키며, 텅스텐 누클리에이션 막의 생성을 돕는 실리콘 모노레이어(402)를 수 Å만큼 얇게 증착시킨다.First, in order to CVD tungsten deposition (S300) to prevent the damage of the barrier titanium layer, the underlying layer of the contact hole 400 due to the WF6 gas used in the tungsten deposition process, the silicon monolayer to help the formation of tungsten nucleation film 402 is deposited as thin as several milliseconds.
이어 (S302)단계에서 SiH4환원을 통해 상기 실리콘 모노레이어(402) 위에 텅스텐 누클리에이션 막(404)을 증착시킨다. 상기 누클리에이션 막(404)은 전술한 바와 같이 이후에 진행될 텅스텐 비아 필 막 형성 공정에서 H2 환원시 부산물로 생성되는 HF 에 의한 콘택홀 하지막의 손상을 방지하기 위한 것이다.Next, in step S302, a tungsten nucleation film 404 is deposited on the silicon monolayer 402 through SiH 4 reduction. The nucleation film 404 is to prevent damage to the underlying contact hole film by HF generated as a by-product during H2 reduction in the tungsten via fill film forming process to be performed as described above.
그런 후, (S304)단계에서 상기 누클리이션 막(404)위에 N2 패시베이션 막(406)을 증착시킨다. 상기 N2 패시베이션 막(406)은 전술한 바와 같이 콘택 플러그 형성시 콘택홀(400)내 상단부부터 텅스텐 증착이 진행되는 것을 지연시키기 위한 것으로, 상기 도 4에서 보여지는 바와 같이 N2 가스의 확산성(Diffusivity)에 의해 콘택홀 상단부에 많이 증착되며, 콘택홀 내부로 갈수록 증착 정도가 약해지게 형성된다.Thereafter, an N2 passivation film 406 is deposited on the nucleation film 404 in step S304. As described above, the N2 passivation film 406 is to delay tungsten deposition from the upper end of the contact hole 400 when forming the contact plug. As shown in FIG. 4, the diffusivity of the N2 gas is shown. Is deposited on the upper end of the contact hole, and the degree of deposition becomes weaker toward the inside of the contact hole.
이어 (S306)단계에서 CVD 텅스텐으로 비아 필 막 증착 공정을 수행하여 콘택홀(400)내 텅스텐을 증착시키게 되며, 상기 비아 필 막 증착 공정에서는 상기 [화학식 2]에서와 같이 높은 스텝 커버리지를 가지는 H2 환원 반응을 통하여 텅스텐 비아 필 막(408)을 생성시키게 된다.Subsequently, a via fill film deposition process is performed by CVD tungsten in step S306 to deposit tungsten in the contact hole 400. In the via fill film deposition process, H2 having a high step coverage as shown in [Formula 2]. The reduction reaction produces a tungsten via fill film 408.
즉, 상기 비아 필 막 증착 공정에서 N2 패시베이션 막(406)은 H2 환원시의 부산물인 HF나 WF6 공정 가스에 의하여 식각되게 되며, 상기 N2 패시베이션 막(406)이 모두 식각된 후에야, 텅스텐 비아 필 막(408)이 성장하기 시작하여 콘택홀(400)이 텅스텐으로 채워지게 되는 것이다. 이때 상기 N2 패시베이션 막(406)은 전술한 바와 같이 N2 가스의 확산 특성으로 인해 콘택홀(400)의 하단부보다 상단부에 두텁게 증착되어 있기 때문에 상단부의 N2 패시베이션 막(406)이 식각되는 동안에 상대적으로 N2 패시베이션 막(406)이 얇게 증착되었던 콘택홀(400) 하단 바닥부에서는 텅스텐 비아 필 막(408)이 먼저 성장하기 시작하게 된다. 이에 따라 상기 도 4에서 보여지는 바와 같이 텅스텐이 콘택홀(400)의 바닥부에서부터 차례로 성장하게 되어 스텝 커버리지가 높아지게 되는 것이다.That is, in the via fill film deposition process, the N2 passivation film 406 is etched by HF or WF6 process gas which is a by-product of H2 reduction, and after the N2 passivation film 406 is etched, the tungsten via fill film is etched. 408 begins to grow and the contact hole 400 is filled with tungsten. At this time, since the N2 passivation film 406 is deposited at the upper end of the contact hole 400 thicker due to the diffusion characteristics of the N2 gas as described above, the N2 passivation film 406 at the upper end is relatively relatively N2. At the bottom bottom of the contact hole 400 where the passivation film 406 is thinly deposited, the tungsten via fill film 408 starts to grow first. As a result, as shown in FIG. 4, tungsten is sequentially grown from the bottom of the contact hole 400, thereby increasing step coverage.
또한 본 발명의 실시 예에서는 상기 콘택홀내 증착되는 텅스텐의 비아 필 막의 스텝 커버리지가 기준치 이하로 되는 경우에는 콘택홀의 깊이에 따라 N2 패시베이션 막 증착 공정과 텅스텐 비아 필 막 증착 공정을 반복 수행함으로써, 스텝 커버리지가 일정 기준으로 유지될 수 있도록 한다.In addition, in the embodiment of the present invention, when the step coverage of the tungsten via fill film deposited in the contact hole is less than the reference value, the step coverage is repeated by repeatedly performing the N2 passivation film deposition process and the tungsten via fill film deposition process according to the depth of the contact hole. To be maintained on a certain basis.
한편 상술한 본 발명의 설명에서는 구체적인 실시 예에 관해 설명하였으나, 여러 가지 변형이 본 발명의 범위에서 벗어나지 않고 실시될 수 있다. 따라서 발명의 범위는 설명된 실시 예에 의하여 정할 것이 아니고 특허청구범위에 의해 정하여져야 한다.Meanwhile, in the above description of the present invention, specific embodiments have been described, but various modifications may be made without departing from the scope of the present invention. Therefore, the scope of the invention should be determined by the claims rather than by the described embodiments.
이상에서 설명한 바와 같이, 본 발명에서는 반도체 소자 제조 공정 중 콘택 플러그 형성 공정에서 CVD 텅스텐 증착에 있어서, 가로세로비가 높게 설정되는 깊은 콘택홀에 대한 텅스텐 증착시에는 텅스텐 증착을 지연시키는 N2 패시베이션 막을 콘택홀 하단부로 갈수록 농도가 낮게 콘택홀내 증착시킨 후, 텅스텐 비아 필 막 형성을 진행함으로써, 텅스텐 비아 필 막이 N2 패시베이션 막이 먼저 식각되는 콘택홀 하단부에서부터 순차적으로 상단부로 증착되도록 제어하여 콘택홀내 텅스텐 비아 필 막이 고르게 증착되도록 하는 이점이 있다.As described above, in the present invention, in the CVD tungsten deposition in the contact plug forming process of the semiconductor device manufacturing process, an N2 passivation film for delaying tungsten deposition during tungsten deposition to a deep contact hole in which the aspect ratio is set to high is used as a contact hole. As the concentration is lowered toward the lower end, the tungsten via fill film is formed, and then the tungsten via fill film is formed so that the tungsten via fill film is controlled to be sequentially deposited from the lower end of the contact hole where the N2 passivation film is etched first to the upper part, so that the tungsten via fill film in the contact hole is evenly distributed. There is an advantage to being deposited.
또한 상기 콘택홀내 증착되는 텅스텐의 비아 필 막의 스텝 커버리지가 기준치 이하로 되는 경우에는 콘택홀의 깊이에 따라 N2 패시베이션 막 증착 공정과 텅스텐 비아 필 막 증착 공정을 반복 수행하도록 함으로써, 스텝커버리지가 일정 기준으로 유지될 수 있도록 하는 이점이 있다.In addition, when the step coverage of the tungsten via fill film deposited in the contact hole is less than the reference value, the step coverage is maintained on a predetermined basis by repeatedly performing the N2 passivation film deposition process and the tungsten via fill film deposition process according to the depth of the contact hole. There is an advantage to this.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05144951A (en) * | 1991-09-27 | 1993-06-11 | Sony Corp | Wiring formation method |
| JPH08124876A (en) * | 1994-10-27 | 1996-05-17 | Sony Corp | Formation of high-melting-point metal film |
| KR19990026626A (en) * | 1997-09-25 | 1999-04-15 | 윤종용 | Method of forming metal wiring in semiconductor process |
| JPH11176767A (en) * | 1997-12-11 | 1999-07-02 | Toshiba Corp | Manufacture of semiconductor device |
| KR20010109474A (en) * | 2000-05-31 | 2001-12-10 | 윤종용 | Metal wiring method of semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05144951A (en) * | 1991-09-27 | 1993-06-11 | Sony Corp | Wiring formation method |
| JPH08124876A (en) * | 1994-10-27 | 1996-05-17 | Sony Corp | Formation of high-melting-point metal film |
| KR19990026626A (en) * | 1997-09-25 | 1999-04-15 | 윤종용 | Method of forming metal wiring in semiconductor process |
| JPH11176767A (en) * | 1997-12-11 | 1999-07-02 | Toshiba Corp | Manufacture of semiconductor device |
| KR20010109474A (en) * | 2000-05-31 | 2001-12-10 | 윤종용 | Metal wiring method of semiconductor device |
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