JP2013093512A - Manufacturing method of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To keep a void from being formed in a contact plug by forming an inclination at a side wall of a contact hole with good controllability.SOLUTION: The manufacturing method of a semiconductor device comprises the steps of: forming a first contact hole (dashed line) at an insulator film 10; forming a second contact hole 13 whose inner wall is inclined by applying chemical dry etching where the upper the insulator film which constitutes an inner wall of the first contact hole is, the larger the etching amount is; and forming a contact plug in the second contact hole.

Description

  The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming a fine contact hole in an insulating film.

  In a semiconductor device, a contact hole is formed in an interlayer insulating film and a conductor (contact plug) is embedded to connect a lower conductor of the interlayer insulating film and an upper conductor.

  Usually, such a contact hole is formed by a photolithography technique and a dry etching technique.

  Usually, in the dry etching method, anisotropic dry etching is used to transfer a pattern faithful to the mask pattern to a workpiece. In short, it is vertical etching using the electric field acceleration of etching gas ions generated in plasma. Fluorine ions are mainly used for etching silicon compounds such as a silicon oxide film and a silicon nitride film, and chlorine ions are mainly used for etching metals such as an aluminum film and a tungsten film. Since anisotropic dry etching does not cause deviation from the mask pattern in the lateral direction, a fine pattern can be formed. At present, it is used as a mainstream technology in the manufacture of semiconductor devices in general.

  However, in the production of a semiconductor device of a generation with further miniaturization, there has been a problem that this vertical etching adversely affects. Hereinafter, this problem will be described.

  FIG. 26A shows a state in which the interlayer insulating film 103 is formed on the semiconductor substrate 100 in which the diffusion layer 102 is formed in a predetermined region on the upper surface, and the contact hole 104 exposing the upper surface of the diffusion layer 102 is formed. Yes. Thereafter, as shown in FIG. 26B, a conductor 105 is formed on the entire surface, and further, as shown in FIG. 26C, etching back is performed by dry etching to form a contact plug 107. A process of connecting a wiring (not shown) to the upper surface of the wiring and connecting the wiring and the diffusion layer 102 has been used for a long time in semiconductor manufacturing. The diffusion layer 102 shown in the figure is an example, and may be a contact plug located in a lower layer, a wiring located in a lower layer, or the like.

  In FIG. 26A, the contact hole 104 formed in the interlayer insulating film 103 has become extremely small with a diameter of about 30 nm as the semiconductor device is miniaturized. On the other hand, there is a situation that the wiring 108 cannot be thinned even if miniaturization progresses due to the necessity of maintaining a low resistance. Accordingly, the thickness of the interlayer insulating film 103 for insulating the wiring 108 from the upper layer wiring is hardly reduced, and a constant film thickness is maintained. For this reason, the aspect ratio (depth / diameter) of the contact hole 104 increases as the miniaturization generation of the semiconductor device advances. When the aspect ratio increases, as shown in FIG. 26B, when the conductor 105 is formed, the conductor 105 is insufficiently embedded in the contact hole having a small diameter, and the void 106 is generated. Next, as shown in FIG. 26C, even if the conductor 105 formed on the upper surface of the interlayer insulating film 103 is removed to form the contact plug 107, the void 106 remains. As a result, there is a problem that the cross-sectional area in a plan view of the contact plug 107 where the void 106 occurs is reduced and the resistance is increased. The increase in resistance becomes a cause of hindering high-speed operation of the semiconductor device. In addition, as shown in FIG. 26D, when the contact plug 107 is formed by etching back the conductor 105 formed on the upper surface of the interlayer insulating film 103 by dry etching, the void 106 is formed by overetching. As a result of exposing the upper part, through-etching is performed up to the diffusion layer 102, which causes a problem of poor bonding.

  The method for manufacturing a semiconductor device of the present invention has been devised in view of the above problems, and the amount of etching increases as the step of forming a contact hole in the insulating film and above the insulating film constituting the inner wall of the contact hole are performed. The method includes a step of forming an inclination on the inner wall of the contact hole by performing chemical dry etching, and a step of forming a contact plug in the contact hole.

  According to the present invention, the opening diameter of the contact hole can be uniformly enlarged on the substrate surface toward the upper portion, and the formation of voids in the contact plug embedded in the contact hole can be prevented.

It is a graph showing the SiN / SiO ₂ selectivity ratio with respect to the temperature conditions of the chemical dry etching. It is a top view of the MOS transistor which concerns on one Example of this invention. FIG. 5 is a process cross-sectional view illustrating a contact formation process connected to the diffusion layer of the MOS transistor shown in FIG. 2. FIG. 5 is a process cross-sectional view illustrating a contact formation process connected to the diffusion layer of the MOS transistor shown in FIG. 2. FIG. 5 is a process cross-sectional view illustrating a contact formation process connected to the diffusion layer of the MOS transistor shown in FIG. 2. FIG. 5 is a process cross-sectional view illustrating a contact formation process connected to the diffusion layer of the MOS transistor shown in FIG. 2. FIG. 5 is a process cross-sectional view illustrating a contact formation process connected to the diffusion layer of the MOS transistor shown in FIG. 2. FIG. 5 is a process cross-sectional view illustrating a contact formation process for connecting to the gate electrode of the MOS transistor shown in FIG. 2. FIG. 5 is a process cross-sectional view illustrating a contact formation process for connecting to the gate electrode of the MOS transistor shown in FIG. 2. FIG. 5 is a process cross-sectional view illustrating a contact formation process for connecting to the gate electrode of the MOS transistor shown in FIG. 2. 1 is a plan view of a memory cell array according to an embodiment of the present invention. 12A and 12B are process cross-sectional views illustrating a process of forming a capacitor contact plug in the memory cell array of FIG. 11, where FIG. 11A is a cross-sectional view taken along the line AA ′ in FIG. Indicates. 12A and 12B are process cross-sectional views illustrating a process of forming a capacitor contact plug in the memory cell array of FIG. 11, where FIG. 11A is a cross-sectional view taken along the line AA ′ in FIG. 11, and FIG. Indicates. 12A and 12B are process cross-sectional views illustrating a process of forming a capacitor contact plug in the memory cell array of FIG. 11, where FIG. 11A is a cross-sectional view taken along the line AA ′ in FIG. Indicates. 12A and 12B are process cross-sectional views illustrating a process of forming a capacitor contact plug in the memory cell array of FIG. 11, where FIG. 11A is a cross-sectional view taken along the line AA ′ in FIG. Indicates. 12A and 12B are process cross-sectional views illustrating a process of forming a capacitor contact plug in the memory cell array of FIG. 11, where FIG. 11A is a cross-sectional view taken along the line AA ′ in FIG. 11, and FIG. Indicates. FIG. 6 is a plan view of a memory cell array according to another embodiment of the present invention. 18A and 18B are process cross-sectional views illustrating a process for forming a capacitor contact plug in the memory cell array of FIG. 17, where FIG. 18A is a cross-sectional view taken along the line AA ′ in FIG. Indicates. 18A and 18B are process cross-sectional views illustrating a process for forming a capacitor contact plug in the memory cell array of FIG. 17, where FIG. 18A is a cross-sectional view taken along the line AA ′ in FIG. Indicates. 18A and 18B are process cross-sectional views illustrating a process for forming a capacitor contact plug in the memory cell array of FIG. 17, where FIG. 18A is a cross-sectional view taken along the line AA ′ in FIG. Indicates. 18A and 18B are process cross-sectional views illustrating a process for forming a capacitor contact plug in the memory cell array of FIG. 17, where FIG. 18A is a cross-sectional view taken along the line AA ′ in FIG. Indicates. 18A and 18B are process cross-sectional views illustrating a process for forming a capacitor contact plug in the memory cell array of FIG. 17, where FIG. 18A is a cross-sectional view taken along the line AA ′ in FIG. Indicates. 18A and 18B are process cross-sectional views illustrating a process for forming a capacitor contact plug in the memory cell array of FIG. 17, where FIG. 18A is a cross-sectional view taken along the line AA ′ in FIG. 17 and FIG. Indicates. FIG. 18 is a process cross-sectional view illustrating a capacitor contact plug formation process in the memory cell array of FIG. 17. 18A and 18B are process cross-sectional views illustrating a process for forming a capacitor contact plug in the memory cell array of FIG. 17, where FIG. 18A is a cross-sectional view taken along the line AA ′ in FIG. Indicates. It is process sectional drawing explaining one subject of this invention.

Description of Chemical Dry Etching (CDE) Conditions Applied to the Present Invention In conventional CDE, a technique is known in which the surface of a silicon oxide film is etched away by a certain amount with high accuracy. As a result of various studies of applying CDE to the silicon nitride film, the present inventor etched the silicon nitride film with an etching amount equivalent to that of the silicon oxide film by controlling the temperature of the etching atmosphere to 70 ° C. or higher. I found out that I can do it.

FIG. 1 is a graph showing SiN / SiO ₂ selectivity with respect to CDE temperature conditions. As shown in the graph, the selection ratio decreases linearly from room temperature (25 ° C.) to around 45 ° C., and when the temperature is further increased, the selection ratio gradually decreases. At a temperature of 70 ° C. or higher, the selectivity is almost 1, and the silicon nitride film can be etched with the same etching amount as the silicon oxide film. In the case of a silicon oxide film alone or a silicon nitride film alone, there is no need to consider the selection ratio, so the temperature may be controlled so as to obtain a desired etching rate.

In CDE, deposition may occur due to a reaction between constituent atoms in the insulating film and constituent atoms in the etching gas. When an insulating film containing silicon as a constituent atom such as silicon oxide or silicon nitride is used as an etching gas with a gas containing fluorine (such as HF or NF ₃ ) and ammonia (NH ₃ ), ammonium fluoride is used. (NH ₄ F) or the like is generated in the etching atmosphere, while fluorine (F) and silicon (Si) in the insulating film react to generate silicon fluoride (SiF ₄ ). Silicon fluoride and ammonium fluoride react to produce ammonium silicofluoride ((NH ₄ ) ₂ SiF ₆ ).
For example, in the case of silicon oxide (SiO ₂ ), the following reaction proceeds.
SiO ₂ + 4F → SiF ₄
SiF ₄ + 2NH ₄ F → (NH ₄ ) ₂ SiF ₆

  Ammonium silicofluoride adheres to the insulating film as a deposit, thereby inhibiting etching. Depending on the conditions, the reaction may be saturated at about 10 nm and a desired etching amount may not be ensured. Ammonium silicofluoride is sublimable and the insulating film exposed by sublimation is etched again. In this manner, etching proceeds gradually by cycle etching in which ammonium silicofluoride is repeatedly deposited and sublimated. Pure ammonium silicofluoride decomposes at temperatures above 160 ° C. Although sublimation occurs at a temperature lower than the decomposition temperature, heating to 100 ° C. or higher is preferable in order to increase the sublimation rate. Therefore, in the cycle etching, an etching gas is supplied to deposit ammonium silicofluoride at, for example, less than 100 ° C., and the etching gas supply is stopped and heated to 100 ° C. or more to sublimate or decompose ammonium silicofluoride. Then, the removal step can be repeated. As described above, when it is difficult to secure a desired etching amount, cycle etching is suitable.

  Further, when the above conditions were applied to the contact hole, it was found that the etching amount increased toward the upper part of the contact hole when the interlayer insulating film was either a silicon nitride film or a silicon oxide film. In particular, it is possible to accurately control the widening of the upper portion of the contact hole by performing cyclic etching that repeats deposition and sublimation of ammonium silicofluoride.

  Further, in the present invention, when a silicon nitride film and a silicon oxide film are mixedly exposed in the contact hole, the same etching amount is used for both films, thereby widening the upper portion of the contact hole. A method is also provided.

  EXAMPLES Hereinafter, although an Example is given and this invention is demonstrated concretely, this invention is not limited only to these Examples.

Example 1
FIG. 2 shows a plan view of an example of the layout of the MOS transistor. 3 to 7 show sectional views taken along the line AA ′ of FIG.

(Figure 3)
First, an active region 3 surrounded by an element isolation (STI: Shallow Trench Isolation) region 2 is formed on a semiconductor substrate 1. Next, a gate electrode 5 extending across the active region 3 and extending in the X direction is formed. Here, a gate insulating film 4 having a thickness of 5 nm, a gate electrode 5 having a thickness of 50 nm, and a cover insulating film 6 made of a silicon nitride film having a thickness of 50 nm are stacked on the surface of the semiconductor substrate 1 in the active region 3. Next, after sequentially etching by lithography and dry etching, a sidewall (SW) insulating film 7 made of a silicon nitride film is formed on the sidewall. The gate electrode 5 includes a polycide structure in which a metal such as tungsten is stacked on polycrystalline silicon, a metal stacked film in which a low resistance metal such as tungsten is stacked on a barrier metal such as titanium nitride, and a hafnium silicate film on the gate insulating film 4. When a high dielectric constant film is used, a tungsten single layer structure or the like can be used. In any case, the uppermost surface of the gate electrode 5 is made of a metal such as tungsten.

  Subsequently, using the gate electrode pattern as a mask, impurities are introduced into the surface of the semiconductor substrate by ion implantation to form the source diffusion layer 8 and the drain diffusion layer 9.

  Finally, an interlayer insulating film 10 made of a silicon oxide film and having a thickness of 140 nm is formed so as to cover the gate electrode pattern. The interlayer insulating film 10 can be formed by forming a film by a CVD method or a spin coating method and then planarizing the surface by a CMP method.

(Fig. 4)
Next, using the mask 11 formed by lithography, a diffusion layer contact hole (first contact hole) 12 having a diameter of 30 nm connected to the source diffusion layer 8 and the drain diffusion layer 9 is formed in the interlayer insulating film 10 by dry etching. To do. The diffusion layer contact hole 12 is not in contact with the SW insulating film 7. FIG. 2 shows an example in which three are formed in parallel in the X direction on each diffusion layer. At this stage, the inner wall of the diffusion layer contact hole 12 is formed vertically as in the conventional method.

(Fig. 5)
Subsequently, after removing the mask 11, the opening diameter of the diffusion layer contact hole is enlarged by the CDE method of the present invention, and an inclination is formed on the side wall.

The conditions of the CDE method of this example are as follows.
Etching gas: NF ₃ (14 sccm), NH ₃ (50 sccm)
Pressure: 400 Pa (3 Torr)
Temperature: 35 ° C (when supplying etching gas) / 120 ° C (when sublimating ammonium fluorosilicate)
RF power: 30W
Time: 60 seconds

Similar effects can be obtained under the following conditions.
Etching gas: HF (40 sccm), NH ₃ (50 sccm)
Pressure: 11Pa (80mTorr)
Temperature: 35 ° C (when supplying etching gas) / 120 ° C (when sublimating ammonium fluorosilicate)
RF power: 0W
Time: 60 seconds

  As a result, a new diffusion layer contact hole (second contact hole) 13 is formed. The expansion D of the opening is controlled to 5 nm. The diameter increases from 30 nm to 40 nm. Since the bottom diffusion layer is made of silicon, it is not removed by CDE.

  For high-precision widening, cycle etching that repeats formation and sublimation of ammonium silicofluoride as described above is effective.

(Fig. 6)
A conductor 14 is formed on the entire surface by a CVD method so as to fill the diffusion layer contact hole 13. Since the contact hole is inclined from the vertical side wall, no void is generated. Examples of the conductor 14 include a single layer film of a metal such as polycrystalline silicon and tungsten, or a laminated film of a metal such as polycrystalline silicon and tungsten. In the case of tungsten formation, a metal silicide (for example, cobalt silicide) is formed on the surface of the diffusion layer or the upper surface of polycrystalline silicon that is formed first, and a barrier film such as titanium nitride (for example, Ti / TiN or the like) is formed between the insulating film. ) Is preferably formed.

(Fig. 7)
Finally, the conductor 14 formed on the interlayer insulating film 10 is removed by CMP or dry etching, and a diffusion layer contact plug 15 is formed in the diffusion layer contact hole 13. Further, a wiring 16 connected to the upper surface of the diffusion layer contact plug 15 is formed.

  According to the present embodiment, the inner wall of the diffusion layer contact hole 12 is composed of the interlayer insulating film 10 made of a silicon oxide film, and the diffusion layer has an inclination that widens the upper portion of the hole by using the above CDE condition. The contact hole 13 can be processed. As a result, it is possible to form the diffusion layer contact plug 15 that prevents the occurrence of voids in the conductor 14 that embeds the diffusion layer contact hole 13 and avoids an increase in resistance and etching damage to the diffusion layer.

Example 2
In the first embodiment, the diffusion layer contact hole connected to the source and drain diffusion layers has been described. However, as shown in FIG. 2, the gate contact hole connected to the gate electrode 5 can be formed in the same manner. The gate contact hole is formed through the interlayer insulating film 10 made of a silicon oxide film and the cover insulating film 6 made of a silicon nitride film. In the method according to the present invention, such different insulating films are laminated. Even if it is, it is applicable.
8 to 10 show sectional views taken along the line BB 'in FIG.

(Fig. 8)
In the step of FIG. 4 of the first embodiment, a gate contact hole (first contact hole) 17 is formed simultaneously with or separately from the formation of the diffusion layer contact hole 12.

(Fig. 9)
Similar to the step of FIG. 5 of the first embodiment, the opening diameter of the gate contact hole 17 is enlarged by the CDE method of the present invention, and an inclination is formed on the side wall. However, the atmospheric temperature when supplying the etching gas was set to 80 ° C. As a result, a gate contact hole (second contact hole) 18 whose opening diameter increases toward the top is formed. This step can be performed simultaneously with the step of FIG.

(Fig. 10)
Thereafter, the gate contact plug 19 and the wiring 16 are formed through the steps of FIGS. 6 and 7 of the first embodiment.

  As shown in this embodiment, the diameter of the opening can be increased in the same manner even when a different type of insulating film is exposed in the contact hole.

Example 3
FIG. 11 is a plan view of a memory cell array using embedded word lines (WL1 to WL3). In FIG. 11, 22 is an STI region, 24 is an active region, and is formed extending in the X ′ direction (first direction). The active regions 24 are divided by the STI regions 23 in the Y direction (second direction) to form island-shaped active regions 24a. Each active region 24a is further divided into three diffusion layers by two buried word lines extending in the Y direction. A diffusion layer region connected to the bit line is referred to as a bit line contact region 25, and a diffusion layer region to which the capacitor contact plug 35 is connected is referred to as a capacitor contact region 26. The bit line contact region 25 is arranged at the center of each active region 24a, and is connected to bit lines (BL1 to BL3) extending in the X direction (third direction). Capacitance contact regions 26 are disposed at both ends of each active region 24a, and a capacitor contact plug 35 is connected thereto.

  Hereinafter, a method for manufacturing the memory cell array will be described with reference to cross-sectional views. 12 to 16 are process cross-sectional views for explaining the manufacturing process of the memory cell array according to this embodiment. Each figure (a) is a line AA 'in FIG. 11, and each figure (b) is a line BB. 'Corresponds to the cross-section at the line.

(Fig. 12)
First, trenches to be the STI regions 22 and 23 are formed in the semiconductor substrate 21, and the STI regions 22 and 23 are formed by embedding an insulating film. Subsequently, impurity ions for the diffusion layer are implanted into the active region 24 to form a diffusion layer (not shown). Next, a word line trench is formed in the Y direction in FIG. 11, the word line conductor layer is buried, and a cap insulating film 27 made of a silicon nitride film is formed to planarize the surface. The word line and the semiconductor substrate 21 are separated by a gate insulating film (not shown). Further, the surface of the word line conductor layer is buried so as to be deeper than the depth of the active layer. Instead of the STI region 23, a dummy word line can be formed to separate the active region 24 into each active region 24a.

(Fig. 13)
Next, after forming a first interlayer insulating film 28 made of a silicon oxide film, a bit contact hole (not shown) that exposes the bit line contact region 25 is formed, and a conductor layer that becomes a bit line and a silicon nitride film are formed. A cover insulating film 29 to be formed is formed and patterned to form bit lines (BL1 to BL3). Further, first sidewalls (SWD1) made of a silicon nitride film are formed on the sidewalls of the bit lines (BL1 to BL3). Thereafter, a second interlayer insulating film 30 made of a silicon oxide film is formed on the entire surface, and planarized by CMP or the like using the cover insulating film 29 and the first sidewall (SWD1) as stoppers.

(Fig. 14)
A mask film 31 is formed on the second interlayer insulating film 30 and a capacitor contact hole (first contact hole) 32 exposing the capacitor contact region 26 is formed.

(Fig. 15)
Similar to the process of FIG. 5 of the first embodiment, the diameter of the opening of the capacitor contact hole 32 is enlarged by the CDE method of the present invention, and an inclination is formed on the side wall. However, the atmospheric temperature when supplying the etching gas was set to 80 ° C. Here, the second interlayer insulating film 30 made of a silicon oxide film and the first side wall (SWD1) made of a silicon nitride film are etched to the same extent, and both of them have a capacity contact hole (second second) whose diameter increases upward. Contact hole) 33 is formed.

(Fig. 16)
Thereafter, a capacitor contact plug 34 is formed, and a capacitor 35 is further formed. Thus, the diameter of the upper portion of the capacitor contact plug 34 is expanded, so that generation of voids can be suppressed and a contact area with the lower electrode of the capacitor 35 can be ensured even if the array pattern is miniaturized. it can.

Example 4
In the memory cell array shown in the third embodiment, when the miniaturization further proceeds, it is difficult to uniformly form the capacitor contact hole in the capacitor contact region, which may affect the capacitor characteristics. In this embodiment, the capacitor contact regions 26 facing each other in the adjacent island-like active regions 24a are opened in a lump, and a conductor serving as a contact plug is buried, and then a capacitor contact plug is formed by a twin plug method that is divided into two plugs. A method of forming will be described.

  FIG. 17 is a plan view of the memory cell array similarly to FIG. 11, and shows a mask region 41 and an opening region 42 extending in the Y direction. A region defined by the opening region 42 and the bit lines (BL1 to BL3) is called a unit opening 44, and a conductor serving as a contact plug is embedded in this portion.

  18 to 25 are process cross-sectional views illustrating the manufacturing process of the semiconductor device according to the present embodiment. In each figure, (a) is a cross-sectional view taken along the line AA ′ of FIG. 17, and (b). Shows a cross-sectional view taken along the line BB ′ of FIG.

(Fig. 18)
As in the third embodiment, after forming the first sidewall SWD1 on the side wall of the bit line, the second interlayer insulating film 30 made of a silicon oxide film is formed. In the third embodiment, the upper surface of the first sidewall SWD1 is used. However, in this embodiment, the upper surface of the second interlayer insulating film 30 is formed to be higher than the upper surface of the first sidewall SWD1. Next, a mask film 43 such as a photoresist is formed in the mask region 41.

(Fig. 19)
Using the mask film 43 as a mask, the first and second interlayer insulating films 28 and 30 made of a silicon oxide film exposed in the opening region 42 are etched. Thereby, the unit opening 44 is formed.

(Fig. 20)
After the silicon nitride film is formed, etch back is performed to form the second sidewall SWD2 on the sidewalls of the first and second interlayer insulating films 28 and 30 exposed to the unit opening 44 and the sidewall of the first sidewall SWD1. . The unit opening after the formation of the second sidewall SWD2 is defined as a unit opening (first contact hole) 45.

(Fig. 21)
Next, similarly to the step of FIG. 5 of the first embodiment, the opening diameter of the unit opening 45 is enlarged by the CDE method of the present invention, and an inclination is formed on the side wall (second contact hole). However, the atmospheric temperature when supplying the etching gas was set to 80 ° C.

(Fig. 22)
Subsequently, a conductor 46 serving as a capacitor contact plug is formed. The conductor 46 is etched back to such an extent that the cover insulating film 29 on the bit line is just exposed or not exposed. If it is formed lower than the surface of the cover insulating film 29, the third sidewall in the next step is also formed on the second sidewall sidewall of the bit line sidewall, and the subsequent separation of the conductor 46 may be insufficient.

(Fig. 23)
A silicon nitride film is formed and etched back to form the third sidewall SWD3. Further, using the third sidewall SWD 3 as a mask, the conductor 46 is etched and divided into two capacitive contact plugs 47 within the unit opening 45.

(Fig. 24)
An insulating film is formed on the entire surface and planarized by CMP or the like. As a result, the buried insulating film 48 is buried between the two capacitor contact plugs 47 in the unit opening 45.

(Fig. 25)
Thereafter, the capacitor 35 is formed as in the third embodiment.

  As shown in the present embodiment, the diameter of the opening can be similarly increased when the side walls of the unit opening 45 are all silicon nitride films. In addition, since the inclination angle of the inner wall of the opening can be precisely controlled by applying the CDE method of the present invention, in the twin plug structure, the distance between the lower center points of two plugs formed separately in one unit opening is obtained. The distance between the upper center points becomes wider than the distance, and the flexibility of the memory cell layout is improved without being restricted by the capacitor layout.

DESCRIPTION OF SYMBOLS 1,21 Semiconductor substrate 2,22,23 STI region 3,24 Active region 4 Gate insulating film 5 Gate electrode 6 Cover insulating film 7 Side wall insulating film 8 Source diffusion layer 9 Drain diffusion layer 10 Interlayer insulating film 11 Mask 12, 13 Diffusion layer contact hole 14 Conductor 15 Diffusion layer contact plug 16 Wiring 17, 18 Gate contact hole 19 Gate contact plug 25 Bit line contact region 26 Capacitance contact region 27 Cap insulating film 28 First interlayer insulating film 29 Cover insulating film 30 Second interlayer Insulating film 31 Mask film 32, 33 Capacitance contact hole 34 Capacitance contact plug 35 Capacitor 41 Mask region 42 Opening region 43 Mask film 44, 45 Unit opening 46 Conductor 47 Capacitor contact plug

Claims (18)

Forming a first contact hole in the insulating film;
Forming a second contact hole having an inclined inner wall by performing chemical dry etching in which the etching amount increases toward an upper portion of the insulating film constituting the inner wall of the first contact hole;
Forming a contact plug in the second contact hole;
A method for manufacturing a semiconductor device, comprising:   2. The method of manufacturing a semiconductor device according to claim 1, wherein the chemical dry etching includes cycle etching in which deposition by a reactant of an insulating film constituent atom and a constituent atom in an etching gas is repeated and sublimation of the reactant is repeated.   3. The method of manufacturing a semiconductor device according to claim 2, wherein the insulating film contains silicon as a constituent atom, contains a gas containing fluorine as the etching gas, and ammonia, and generates ammonium silicofluoride as the reactant.   The method of manufacturing a semiconductor device according to claim 3, wherein the insulating film constituting the inner wall of the contact hole includes at least one of a silicon oxide film and a silicon nitride film.   The method for manufacturing a semiconductor device according to claim 4, wherein the insulating film constituting the inner wall of the contact hole is a silicon oxide film.   The method for manufacturing a semiconductor device according to claim 4, wherein the insulating film constituting the inner wall of the contact hole is a silicon nitride film.   The method of manufacturing a semiconductor device according to claim 4, wherein the insulating film constituting the inner wall of the contact hole includes both a silicon oxide film and a silicon nitride film.   The method of manufacturing a semiconductor device according to claim 7, wherein the chemical dry etching is performed at a temperature of 70 ° C. or higher.   The method of manufacturing a semiconductor device according to claim 8, wherein the chemical dry etching has an etching selectivity of a silicon oxide film and a silicon nitride film of 1. The contact hole is a diffusion layer contact hole connected to the source and drain diffusion layers of the MOS transistor,
The method of manufacturing a semiconductor device according to claim 4, wherein the diffusion layer contact hole is formed so as to penetrate an interlayer insulating film that is a silicon oxide film. The contact hole is a gate contact hole connected to the gate electrode of the MOS transistor,
5. The semiconductor device according to claim 4, wherein the gate contact hole is formed through a cover insulating film that is a silicon nitride film on the gate electrode and an interlayer insulating film that is a silicon oxide film on the cover insulating film. Production method. The contact holes are a diffusion layer contact hole connected to the source and drain diffusion layers of the MOS transistor and a gate contact hole connected to the gate electrode of the MOS transistor,
The insulating film constituting the inner wall of the diffusion layer contact hole is a silicon oxide film,
The insulating film constituting the inner wall of the gate contact hole is a silicon oxide film and a silicon nitride film,
The method of manufacturing a semiconductor device according to claim 4, wherein the chemical dry etching is simultaneously performed on both the diffusion layer contact hole and the gate contact hole. The semiconductor device has a wiring formed on a semiconductor substrate, a first side wall made of a silicon nitride film on the side wall of the wiring, and an interlayer insulating film made of a silicon oxide film covering these,
The first contact hole is formed in the interlayer insulating film by exposing a first sidewall facing an adjacent wiring.
The method of manufacturing a semiconductor device according to claim 4, wherein a second contact hole having an inclination is formed in both the first sidewall and the interlayer insulating film by the chemical dry etching. The semiconductor device includes:
An active region extending in a first direction defined by an isolation region formed in the semiconductor substrate;
A word line extending in a second direction intersecting the first direction and embedded in the semiconductor substrate;
A bit line formed on the semiconductor substrate and extending in a third direction intersecting the first and second directions and connected to a part of the active region;
A capacitive contact plug connected to an active region adjacent to the active region connected to the bit line via the word line;
A capacitor connected to the capacitive contact plug;
The wiring formed on the semiconductor substrate is the bit line, the first contact hole is formed in an active region connecting the capacitor contact plug, and the capacitor is formed by embedding a conductor in the second contact hole. The method for manufacturing a semiconductor device according to claim 13, wherein a contact plug is formed. The semiconductor device has a wiring formed on a semiconductor substrate, a first side wall made of a silicon nitride film on the side wall of the wiring, and an interlayer insulating film made of a silicon oxide film covering these,
The first contact hole is formed in the interlayer insulating film with a groove extending in a direction intersecting the extending direction of the wiring, and nitrided on the groove and the first sidewall surface of the wiring exposed in the groove. By forming a second sidewall made of a silicon film, it is defined by an opposing second sidewall of adjacent wiring and an opposing second sidewall of the groove,
The method of manufacturing a semiconductor device according to claim 4, wherein a second contact hole having an inclination is formed in the second sidewall by the chemical dry etching. The semiconductor device includes:
An active region extending in a first direction defined by an isolation region formed in the semiconductor substrate;
A word line extending in a second direction intersecting the first direction and embedded in the semiconductor substrate;
A bit line formed on the semiconductor substrate and extending in a third direction intersecting the first and second directions and connected to a part of the active region;
A capacitive contact plug connected to an active region adjacent to the active region connected to the bit line via the word line;
A capacitor connected to the capacitive contact plug;
The active region shares the active region to which the bit line is connected in the center and is electrically connected in the first direction with two active regions facing each other through two adjacent word lines as one cell unit. Separated into
Forming an interlayer insulating film made of silicon oxide after forming the bit line protected by the first sidewall made of silicon nitride;
An active region to which two opposing capacitor contact plugs of two cell units adjacent in the first direction are connected is continuously exposed, extends in the second direction, and has a substantially vertical side wall. Forming a groove in the interlayer insulating film;
Forming a second sidewall made of silicon nitride on the sidewall of the groove and the sidewall of the first sidewall exposed in the groove;
Etching the second sidewall by the chemical dry etching to form a slope;
Burying a conductor film in a region defined by the groove and the bit line;
The method of manufacturing a semiconductor device according to claim 15, further comprising: forming two capacitive contact plugs by dividing the conductor film into two in the groove in the second direction.   The interlayer insulating film is formed so that the surface thereof is higher than the first sidewall surface of the bit line sidewall, and the conductor film is higher than the first sidewall surface and lower than the interlayer insulating film surface. After embedding, a third sidewall extending in the second direction with respect to the second sidewall of the groove sidewall is formed on the conductor film, and the conductor film is formed using the third sidewall as a mask. The method of manufacturing a semiconductor device according to claim 16.   18. The method of manufacturing a semiconductor device according to claim 17, wherein the capacitor contact plug is formed by embedding an insulating film between the bisected conductor films and planarizing the entire surface until the surface of the first sidewall is exposed. .