JPWO2006126536A1 - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

If a hard mask or cap insulating film is removed during wiring manufacture in a semiconductor device having a low dielectric constant interlayer insulating film, poor adhesion or defective attachment to the wiring interlayer insulating film occurs, resulting in poor wiring characteristics and reliability. A drop occurs. In order to solve this problem, in the present invention, the hard mask is removed, and a modified layer 314 having a uniform thickness different from the composition of the wiring interlayer insulating film 313 is formed on the exposed surface of the wiring interlayer insulating film 313. As a result, the adhesion with the via interlayer insulating film 318 formed thereon is improved, and etching penetration defects are suppressed. The modified layer 314 is formed by post-cleaning after Cu-CMP, vacuum plasma treatment or vacuum UV treatment before forming the upper via interlayer insulation film, etc. in a state where the wiring interlayer insulation film 314 is exposed after Cu-CMP. Can do.

Description

  The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a wiring structure of a semiconductor element, and more particularly, to a structure of a copper (Cu) wiring using a low dielectric constant film as a wiring interlayer insulating film.

  In recent years, there has been a demand for higher speed logic LSIs. The operation speed of a semiconductor device depends largely on the switching delay in a transistor and the propagation delay in a wiring. However, a logic LSI has a larger proportion of the wiring area than a memory, so that the speed of the logic LSI is increased. That is, in order to increase the operation speed, it is necessary to reduce the propagation delay in the wiring.

  The propagation delay in the wiring is proportional to the product of the wiring resistance and the wiring interlayer capacitance. For this reason, it is possible to reduce the propagation delay in the wiring by using a material having a low resistivity as the wiring material and using a material having a low relative dielectric constant as the wiring interlayer insulating film material.

  Therefore, at present, copper (Cu) or copper (Cu) alloys having a specific resistance lower than that of conventional aluminum (Al) or aluminum (Al) alloys are being studied as next-generation wiring materials.

  Wiring using copper or a copper alloy as a wiring material, that is, copper wiring is generally formed by a damascene method. This damascene method includes a step of depositing a wiring interlayer insulating film, a step of forming a groove from the surface side of the wiring interlayer insulating film by a reactive ion etching (RIE) method or the like, and a method of filling the groove. In this way, the copper or copper alloy film is deposited, and the copper or copper alloy film outside the trench is removed by chemical mechanical polishing (CMP) method, and the Cu wiring embedded in the wiring interlayer insulating film is removed. Forming a process.

In addition, silicon dioxide (SiO ₂ ) has been conventionally used as a low dielectric constant wiring interlayer insulating film material, but at present, the dielectric constant is lower than that of silicon dioxide (SiO ₂ ), and only from organic materials. Materials that are configured and materials in which an organic group is contained in a conventional silicon dioxide (SiO ₂ ) film have been studied.

For these low dielectric constant films, as shown in Patent Document 1 and Non-Patent Document 1, a film having a higher dielectric constant than a low dielectric constant film such as silicon dioxide (SiO ₂ ) called a hard mask. Has been deposited on the surface of the low dielectric constant film to reduce process damage to the low dielectric constant film during etching or Cu-CMP.

  On the other hand, as the generation progresses, the space between the wirings decreases, and in the region where the vias formed on the wirings are connected to the wirings, the wirings and the vias have the same dimensions so that they are connected within the same dimensions It has become.

  FIG. 35 is a cross-sectional view showing the positional relationship between the via and the wiring when alignment misalignment with the lower layer wiring occurs during the resist exposure of the via.

  As shown in FIG. 35, when alignment misalignment with the lower layer wiring occurs during the resist exposure of the via, the via 14 is removed from the lower layer wiring 15 by the via etching so as to bite into the wiring interlayer insulating film 11. It is formed.

  In such a case, by leaving the hard mask 12 on the low dielectric constant film even after Cu-CMP, the penetration of the via 14 into the wiring interlayer insulating film 11 is suppressed, and the wiring interlayer insulating film 11 is also removed. Can be prevented from being damaged.

  Furthermore, in the structure of the conventional copper (Cu) wiring, as shown in Non-Patent Document 1, as shown in FIG. 35, copper (Cu) at the time of forming a via interlayer film is formed on the copper (Cu) wiring. In many cases, there is an insulating film called a cap insulating film 13 for preventing the oxidation of Cu) wiring and serving as an etching stop film during via etching.

In Patent Documents 2, 3, and 4, surface treatment of the low dielectric constant film is performed before the hard mask (cap insulating film) of the semiconductor device is formed, that is, before the Cu-CMP process, and the layer surface is modified. Is disclosed.
JP2003-229482 (5th line of paragraph 0011, FIG. 2B) JP 2002-026121 A JP2003-017561 JP 2004-253790 A M.M. Tada et al., Proc. of IITC 2003, 20 June 2, 2003, page 256, FIG. 1

  As shown in Patent Document 1 and Non-Patent Document 1, in the case of a structure in which a hard mask is formed on the surface of a low dielectric constant film and the hard mask remains even after Cu-CMP, the structure is low. Since a film having a dielectric constant larger than that of the dielectric film remains between the wirings, the effective wiring capacity increases.

  Further, during Cu-CMP, the polishing speed varies depending on the width of the wiring pattern and the width of the space between the wirings. For this reason, the polishing amount of the hard mask varies depending on the density of the wiring pattern, and the thickness of the hard mask 31 remaining after Cu-CMP is not uniform. That is, as shown in FIG. This causes the problem that the thicknesses of the two are different. As a result, the estimated amount of inter-wiring capacitance cannot be determined only by the space between the wirings due to the difference in the wiring pattern.

  Note that the hard mask can be removed during Cu-CMP by changing the slurry used during Cu-CMP to a material that does not easily damage the low dielectric constant film.

  On the other hand, since the cap insulating film formed on the copper (Cu) wiring shown in Non-Patent Document 1 is composed of a material having a dielectric constant larger than that of the low dielectric constant material, by removing this cap insulating film, It becomes possible to reduce the capacitance between wirings.

  However, when a low dielectric constant interlayer insulating film containing oxygen is formed on the copper (Cu) wiring, the surface of the copper (Cu) wiring is oxidized by the oxygen, resulting in deterioration of wiring characteristics.

  In recent years, a metal cap metal film made of cobalt tungsten phosphorus (CoWP) or cobalt tungsten boron (CoWB) is selectively formed on the copper (Cu) wiring in order to prevent oxidation of the copper (Cu) wiring surface. As a result, a low dielectric constant interlayer insulating film containing oxygen can be formed on the copper (Cu) wiring.

  As described above, the hard mask and the cap insulating film can be removed, and the capacitance between wirings can be reduced. On the other hand, the low dielectric constant film is exposed after Cu-CMP. In some cases, the low dielectric constant film as the wiring interlayer insulating film and the low dielectric constant film as the via interlayer insulating film are in direct contact with each other.

  In this case, if an alignment misalignment with the lower layer wiring occurs during the exposure patterning of the via, the via hole is formed in a state where the lower layer wiring is stepped off during the via etching, so that the via bites into the wiring interlayer insulating film.

  There is a film with a composition different from that of a low dielectric constant film such as a hard mask and a high density, or there is a film that temporarily stops etching such as a cap insulating film. In this case, as shown in FIG. 35, the amount of etching bite is small.

  On the other hand, when there is no hard mask or cap insulating film, the amount of bite increases because the bite during etching occurs in the low dielectric constant film 21 with low density. As a result, as shown in FIG. 36, microvoids 22 may be generated during the formation of copper (Cu), which in turn may cause deterioration of wiring characteristics.

  Further, in the techniques disclosed in Patent Documents 2, 3, and 4, when the low dielectric constant film is exposed on the surface of the wiring interlayer insulating film, the low dielectric constant is caused by the dependency of the polishing rate on the wiring pattern in the Cu-CMP process. The film thickness of the modified layer formed on the surface of the rate film changes. That is, the film thickness of the modified layer varies depending on the position, like the hard mask 31 shown in FIG.

  The present invention has been made to solve the above-described problems in the prior art, and an object thereof is to provide a semiconductor device having high performance and high reliability and a method for manufacturing the same. .

  In order to achieve the above object, the present invention provides a semiconductor substrate, a plurality of copper wiring layers formed on the semiconductor substrate, and a copper via interconnecting an upper copper wiring layer and a lower copper wiring layer. A wiring interlayer insulating film for insulating and separating the copper wiring layer from each other; and a via interlayer insulating film for insulating and separating the copper via layer from each other. Provided is a semiconductor device comprising a modified layer having a uniform thickness formed on at least the surface of the wiring interlayer insulating film among the insulating films.

  The modified layer preferably changes in composition toward the inside of the wiring interlayer insulating film.

  The semiconductor device preferably further includes a cap metal film formed on the copper wiring layer in order to prevent oxidation of copper contained in the copper wiring layer.

  In the semiconductor device, it is preferable that the via interlayer insulating film is directly formed on the cap metal film and the wiring interlayer insulating film.

  The semiconductor device preferably further includes a cap insulating film formed on the modified layer and the copper wiring layer.

  The present invention further includes a semiconductor substrate, a plurality of copper wiring layers formed on the semiconductor substrate, a copper via layer interconnecting an upper copper wiring layer and a lower copper wiring layer, and the copper wiring. In a method of manufacturing a semiconductor device comprising a wiring interlayer insulating film for insulating and separating layers from each other and a via interlayer insulating film for insulating and separating the copper via layer from each other, the copper wiring layer is embedded in the wiring interlayer insulating film Thereafter, a method of manufacturing a semiconductor device is provided, comprising a step of subjecting the wiring interlayer insulating film to a vacuum surface treatment and selectively modifying the surface layer of the wiring interlayer insulating film.

  As the vacuum surface treatment, for example, a vacuum plasma treatment or a vacuum UV treatment can be selected.

  The method preferably further includes a step of forming a cap metal film on the copper wiring layer in order to prevent oxidation of copper contained in the copper wiring layer.

  The method preferably further includes a step of directly forming the via interlayer insulating film on the cap metal film and the wiring interlayer insulating film.

  Preferably, the method further includes a step of forming a cap insulating film on the modified layer and the copper wiring layer.

  According to the present invention, when the hard mask is completely removed during Cu-CMP and the wiring interlayer insulating film (low dielectric constant film) is exposed, before the cap insulating film formed on the wiring interlayer insulating film is formed. By reforming only the outermost surface of the wiring interlayer insulation film, the modification has good adhesion to the cap insulation film and can suppress penetration into the wiring interlayer insulation film during via etching. A layer is formed. As shown in FIG. 1 (the modified layer is indicated by reference numeral 41 in FIG. 1), the modified layer has a uniform film thickness over the wafer surface.

  In the conventional example, as shown in FIG. 37, the film thickness of the modified layer may differ depending on the dependency of the polishing rate on the wiring pattern in the Cu-CMP process. On the other hand, according to the present invention, it is possible to form a modified layer having a uniform film thickness over the wafer surface.

  In addition, according to the present invention, when all of the hard mask is removed during Cu-CMP and the wiring interlayer insulating film (low dielectric constant film) is exposed, copper oxidation is suppressed on the surface of the copper wiring layer after Cu-CMP. When forming a low dielectric constant film to be a wiring interlayer insulating film directly without forming a cap insulating film thereon, a metal cap film that can be formed is formed. Before the film, only the outermost surface of the wiring interlayer insulating film is uniformly modified. As a result, a modified layer having a uniform film thickness is formed over the entire wafer surface, which suppresses penetration into the wiring interlayer insulating film during via etching.

  In the conventional example, as shown in FIG. 37, the film thickness of the modified layer may differ depending on the dependency of the polishing rate on the wiring pattern in the Cu-CMP process. On the other hand, according to the present invention, it is possible to form a modified layer having a uniform film thickness over the wafer surface.

  According to the present invention, it is possible to reduce the capacitance between wirings by removing one or both of the hard mask and the cap insulating film in the wiring interlayer insulating film of the semiconductor device.

  Furthermore, it is possible to make etching through the wiring interlayer insulating film when the misalignment occurs in the via alignment to the same level as when the hard mask and cap insulating film exist. Therefore, it is possible to obtain wiring characteristics and reliability equivalent to or higher than those of the conventional structure while reducing the capacitance between the wirings.

  As described above, the present invention provides a high-performance and highly reliable semiconductor device and a method for manufacturing the same.

It is sectional drawing of the semiconductor device in which the modified layer in this invention was formed. 1 is a cross-sectional view of a semiconductor device according to a first embodiment of the present invention. It is sectional drawing of the semiconductor device which concerns on 2nd embodiment of this invention. It is sectional drawing of the semiconductor device which concerns on the 1st Example of the semiconductor device which concerns on 1st embodiment of this invention. It is a figure which shows the condition where the composition of the modified layer formed in the outermost surface of a wiring interlayer insulation film changes in steps. It is a figure which shows the condition where the composition of the modified layer formed in the outermost surface of a wiring interlayer insulation film changes in steps. It is a figure which shows the condition where the composition of the modified layer formed in the outermost surface of a wiring interlayer insulation film changes in steps. It is sectional drawing of the semiconductor device which concerns on the 2nd Example of the semiconductor device which concerns on 1st embodiment of this invention. It is sectional drawing of the semiconductor device which concerns on the Example of the semiconductor device which concerns on 2nd embodiment of this invention. It is sectional drawing of the semiconductor device in each process of the manufacturing method of the semiconductor device which concerns on a 1st Example. It is sectional drawing of the semiconductor device in each process of the manufacturing method of the semiconductor device which concerns on a 1st Example. It is sectional drawing of the semiconductor device in each process of the manufacturing method of the semiconductor device which concerns on a 1st Example. It is sectional drawing of the semiconductor device in each process of the manufacturing method of the semiconductor device which concerns on a 1st Example. It is sectional drawing of the semiconductor device in each process of the manufacturing method of the semiconductor device which concerns on a 1st Example. It is sectional drawing of the semiconductor device in each process of the manufacturing method of the semiconductor device which concerns on a 1st Example. It is sectional drawing of the semiconductor device in each process of the manufacturing method of the semiconductor device which concerns on a 1st Example. It is sectional drawing of the semiconductor device in each process of the manufacturing method of the semiconductor device which concerns on a 1st Example. It is sectional drawing of the semiconductor device in each process of the manufacturing method of the semiconductor device which concerns on a 1st Example. It is sectional drawing of the semiconductor device in each process of the manufacturing method of the semiconductor device which concerns on a 1st Example. It is sectional drawing of the semiconductor device in each process of the manufacturing method of the semiconductor device which concerns on a 1st Example. It is sectional drawing of the semiconductor device in each process of the manufacturing method of the semiconductor device which concerns on a 2nd Example. It is sectional drawing of the semiconductor device in each process of the manufacturing method of the semiconductor device which concerns on a 2nd Example. It is sectional drawing of the semiconductor device in each process of the manufacturing method of the semiconductor device which concerns on a 2nd Example. It is sectional drawing of the semiconductor device in each process of the manufacturing method of the semiconductor device which concerns on a 2nd Example. It is sectional drawing of the semiconductor device in each process of the manufacturing method of the semiconductor device which concerns on a 2nd Example. It is sectional drawing of the semiconductor device in each process of the manufacturing method of the semiconductor device which concerns on a 2nd Example. It is sectional drawing of the semiconductor device in each process of the manufacturing method of the semiconductor device which concerns on a 2nd Example. It is sectional drawing of the semiconductor device in each process of the manufacturing method of the semiconductor device which concerns on a 2nd Example. It is sectional drawing of the semiconductor device which concerns on a 2nd Example in the case of not forming a cap insulating film. It is sectional drawing of the semiconductor device in each process of the manufacturing method of the semiconductor device which concerns on a 2nd Example. It is sectional drawing of the semiconductor device in each process of the manufacturing method of the semiconductor device which concerns on a 2nd Example. It is sectional drawing of the semiconductor device in each process of the manufacturing method of the semiconductor device which concerns on a 2nd Example. It is sectional drawing of the semiconductor device in each process of the manufacturing method of the semiconductor device which concerns on a 2nd Example. It is sectional drawing of the semiconductor device in each process of the manufacturing method of the semiconductor device which concerns on a 2nd Example. It is sectional drawing of the semiconductor device of a prior art example. It is sectional drawing of the semiconductor device of a prior art example. It is sectional drawing of the semiconductor device of a prior art example.

Explanation of symbols

1001, 1021 Substrate 1002, 1022 Insulating film 1003, 1023 Wiring interlayer insulating film 1004, 1024 Conductive metal wiring (copper wiring layer)
1005, 1025 Modified layer 1006, 1026 Cap insulating film 1007, 1027 Via interlayer insulating film 1008, 1028 Conductive metal via (copper via layer)
1009, 1029 Wiring interlayer insulating films 1010, 1030 Modified layers 1011 and 1031 Conductive metal wiring (copper wiring layer)
111, 211, 311 Substrate 112, 212, 312 Insulating film 113, 213, 313 Wiring interlayer insulating film 114, 214, 314 Modified layer 115, 215, 315 Conductive metal wiring (copper wiring layer)
116, 217 Cap insulating film 117, 218, 318 Via interlayer insulating film 118, 219, 319 Wiring interlayer insulating film 119, 220, 320 Modified layer 120, 221 and 321 Conductive metal wiring (copper wiring layer)
121, 222, 322 Conductive metal via (copper via layer)
216, 316 Cap metal film 411, 511 Substrate 412, 512 Insulating film 413, 513 Wiring interlayer insulating film 414, 514 Wiring groove 415, 515 Wiring metal film 416, 516 Conductive metal wiring (copper wiring layer)
417, 518 Surface treatment 418, 519 Modified layer 419, 520 Cap insulating film 420, 521 Via interlayer insulating film 421, 522 Wiring interlayer insulating film 422, 523 Via etching hole 423, 524 Wiring etching groove 424, 525 Wiring metal film 425 527 Conductive metal via (copper via layer)
426, 526 Conductive metal wiring (copper wiring layer)
427, 529 Surface treatment 428, 530 Modified layer 517, 528 Cap metal film

  FIG. 2 is a cross-sectional view of the semiconductor device according to the first embodiment of the present invention.

  A semiconductor device 1000 according to the first embodiment of the present invention includes a semiconductor substrate 1001, an insulating film 1002 formed on the semiconductor substrate 1001, a wiring interlayer insulating film 1003 formed on the insulating film 1002, and a wiring interlayer. By modifying the surface of the insulating film 1003, a modified layer 1005 formed on the surface of the wiring interlayer insulating film 1003, having a film composition different from that of the wiring interlayer insulating film 1003 and having a uniform film thickness, and wiring A conductive metal wiring 1004 formed over the entire length in the thickness direction inside the interlayer insulating film 1003 and the modified layer 1005, and a cap insulating film 1006 formed on the conductive metal wiring 1004 and the modified layer 1005 The via interlayer insulating film 1007 formed on the cap insulating film 1006 and the entire length in the thickness direction within the via interlayer insulating film 1007. Thus, a conductive metal via 1008 formed so as to be connected to the conductive metal wiring 1004, a wiring interlayer insulating film 1007 formed on the via interlayer insulating film 1007 and the conductive metal via 1008, and a wiring interlayer insulating film By reforming the surface of 1009, a modified layer 1010 formed on the surface of the wiring interlayer insulating film 1009, having a film composition different from the wiring interlayer insulating film 1009 and having a uniform film thickness, and a wiring interlayer insulating film A conductive metal wiring 1011 formed so as to be connected to the conductive metal via 1008 over the entire length in the thickness direction inside the film 1009 and the modified layer 1010.

  The conductive metal wirings 1004 and 1011 are made of copper or a copper alloy. Similarly, the conductive metal via 1008 that connects the conductive metal wiring 1004 and the conductive metal wiring 1011 is also made of copper or a copper alloy.

  As described above, the semiconductor device 1000 according to this embodiment includes the conductive metal wirings 1004 and 1011 made of a plurality of copper and the conductive metal vias 1008 connecting the conductive metal wirings 1004 and 1011 on the semiconductor substrate 1001. A multi-layer wiring consisting of

  The conductive metal wirings 1004 and 1011 are insulated and separated by low dielectric constant wiring interlayer insulation films 1003 and 1009, and the conductive metal via 1008 is insulated and separated by a via interlayer insulation film. Further, modified layers 1005 and 1010 having a uniform film thickness are formed on the surfaces of the wiring interlayer insulating films 1003 and 1009.

  The layer thickness and film thickness of each layer and each film are set in the same range as those conventionally known, and the sizes of the conductive metal wirings 1004 and 1011 and the conductive metal via 1008 are the same as those in the conventionally known semiconductor device. Set by range. A conventionally known method can be applied to a method for forming each layer or each film that is not described later.

  FIG. 3 is a cross-sectional view of a semiconductor device according to the second embodiment of the present invention.

  A semiconductor device 1500 according to the second embodiment of the present invention includes a semiconductor substrate 1021, an insulating film 1022 formed on the semiconductor substrate 1021, a wiring interlayer insulating film 1023 formed on the insulating film 1022, and a wiring interlayer. By modifying the surface of the insulating film 1023, a modified layer 1025 formed on the surface of the wiring interlayer insulating film 1023, having a film composition different from that of the wiring interlayer insulating film 1023 and having a uniform film thickness, and wiring Conductive metal wiring 1024 formed over the entire length in the thickness direction inside the interlayer insulating film 1023 and the modified layer 1025, a cap metal film 1026 formed on the conductive metal wiring 1024, and the modified layer 1025 Via interlayer insulating film 1027 formed thereon, and conductive metal wiring 10 over the entire length in the thickness direction inside via interlayer insulating film 1027 The conductive metal via 1028 formed so as to be connected to the wiring 4, the wiring interlayer insulating film 1027 formed on the via interlayer insulating film 1027 and the conductive metal via 1028, and the surface of the wiring interlayer insulating film 1029 are modified. Thus, a modified layer 1030 is formed on the surface of the wiring interlayer insulating film 1029 and has a film composition different from that of the wiring interlayer insulating film 1029 and has a uniform film thickness, and the wiring interlayer insulating film 1029 and the modified layer 1030. The conductive metal wiring 1031 is formed so as to be connected to the conductive metal via 1028 over the entire length in the thickness direction.

  The conductive metal wirings 1024 and 1031 are made of copper or a copper alloy. Similarly, the conductive metal via 1028 that connects the conductive metal wiring 1024 and the conductive metal wiring 1031 is also made of copper or a copper alloy.

  Compared to the semiconductor device 1000 according to the first embodiment (FIG. 2), the semiconductor device 1500 according to the second embodiment has a conductive metal in order to prevent oxidation of copper contained in the conductive metal wiring 1024. A cap metal film 1026 is further provided over the wiring 1024, but an insulating film corresponding to the cap insulating film 1006 formed over the conductive metal wiring 1004 and the modified layer 1005 is not provided.

  The method for manufacturing the semiconductor device 1000 according to the first embodiment shown in FIG. 2 includes a first step of forming the insulating film 1002 on the semiconductor substrate 1001, and a wiring layer on the insulating film 1002 formed in the first step. A second step of forming the insulating film 1003, and a third step of forming the conductive metal wiring 1004 over the entire length in the thickness direction of the wiring interlayer insulating film 1003 inside the wiring interlayer insulating film 1003 formed in the second step; After the conductive metal wiring 1004 is formed, the surface of the wiring interlayer insulating film 1003 is modified, so that the film composition differs from that of the wiring interlayer insulating film 1003 on the surface of the wiring interlayer insulating film 1003. A fourth step of forming a modified layer 1005 having a uniform thickness; a fifth step of forming a via interlayer insulating film 1007 on the conductive metal wiring 1004 and the modified layer 1005; A sixth step of forming the conductive metal via 1008 so as to be connected to the conductive metal wiring 1004 over the entire length in the thickness direction inside the via interlayer insulating film 1007, and the via interlayer insulating film 1007 and the conductive metal via 1008. A seventh step of forming a wiring interlayer insulating film 1009 thereon, and a conductive metal wiring 1011 for connecting to the conductive metal via 1008 over the entire length in the thickness direction inside the wiring interlayer insulating film 1009 After the formation of the conductive metal wiring 1011 in the eight steps, the surface of the wiring interlayer insulating film 1009 is modified so that the film composition differs from that of the wiring interlayer insulating film 1009 on the surface of the wiring interlayer insulating film 1009. And a ninth step of forming the modified layer 1010 having a uniform film thickness.

  The surface modification of the wiring interlayer insulating films 1003 and 1009 is performed by subjecting the surfaces of the wiring interlayer insulating films 1003 and 1009 to vacuum surface treatment. For example, vacuum plasma treatment or vacuum UV treatment can be selected as the vacuum surface treatment.

  The method for manufacturing the semiconductor device 1500 according to the second embodiment shown in FIG. 3 includes a first step of forming the insulating film 1022 on the semiconductor substrate 1021 and a wiring layer on the insulating film 1022 formed in the first step. A second step of forming the insulating film 1023, and a third step of forming the conductive metal wiring 1024 over the entire length in the thickness direction of the wiring interlayer insulating film 1023 inside the wiring interlayer insulating film 1023 formed in the second process; The fourth step of forming the cap metal film 1026 on the conductive metal wiring 1024, and after the formation of the cap metal film 1026, the surface of the wiring interlayer insulating film 1023 is modified to thereby form the wiring interlayer insulating film 1023. A fifth step of forming a modified layer 1025 having a film composition different from that of the wiring interlayer insulating film 1023 and having a uniform film thickness on the surface; and a conductive metal wiring 024 and the sixth step of forming the via interlayer insulating film 1027 on the modified layer 1025, and the conductive metal so as to be connected to the conductive metal wiring 1024 over the entire length in the thickness direction inside the via interlayer insulating film 1027 A seventh step of forming the via 1028; an eighth step of forming the wiring interlayer insulating film 1029 on the via interlayer insulating film 1027 and the conductive metal via 1028; and a total length in the thickness direction inside the wiring interlayer insulating film 1029. Over the ninth step of forming the conductive metal wiring 1031 so as to be connected to the conductive metal via 1028, and after the conductive metal wiring 1031 is formed, the surface of the wiring interlayer insulating film 1029 is modified, On the surface of the wiring interlayer insulating film 1029, a modified layer 1030 having a film composition different from that of the wiring interlayer insulating film 1029 and having a uniform film thickness is formed. And a tenth step that consists of.

  Compared with the manufacturing method of the semiconductor device 1000 according to the first embodiment, the manufacturing method of the semiconductor device 1500 according to the second embodiment is performed in order to prevent oxidation of copper contained in the conductive metal wiring 1024. A step of manufacturing a cap metal film 1026 on the conductive metal wiring 1024 is additionally provided.

  FIG. 4 is a cross-sectional view of the semiconductor device 100 according to the first example of the semiconductor device 1000 according to the first embodiment of the present invention described above. The semiconductor device 100 according to the first embodiment will be described below with reference to FIG.

  The semiconductor device 100 according to the first embodiment includes a semiconductor substrate 111, an insulating film 112 formed on the semiconductor substrate 111, a wiring interlayer insulating film 113 formed on the insulating film 112, and a wiring interlayer insulating film 113. By modifying the surface of the wiring interlayer insulating film 113, a modified layer 114 having a film composition different from that of the wiring interlayer insulating film 113 and having a uniform thickness, and a wiring interlayer insulating film are formed. 113 and the modified layer 114, the conductive metal wiring 115 formed over the entire length in the thickness direction, the cap insulating film 116 formed on the conductive metal wiring 115 and the modified layer 114, and the cap insulation The via interlayer insulating film 117 formed on the film 116 and the via interlayer insulating film 117 are formed so as to be connected to the conductive metal wiring 115 over the entire length in the thickness direction. By modifying the surface of the conductive metal via 121, the wiring interlayer insulating film 117, the wiring interlayer insulating film 118 formed on the conductive metal via 121, and the wiring interlayer insulating film 118, the wiring interlayer insulating film The modified layer 119 is formed on the surface of the wiring 118 and has a film composition different from that of the wiring interlayer insulating film 118 and has a uniform film thickness, and the thickness of the modified layer 119 inside the wiring interlayer insulating film 118 and the modified layer 119. The conductive metal wiring 120 is formed so as to be connected to the conductive metal via 121 over the entire length in the direction.

  As the semiconductor substrate 111, for example, a single crystal silicon substrate can be used.

The insulating film 112 is formed of, for example, borophosphosilicate glass (BPSG), phosphosilicate glass (PSG), silicon oxide (SiO ₂ ), silicon nitride (SiN), or silicon oxynitride. (SiON), silicon oxyfluoride (SiOF), silicon carbide (SiC), silicon carbonitride (SiCN), or a combination thereof.

  The wiring interlayer insulating film 113 is made of, for example, an organic polymer of a low dielectric constant material, MSQ, HSQ, or a carbon-containing silicon oxide film.

  The composition of the modified layer 114 is determined according to the composition of the wiring interlayer insulating film 113.

For example, when the wiring interlayer insulating film 113 is a carbon-containing silicon oxide film (SiO _1.6 C _0.4 H), the modified layer 114 is SiO ₂ or SiO _1.9 C _0.1 .

The modified layer 114 can also be composed of SiO _1.8 C _0.1 N _0.1 .

  Further, since the modified layer 114 is a film formed by modifying the wiring interlayer insulating film 113, the composition changes stepwise from the surface of the wiring interlayer insulating film 113 toward the inside of the wiring interlayer insulating film 113. Sometimes it is.

For example, when the wiring interlayer insulating film 113 is a carbon-containing silicon oxide film SiO _1.6 C _0.4 , the modified layer 114 is made of SiO _1.9 C _{0.1 on} the outermost surface of the modified layer 114. As shown in FIG. 5, the concentration of oxygen (O) and carbon (C) may change step by step as the wiring interlayer insulating film 113 is formed.

  As described above, the film thickness of the modified layer 114 is uniform. For example, the film thickness of the modified layer 114 is uniform between 50 angstroms and 200 angstroms in the wafer surface.

  The conductive metal wiring 115 and the conductive metal via 121 are made of copper or a copper alloy.

  The cap insulating film 116 formed on the conductive metal wiring 115 serves to prevent oxidation of the conductive metal wiring 115 and to serve as a stopper during etching for forming a via hole. The cap insulating film 116 is made of, for example, silicon carbide (SiC), silicon carbonitride (SiCN), or silicon nitride (SiN).

For example, when the wiring interlayer insulating film 113 is made of SiO _1.6 C _0.4 and the cap insulating film 116 is made of silicon carbonitride (SiCN), the modified layer 114 is as shown in FIG. In addition, the concentration of nitrogen (N) increases stepwise as it approaches the cap insulating film 116 (SiCN), and nitrogen (stepwise) as it approaches the wiring interlayer insulating film 113 (SiO _1.6 C _0.4 ). N) concentration decreases. As described above, the composition of the modified layer 114 changes stepwise toward the upper and lower films in accordance with the compositions of the upper and lower films of the modified layer 114, that is, the wiring interlayer insulating film 113 and the cap insulating film 116. There is also.

  The via interlayer insulating film 117 is made of, for example, an organic polymer of a low dielectric constant material, MSQ, HSQ, or a carbon-containing silicon oxide film.

  The wiring interlayer insulating film 118 is made of, for example, an organic polymer of a low dielectric constant material, MSQ, HSQ, or a carbon-containing silicon oxide film.

  On the outermost surface of the wiring interlayer insulating film 118, a modified layer 119 having an element composition different from that of the wiring interlayer insulating film 118 is formed with a uniform film thickness over the wafer surface.

For example, when the wiring interlayer insulating film 118 is made of a carbon-containing silicon oxide film (SiO _1.6 C _0.4 H), the modified layer 119 is made of SiO ₂ or SiO _1.9 C _0.1. Become.

The modified layer 119 can also be composed of SiO _1.8 C _0.1 N _0.1 .

  Further, since the modified layer 119 is a film formed by modifying the wiring interlayer insulating film 118, the composition changes stepwise from the surface of the wiring interlayer insulating film 118 toward the inside of the wiring interlayer insulating film 118. Sometimes it is.

For example, when the wiring interlayer insulating film 118 is a carbon-containing silicon oxide film SiO _1.6 C _0.4 , the modified layer 119 is made of SiO _1.9 C _{0.1 on} the outermost surface of the modified layer 119, As shown in FIG. 5, the concentration of oxygen (O) and carbon (C) may change step by step as the wiring interlayer insulating film 118 is formed.

  As described above, the film thickness of the modified layer 119 is uniform. For example, the film thickness of the modified layer 119 is uniform between 50 angstroms and 200 angstroms in the wafer surface.

  As shown in FIG. 4, the semiconductor device 100 according to the first embodiment is configured to have two layers of conductive metal wiring, but the manufacturing process of the conductive metal wiring and the wiring interlayer insulating film is repeated. Therefore, it is possible to configure as a multilayer wiring structure having three or more layers.

  Alternatively, a wiring interlayer insulating film (not shown) of a type different from the wiring interlayer insulating film 118 can be formed on the multilayer wiring structure, and a conductive metal wiring can be formed therein.

  The semiconductor device 100 according to the first embodiment is manufactured by a dual damascene process in which the conductive metal via 121 and the conductive metal wiring 120 are simultaneously formed. It is also possible to manufacture by a single damascene process in which 120 is formed separately.

  FIG. 8 is a cross-sectional view of the semiconductor device 200 according to the second example of the semiconductor device 1000 according to the first embodiment of the present invention described above. The semiconductor device 200 according to the second embodiment will be described below with reference to FIG.

  The semiconductor device 200 according to the second embodiment includes a semiconductor substrate 211, an insulating film 212 formed on the semiconductor substrate 211, a wiring interlayer insulating film 213 formed on the insulating film 212, and a wiring interlayer insulating film 213. By modifying the surface of the wiring interlayer insulating film 213, a modified layer 214 having a film composition different from that of the wiring interlayer insulating film 213 and having a uniform film thickness, and a wiring interlayer insulating film are formed. The conductive metal wiring 215 formed over the entire length in the thickness direction inside the 213 and the modified layer 214, the cap metal film 216 formed on the conductive metal wiring 215, the cap metal film 216, and the modified metal The cap insulating film 217 formed on the layer 214, the via interlayer insulating film 218 formed on the cap insulating film 217, and the thickness direction inside the via interlayer insulating film 218 A conductive metal via 222 formed so as to be connected to the conductive metal wiring 215 over the entire length, a wiring interlayer insulating film 218 formed on the via interlayer insulating film 218 and the conductive metal via 222, and a wiring interlayer insulating film By modifying the surface of 219, a modified layer 220 is formed on the surface of the wiring interlayer insulating film 219, which has a film composition different from that of the wiring interlayer insulating film 219 and has a uniform film thickness. The conductive metal wiring 221 is formed so as to be connected to the conductive metal via 222 over the entire length in the thickness direction inside the film 219 and the modified layer 220.

  Compared with the semiconductor device 100 according to the first embodiment shown in FIG. 4, the semiconductor device 200 according to the second embodiment additionally includes a cap metal film 216 formed on the conductive metal wiring 215. I have.

  As the semiconductor substrate 211, for example, a single crystal silicon substrate can be used.

The insulating film 212 is formed of, for example, borophosphosilicate glass (BPSG), phosphosilicate glass (PSG), silicon oxide (SiO ₂ ), silicon nitride (SiN), or silicon oxynitride. (SiON), silicon oxyfluoride (SiOF), silicon carbide (SiC), silicon carbonitride (SiCN), or a combination thereof.

  The wiring interlayer insulating film 213 is made of, for example, an organic polymer of a low dielectric constant material, MSQ, HSQ, or a carbon-containing silicon oxide film.

  The composition of the modified layer 214 is determined according to the composition of the wiring interlayer insulating film 213.

For example, when the wiring interlayer insulating film 213 is a carbon-containing silicon oxide film (SiO _1.6 C _0.4 H), the modified layer 214 is SiO ₂ or SiO _1.9 C _0.1 .

The modified layer 214 can also be composed of SiO _1.8 C _0.1 N _0.1 .

  Further, since the modified layer 214 is a film formed by modifying the wiring interlayer insulating film 213, the composition changes stepwise from the surface of the wiring interlayer insulating film 213 toward the inside of the wiring interlayer insulating film 213. Sometimes it is.

For example, when the wiring interlayer insulating film 213 is a carbon-containing silicon oxide film SiO _1.6 C _0.4 , the modified layer 214 is made of SiO _1.9 C _{0.1 on} the outermost surface of the modified layer 214, As shown in FIG. 5, the concentration of oxygen (O) and carbon (C) may change step by step as the wiring interlayer insulating film 213 is located.

  As described above, the film thickness of the modified layer 214 is uniform. For example, the thickness of the modified layer 214 is uniform between 50 angstroms and 200 angstroms in the wafer surface.

  The conductive metal wiring 215 and the conductive metal via 222 are made of copper or a copper alloy.

  The cap metal film 216 formed on the conductive metal wiring 215 prevents oxidation of copper contained in the conductive metal wiring 215.

  The cap metal film 216 is made of a non-oxidizing metal such as cobalt tungsten phosphorus or cobalt tungsten boron, for example.

  The cap insulating film 217 formed on the cap metal film 216 and the modified layer 214 serves as a stopper at the time of etching for forming a via hole. The cap insulating film 217 is made of, for example, silicon carbide (SiC), silicon carbonitride (SiCN), or silicon nitride (SiN).

In the case where the cap metal film 216 is a film made of a non-oxidizing material, the cap insulating film 217 can be made of an oxide such as silicon oxide (SiO ₂ ).

For example, when the wiring interlayer insulating film 213 is made of SiO _1.6 C _0.4 and the cap insulating film 217 is made of silicon carbonitride (SiCN), the modified layer 214 is formed as shown in FIG. In addition, the concentration of nitrogen (N) increases step by step as the cap insulating film 217 (SiCN) is approached, and nitrogen (N) increases step by step as the wiring interlayer insulating film 213 (SiO _1.6 C _0.4 ) is approached. N) concentration decreases. As described above, the composition of the modified layer 214 changes stepwise toward the upper and lower films according to the upper and lower films of the modified layer 214, that is, the compositions of the wiring interlayer insulating film 213 and the cap insulating film 217. There is also.

  The via interlayer insulating film 218 is made of, for example, an organic polymer of a low dielectric constant material, MSQ, HSQ, or a carbon-containing silicon oxide film.

  The wiring interlayer insulating film 219 is made of, for example, a low dielectric constant material organic polymer, MSQ, HSQ, or a carbon-containing silicon oxide film.

  On the outermost surface of the wiring interlayer insulating film 219, a modified layer 220 having an element composition different from that of the wiring interlayer insulating film 219 is formed with a uniform film thickness over the wafer surface.

For example, when the wiring interlayer insulating film 219 is made of a carbon-containing silicon oxide film (SiO _1.6 C _0.4 H), the modified layer 220 is made of SiO ₂ or SiO _1.9 C _0.1. Become.

Further, the modified layer 220 may be composed of _SiO 1.8 _{C 0.1 N} 0.1.

  Further, since the modified layer 220 is a film formed by modifying the wiring interlayer insulating film 219, the composition changes stepwise from the surface of the wiring interlayer insulating film 219 toward the inside of the wiring interlayer insulating film 219. Sometimes it is.

For example, when the wiring interlayer insulating film 219 is a carbon-containing silicon oxide film SiO _1.6 C _0.4 , the modified layer 220 is made of SiO _1.9 C _{0.1 on} the outermost surface of the modified layer 220. As shown in FIG. 5, the concentration of oxygen (O) and carbon (C) may change step by step as the wiring interlayer insulating film 219 is formed.

  As described above, the film thickness of the modified layer 220 is uniform. For example, the film thickness of the modified layer 220 is uniform between 50 angstroms and 200 angstroms in the wafer surface.

  As shown in FIG. 8, the semiconductor device 200 according to the second embodiment is configured to have two layers of conductive metal wiring, but the manufacturing process of the conductive metal wiring and the wiring interlayer insulating film is repeated. Therefore, it is possible to configure as a multilayer wiring structure having three or more layers.

  Alternatively, it is possible to form a wiring interlayer insulating film (not shown) of a type different from the wiring interlayer insulating film 219 on the multilayer wiring structure, and to form a conductive metal wiring therein.

  The semiconductor device 200 according to the second embodiment is manufactured by a dual damascene process in which the conductive metal via 222 and the conductive metal wiring 221 are simultaneously formed. It is also possible to manufacture by a single damascene process in which 221 is formed separately.

  FIG. 9 is a cross-sectional view of a semiconductor device 300 according to an example of the semiconductor device 1500 according to the second embodiment of the present invention described above. Hereinafter, with reference to FIG. 9, a semiconductor device 300 according to an example of the semiconductor device 1500 according to the second embodiment will be described as a semiconductor device according to a third example.

  A semiconductor device 300 according to the third embodiment includes a semiconductor substrate 311, an insulating film 312 formed on the semiconductor substrate 311, a wiring interlayer insulating film 313 formed on the insulating film 312, and a wiring interlayer insulating film 313. By reforming the surface of the wiring interlayer insulating film 313, a modified layer 314 having a film composition different from that of the wiring interlayer insulating film 313 and having a uniform thickness, and a wiring interlayer insulating film are formed. The conductive metal wiring 315 formed over the entire length in the thickness direction inside the 313 and the modified layer 314, the cap metal film 316 formed on the conductive metal wiring 315, the modified layer 314 and the cap metal The via interlayer insulating film 318 formed on the film 316 and the via interlayer insulating film 318 are formed so as to be connected to the conductive metal wiring 315 over the entire length in the thickness direction. By modifying the surface of the conductive metal via 322, the wiring interlayer insulating film 318 and the wiring interlayer insulating film 319 formed on the conductive metal via 322, the wiring interlayer insulating film The modified layer 320 is formed on the surface of 319 and has a film composition different from that of the wiring interlayer insulating film 319 and has a uniform film thickness, and the thickness of the modified layer 320 inside the wiring interlayer insulating film 319 and the modified layer 320. The conductive metal wiring 321 is formed so as to be connected to the conductive metal via 322 over the entire length in the direction.

  The conductive metal wirings 315 and 321 are made of copper or a copper alloy. Similarly, the conductive metal via 322 connecting the conductive metal wiring 315 and the conductive metal wiring 321 is also made of copper or a copper alloy.

  Compared to the semiconductor device 200 according to the second embodiment (FIG. 8), the semiconductor device 300 according to the third embodiment has a cap insulating film 217 formed on the cap metal film 216 and the modified layer 214. It does not have a corresponding insulating film.

  As the semiconductor substrate 311, for example, a single crystal silicon substrate can be used.

The insulating film 312 is formed of, for example, borophosphosilicate glass (BPSG), phosphosilicate glass (PSG), silicon oxide (SiO ₂ ), silicon nitride (SiN), or silicon oxynitride. (SiON), silicon oxyfluoride (SiOF), silicon carbide (SiC), silicon carbonitride (SiCN), or a combination thereof.

  The wiring interlayer insulating film 313 is made of, for example, an organic polymer of a low dielectric constant material, MSQ, HSQ, or a carbon-containing silicon oxide film.

  The composition of the modified layer 314 is determined according to the composition of the wiring interlayer insulating film 313.

For example, when the wiring interlayer insulating film 313 is a carbon-containing silicon oxide film (SiO _1.6 C _0.4 H), the modified layer 314 is SiO ₂ or SiO _1.9 C _0.1 .

The modified layer 314 can also be composed of SiO _1.8 C _0.1 N _0.1 .

  Further, since the modified layer 314 is a film formed by modifying the wiring interlayer insulating film 313, the composition changes stepwise from the surface of the wiring interlayer insulating film 313 toward the inside of the wiring interlayer insulating film 313. Sometimes it is.

For example, when the wiring interlayer insulating film 313 is a carbon-containing silicon oxide film SiO _1.6 C _0.4 , the modified layer 314 is made of SiO _1.9 C _{0.1 on} the outermost surface of the modified layer 314. As shown in FIG. 5, the concentration of oxygen (O) and carbon (C) may change step by step as the wiring interlayer insulating film 313 is located.

  As described above, the film thickness of the modified layer 314 is uniform. For example, the film thickness of the modified layer 314 is uniform between 50 angstroms and 200 angstroms in the wafer surface.

  The conductive metal wiring 315 and the conductive metal via 322 are made of copper or a copper alloy.

  The cap metal film 316 formed on the conductive metal wiring 315 prevents oxidation of copper contained in the conductive metal wiring 315.

  The cap metal film 316 is made of a non-oxidizing metal such as cobalt tungsten phosphorus or cobalt tungsten boron, for example.

  The via interlayer insulating film 318 is made of, for example, an organic polymer of a low dielectric constant material, MSQ, HSQ, or a carbon-containing silicon oxide film.

  The wiring interlayer insulating film 219 is made of, for example, a low dielectric constant material organic polymer, MSQ, HSQ, or a carbon-containing silicon oxide film.

  On the outermost surface of the wiring interlayer insulating film 219, a modified layer 220 having an element composition different from that of the wiring interlayer insulating film 219 is formed with a uniform film thickness over the wafer surface.

For example, when the wiring interlayer insulating film 219 is made of a carbon-containing silicon oxide film (SiO _1.6 C _0.4 H), the modified layer 220 is made of SiO ₂ or SiO _1.9 C _0.1. Become.

Further, the modified layer 220 may be composed of _SiO 1.8 _{C 0.1 N} 0.1.

For example, when the wiring interlayer insulating film 313 is made of SiO _1.6 C _0.4 and the via interlayer insulating film 318 is made of SiO _1.6 C _0.4 , the modified layer 314 has the structure shown in FIG. As shown, the concentration of carbon (C) increases step by step as approaching the via interlayer insulating film 318 and the wiring interlayer insulating film 313 which are upper and lower films. As described above, the composition of the modified layer 314 changes stepwise toward the upper and lower films in accordance with the compositions of the upper and lower films of the modified layer 314, that is, the via interlayer insulating film 318 and the wiring interlayer insulating film 313. In some cases.

  The wiring interlayer insulating film 319 is made of, for example, an organic polymer of a low dielectric constant material, MSQ, HSQ, or a carbon-containing silicon oxide film.

  On the outermost surface of the wiring interlayer insulating film 319, a modified layer 320 having an element composition different from that of the wiring interlayer insulating film 319 is formed with a uniform film thickness over the wafer surface.

For example, when the wiring interlayer insulating film 319 is made of a carbon-containing silicon oxide film (SiO _1.6 C _0.4 H), the modified layer 320 is made of SiO ₂ or SiO _1.9 C _0.1. Become.

The modified layer 320 can also be made of SiO _1.8 C _0.1 N _0.1 .

  Further, since the modified layer 320 is a film formed by modifying the wiring interlayer insulating film 319, the composition changes stepwise from the surface of the wiring interlayer insulating film 319 toward the inside of the wiring interlayer insulating film 319. Sometimes it is.

For example, when the wiring interlayer insulating film 319 is a carbon-containing silicon oxide film SiO _1.6 C _0.4 , the modified layer 320 is made of SiO _1.9 C _{0.1 on} the outermost surface of the modified layer 320. As shown in FIG. 5, the concentration of oxygen (O) and carbon (C) may change step by step as the wiring interlayer insulating film 319 is located.

  As described above, the film thickness of the modified layer 320 is uniform. For example, the film thickness of the modified layer 320 is uniform between 50 angstroms and 200 angstroms in the wafer surface.

  As shown in FIG. 9, the semiconductor device 300 according to the third embodiment is configured to have two layers of conductive metal wiring, but the manufacturing process of the conductive metal wiring and the wiring interlayer insulating film is repeated. Therefore, it is possible to configure as a multilayer wiring structure having three or more layers.

  Alternatively, a wiring interlayer insulating film (not shown) of a type different from the wiring interlayer insulating film 319 can be formed on the multilayer wiring structure, and a conductive metal wiring can be formed therein.

  The semiconductor device 300 according to the third embodiment is manufactured by a dual damascene process in which the conductive metal via 322 and the conductive metal wiring 321 are simultaneously formed. It is also possible to manufacture by a single damascene process in which 321 is formed separately.

  10 to 20 are cross-sectional views of the semiconductor device 100 in each step of the method of manufacturing the semiconductor device 100 according to the first embodiment shown in FIG. Hereinafter, as a fourth embodiment, a method of manufacturing the semiconductor device 100 according to the first embodiment will be described with reference to FIGS.

  First, as illustrated in FIG. 10, the insulating film 412 is formed over the semiconductor substrate 411.

  As the semiconductor substrate 411, a single crystal silicon substrate can be used.

  The insulating film 412 is formed of, for example, borophosphosilicate glass (BPSG), phosphosilicate glass (PSG), silicon oxide (SiO 2), silicon nitride (SiN), silicon oxynitride (PSN). The film is composed of SiON), silicon oxyfluoride (SiOF), silicon carbide (SiC), silicon carbonitride (SiCN), or a combination thereof.

  Next, as shown in FIG. 11, a wiring interlayer insulating film 413 is formed on the insulating film 412.

  The wiring interlayer insulating film 413 is made of, for example, an organic polymer of a low dielectric constant material, MSQ, HSQ, or a carbon-containing silicon oxide film.

In some cases, a hard mask made of, for example, an insulating film of SiO ₂ or SiC is formed on the wiring interlayer insulating film 413.

  Next, a photoresist (not shown) is applied on the wiring interlayer insulating film 413, and the photoresist is exposed and developed to form an etching mask (not shown). Next, using this mask, the wiring interlayer insulating film 413 is etched to form a wiring groove 414 in the wiring interlayer insulating film 413 as shown in FIG.

  Next, as shown in FIG. 13, a metal barrier film (not shown) or a wiring metal film 415 is embedded in the wiring groove 414.

  For example, the metal barrier film is made of tantalum or tantalum nitride, and the wiring metal film 415 is made of copper or a copper alloy.

  Thereafter, as shown in FIG. 14, the excessive wiring metal film 415, that is, the wiring metal film 415 above the wiring interlayer insulating film 413 is removed by chemical mechanical polishing (CMP) to form a wiring 416. . In this CMP, the wiring interlayer insulating film 413 is exposed.

  Next, as shown in FIG. 15, before forming the cap insulating film 419, a predetermined treatment 417 is performed on the surface of the metal wiring 416 and the surface of the wiring interlayer insulating film 413, so that the outermost surface of the wiring interlayer insulating film 413 is formed. Then, a modified layer 418 having an element composition different from that of the wiring interlayer insulating film 413 is formed.

  As the predetermined treatment 417, plasma treatment (vacuum plasma treatment) such as nitrogen plasma treatment, ammonia plasma treatment, hydrogen plasma treatment, helium plasma treatment before the formation of the cap insulating film 419 can be selected.

  Alternatively, as the predetermined processing 417, UV processing (vacuum UV processing) or EB processing can be performed.

The modified layer 418 is made of, for example, SiO ₂ or SiO _1.9 C _0.1 . Alternatively, the modified layer 418 can be composed of SiO _1.8 C _0.1 N _0.1 .

  Further, since the modified layer 418 is a film formed by modifying the wiring interlayer insulating film 413, the composition changes stepwise from the surface of the wiring interlayer insulating film 413 toward the inside of the wiring interlayer insulating film 413. Sometimes it is.

For example, when the wiring interlayer insulating film 413 is a carbon-containing silicon oxide film SiO _1.6 C _0.4 , the modified layer 418 is made of SiO _1.9 C _{0.1 on} the outermost surface of the modified layer 418. As shown in FIG. 5, the concentration of oxygen (O) and carbon (C) may change step by step as the wiring interlayer insulating film 413 enters.

  As described above, the film thickness of the modified layer 418 is uniform. For example, the film thickness of the modified layer 418 is uniform between 50 angstroms and 200 angstroms in the wafer surface.

  After the modified layer 418 is formed by the predetermined process 417, as shown in FIG. 16, a cap insulating film 419, a via interlayer insulating film 420, and a wiring interlayer insulating film 421 are formed in this order.

  The cap insulating film 419 is made of, for example, silicon carbide, silicon carbonitride, or silicon nitride.

  The via interlayer insulating film 420 and the wiring interlayer insulating film 421 are organic polymers of low dielectric constant materials, MSQ, HSQ, or carbon-containing silicon oxide films.

  Thereafter, as shown in FIG. 17, via holes 422 are formed in the via interlayer insulating film 420 and wiring trenches 423 are formed in the wiring interlayer insulating film 421 by an etching process.

  Next, as shown in FIG. 18, a metal barrier film (not shown) or a wiring metal film 424 is embedded in the via hole 422 and the wiring groove 423.

  The barrier metal film is made of, for example, tantalum or tantalum nitride, and the wiring metal film 424 is made of copper or a copper alloy.

  At this time, as shown in FIG. 18, even when the bottom surface of the via hole 422 is displaced from the lower wiring metal film 424 due to misalignment of the via hole 422, the modified layer 418 exists. The etching rate is lower than that of the insulating film 420, and the penetration of the via hole 422 into the wiring interlayer insulating film 413 can be suppressed.

  After that, as shown in FIG. 19, the excess wiring metal film 424 is removed by chemical mechanical polishing (CMP), and the metal wiring 426 and the via 425 are formed. In this CMP, the wiring interlayer insulating film 421 is exposed.

  Next, as shown in FIG. 20, before forming the cap insulating film 429, a predetermined treatment 427 is performed on the surface of the metal wiring 426 and the surface of the wiring interlayer insulating film 421, so that the outermost surface of the wiring interlayer insulating film 421 is formed. Then, a modified layer 428 having an element composition different from that of the wiring interlayer insulating film 421 is formed.

  As the predetermined treatment 427, plasma treatment (vacuum plasma treatment) such as nitrogen plasma treatment, ammonia plasma treatment, hydrogen plasma treatment, helium plasma treatment before film formation of a cap insulating film (not shown) can be selected. .

  Alternatively, as the predetermined processing 427, UV processing (vacuum UV processing) or EB processing can be performed.

The modified layer 428 is made of, for example, SiO ₂ or SiO _1.9 C _0.1 . Alternatively, the modified layer 428 can be composed of SiO _1.8 C _0.1 N _0.1 .

  Further, since the modified layer 428 is a film formed by modifying the wiring interlayer insulating film 421, the composition changes stepwise from the surface of the wiring interlayer insulating film 421 toward the inside of the wiring interlayer insulating film 421. Sometimes it is.

For example, when the wiring interlayer insulating film 421 is a carbon-containing silicon oxide film SiO _1.6 C _0.4 , the modified layer 428 is made of SiO _1.9 C _{0.1 on} the outermost surface of the modified layer 428. As shown in FIG. 5, the concentration of oxygen (O) and carbon (C) may change stepwise as it becomes inside the wiring interlayer insulating film 421.

  As described above, the film thickness of the modified layer 428 is uniform. For example, the film thickness of the modified layer 428 is uniform between 50 angstroms and 200 angstroms in the wafer surface.

  As shown in FIG. 20, the semiconductor device manufactured by the method of manufacturing a semiconductor device according to the fourth embodiment is configured to have two layers of conductive metal wiring. By repeating the manufacturing process of the insulating film, a structure having a multilayer wiring structure of three or more layers can be formed.

  Alternatively, it is also possible to form a wiring interlayer insulating film (not shown) of a type different from the wiring interlayer insulating film 421 on the multilayer wiring structure and to form a conductive metal wiring therein.

  In the semiconductor device manufacturing method according to the fourth embodiment, a dual damascene process in which the conductive metal via 425 and the conductive metal wiring 426 are simultaneously formed is employed. However, the conductive metal via 425 and the conductive metal via 425 are electrically conductive. It is also possible to employ a single damascene process in which the conductive metal wiring 426 is formed separately.

  Note that another layer may be formed over the modified layer 428 after the predetermined treatment 427 is performed.

  21 to 34 are cross-sectional views of the semiconductor device 200 in the respective steps of the method of manufacturing the semiconductor device 200 according to the second embodiment shown in FIG. Hereinafter, as a fifth embodiment, a method of manufacturing the semiconductor device 200 according to the second embodiment will be described with reference to FIGS.

  First, as illustrated in FIG. 21, the insulating film 512 is formed over the semiconductor substrate 511.

  As the semiconductor substrate 511, a single crystal silicon substrate can be used.

  The insulating film 512 is formed of, for example, borophosphosilicate glass (BPSG), phosphosilicate glass (PSG), silicon oxide (SiO 2), silicon nitride (SiN), silicon oxynitride (PSN). The film is composed of SiON), silicon oxyfluoride (SiOF), silicon carbide (SiC), silicon carbonitride (SiCN), or a combination thereof.

  Next, as shown in FIG. 22, a wiring interlayer insulating film 513 is formed on the insulating film 512.

  The wiring interlayer insulating film 513 is made of, for example, an organic polymer of a low dielectric constant material, MSQ, HSQ, or a carbon-containing silicon oxide film.

In some cases, a hard mask made of, for example, a SiO ₂ or SiC insulating film is formed on the wiring interlayer insulating film 513.

  Next, a photoresist (not shown) is applied on the wiring interlayer insulating film 513, and the photoresist is exposed and developed to form an etching mask (not shown). Next, using this mask, the wiring interlayer insulating film 513 is etched to form a wiring groove 514 in the wiring interlayer insulating film 513 as shown in FIG.

  Next, as shown in FIG. 24, a metal barrier film (not shown) or a wiring metal film 515 is embedded in the wiring groove 514.

  For example, the metal barrier film is made of tantalum or tantalum nitride, and the wiring metal film 515 is made of copper or a copper alloy.

  After that, as shown in FIG. 25, the excessive wiring metal film 515, that is, the wiring metal film 515 above the wiring interlayer insulating film 513 is removed by chemical mechanical polishing (CMP), and the wiring 516 is formed. . During this CMP, the wiring interlayer insulating film 513 is exposed.

  Next, as shown in FIG. 26, a cap metal film 517 is formed on the metal wiring 516.

  The cap metal film 517 is made of, for example, cobalt tungsten phosphorus or cobalt tungsten boron, which is a non-oxidizing metal.

  Next, as shown in FIG. 27, a predetermined treatment 518 is performed on the surface of the cap metal film 517 and the surface of the wiring interlayer insulating film 513, and the element composition of the wiring interlayer insulating film 513 is on the outermost surface of the wiring interlayer insulating film 513. Different modified layers 519 are formed.

  As the predetermined treatment 518, plasma treatment (vacuum plasma treatment) such as nitrogen plasma treatment, ammonia plasma treatment, hydrogen plasma treatment, and helium plasma treatment before the formation of the cap insulating film 520 can be selected.

  Alternatively, as the predetermined treatment 518, since the surface of the metal wiring 516 is covered with the non-oxidizing cap metal film 517, it is possible to select oxygen plasma treatment (vacuum oxygen plasma treatment).

  Alternatively, as the predetermined processing 518, UV processing (vacuum UV processing) or EB processing can be performed.

The modified layer 519 is made of, for example, SiO ₂ or SiO _1.9 C _0.1 . Alternatively, the modified layer 519 can be composed of SiO _1.8 C _0.1 N _0.1 .

  Further, since the modified layer 519 is a film formed by modifying the wiring interlayer insulating film 513, the composition changes stepwise from the surface of the wiring interlayer insulating film 513 toward the inside of the wiring interlayer insulating film 513. Sometimes it is.

For example, when the wiring interlayer insulating film 513 is a carbon-containing silicon oxide film SiO _1.6 C _0.4 , the modified layer 519 is made of SiO _1.9 C _{0.1 on} the outermost surface of the modified layer 519, As shown in FIG. 5, the concentration of oxygen (O) and carbon (C) may change step by step as the wiring interlayer insulating film 513 is formed.

  As described above, the film thickness of the modified layer 519 is uniform. For example, the film thickness of the modified layer 519 is uniform between 50 angstroms and 200 angstroms in the wafer surface.

  After the modified layer 517 is formed by the predetermined treatment 518, as shown in FIG. 28, a cap insulating film 520, a via interlayer insulating film 521, and a wiring interlayer insulating film 522 are formed in this order.

  The cap insulating film 520 is made of, for example, silicon carbide, silicon carbonitride, or silicon nitride.

  Further, when the cap metal film 517 is made of a non-oxidizing material, the cap insulating film 520 can also be made of an oxide such as silicon oxide.

  The via interlayer insulating film 521 and the wiring interlayer insulating film 522 are organic polymer, MSQ, HSQ, or carbon-containing silicon oxide film of a low dielectric constant material.

  Further, since the surface of the metal wiring 516 is covered with the non-oxidizing cap metal film 517, as shown in FIG. 29, the via interlayer insulating film 521 is directly formed on the modified layer without forming the cap insulating film 520. It is also possible to form on 519 and the cap metal film 517.

  Thereafter, as shown in FIG. 30, via holes 523 are formed in the via interlayer insulating film 521 and wiring trenches 524 are formed in the wiring interlayer insulating film 522 by an etching process.

  Next, as shown in FIG. 31, a metal barrier film (not shown) or a wiring metal film 525 is embedded in the via hole 523 and the wiring groove 524.

  The barrier metal film is made of, for example, tantalum or tantalum nitride, and the wiring metal film 525 is made of copper or a copper alloy.

  At this time, as shown in FIG. 31, even when the bottom surface of the via hole 523 is displaced from the lower wiring metal film 516 due to the misalignment of the via hole 523, the modified layer 519 is present, The etching rate is lower than that of the insulating film 521, and the penetration of the via hole 523 into the wiring interlayer insulating film 513 can be suppressed.

  Thereafter, as shown in FIG. 32, the excessive wiring metal film 525 is removed by a chemical mechanical polishing (CMP) method, and the metal wiring 526 and the via 527 are formed. In this CMP, the wiring interlayer insulating film 522 is exposed.

  Next, as shown in FIG. 33, a cap metal film 528 made of a non-oxidizing material is formed on the metal wiring 526.

  The cap metal film 528 is made of, for example, cobalt tungsten phosphorus or cobalt tungsten boron.

  Next, as shown in FIG. 34, the surface of the cap metal film 528 and the surface of the wiring interlayer insulating film 522 are subjected to a predetermined treatment 529, and the wiring interlayer insulating film 522 has an element composition on the outermost surface of the wiring interlayer insulating film 522. Different modified layers 530 are formed.

  As the predetermined treatment 529, plasma such as nitrogen plasma treatment, ammonia plasma treatment, hydrogen plasma treatment, helium plasma treatment before the formation of the via interlayer insulation film (not shown) before the formation of the cap insulation film (not shown). A treatment (vacuum plasma treatment) can be selected.

  Alternatively, as the predetermined treatment 529, since the surface of the metal wiring 526 is covered with the non-oxidizing cap metal film 528, an oxygen plasma treatment (vacuum oxygen plasma treatment) can be selected.

  Alternatively, as the predetermined processing 529, UV processing (vacuum UV processing) or EB processing can be performed.

The modified layer 530 is made of, for example, SiO ₂ or SiO _1.9 C _0.1 . Alternatively, the modified layer 530 can be composed of SiO _1.8 C _0.1 N _0.1 .

  Further, since the modified layer 530 is a film formed by modifying the wiring interlayer insulating film 522, the composition changes stepwise from the surface of the wiring interlayer insulating film 522 toward the inside of the wiring interlayer insulating film 522. Sometimes it is.

For example, when the wiring interlayer insulating film 522 is a carbon-containing silicon oxide film SiO _1.6 C _0.4 , the modified layer 530 is made of SiO _1.9 C _{0.1 on} the outermost surface of the modified layer 530. As shown in FIG. 5, the concentration of oxygen (O) and carbon (C) may change step by step as the wiring interlayer insulating film 522 is formed.

  As described above, the film thickness of the modified layer 530 is uniform. For example, the film thickness of the modified layer 530 is uniform between 50 angstroms and 200 angstroms in the wafer surface.

  As shown in FIG. 34, the semiconductor device manufactured by the method of manufacturing a semiconductor device according to the fifth embodiment is configured to have two layers of conductive metal wiring. By repeating the manufacturing process of the insulating film, a structure having a multilayer wiring structure of three or more layers can be formed.

  Alternatively, a wiring interlayer insulating film (not shown) of a type different from the wiring interlayer insulating film 522 can be formed on the multilayer wiring structure, and a conductive metal wiring can be formed therein.

  In the semiconductor device manufacturing method according to the fifth embodiment, a dual damascene process in which the conductive metal via 527 and the conductive metal wiring 526 are simultaneously formed is employed. It is also possible to employ a single damascene process in which the conductive metal wiring 526 is formed separately.

Claims (11)

A semiconductor substrate, a plurality of copper wiring layers formed on the semiconductor substrate, a copper via layer that interconnects the upper copper wiring layer and the lower copper wiring layer, and the copper wiring layer isolated from each other In a semiconductor device comprising a wiring interlayer insulating film and a via interlayer insulating film that insulates and isolates the copper via layer from each other,
A semiconductor device, comprising: a modified layer having a uniform thickness formed on at least a surface of the wiring interlayer insulating film of the wiring interlayer insulating film and the via interlayer insulating film.   The semiconductor device according to claim 1, wherein a composition of the modified layer changes toward the inside of the wiring interlayer insulating film.   The semiconductor device according to claim 1, further comprising a cap metal film formed on the copper wiring layer in order to prevent oxidation of copper contained in the copper wiring layer.   4. The semiconductor device according to claim 3, wherein the via interlayer insulating film is directly formed on the cap metal film and the wiring interlayer insulating film.   The semiconductor device according to claim 1, further comprising a cap insulating film formed on the modified layer and the copper wiring layer. A semiconductor substrate, a plurality of copper wiring layers formed on the semiconductor substrate, a copper via layer that interconnects the upper copper wiring layer and the lower copper wiring layer, and the copper wiring layer isolated from each other In a method for manufacturing a semiconductor device, comprising: a wiring interlayer insulating film; and a via interlayer insulating film that isolates and isolates the copper via layer from each other.
And a step of selectively modifying the surface layer of the wiring interlayer insulating film by embedding the copper wiring layer in the wiring interlayer insulating film and then subjecting the wiring interlayer insulating film to a vacuum surface treatment. A method for manufacturing a semiconductor device.   The method of manufacturing a semiconductor device according to claim 6, wherein the vacuum surface treatment is a vacuum plasma treatment.   The method of manufacturing a semiconductor device according to claim 6, wherein the vacuum surface treatment is a vacuum UV treatment.   9. The semiconductor device according to claim 6, further comprising a step of forming a cap metal film on the copper wiring layer in order to prevent oxidation of copper contained in the copper wiring layer. Manufacturing method.   10. The method of manufacturing a semiconductor device according to claim 9, further comprising a step of directly forming the via interlayer insulating film on the cap metal film and the wiring interlayer insulating film.   The method of manufacturing a semiconductor device according to claim 6, further comprising a step of forming a cap insulating film on the modified layer and the copper wiring layer.

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