JP4263053B2 - Manufacturing method of semiconductor device - Google Patents

Description

The present invention relates to a method of manufacturing a semiconductor device with a multilayer wiring structure having a damascene structure, in particular, while maintaining sufficient mechanical strength to withstand the CMP process, the production of effective semiconductor device that can be reduced wiring capacitance Regarding the method .

  In recent years, in order to meet the demand for higher performance of a semiconductor device and an increase in circuit scale, higher wiring density and multilayering are required. As a technique for realizing high-density and multi-layered wiring, a so-called damascene method in which a conductive material is embedded in a via hole or wiring groove formed in an insulating film to form a metal wiring has been put into practical use.

  However, as the wiring density increases and the number of layers increases, an electrical signal delay caused by the interaction of signals flowing through adjacent metal wirings, that is, an RC delay occurs, resulting in a decrease in the operating speed of the semiconductor device. In addition, the problem of increased power consumption cannot be ignored. Therefore, various studies have been made to reduce the wiring resistance and the capacitance between the wirings to suppress the RC delay.

  In order to reduce the wiring resistance, a technique using Cu having a small resistance value in place of conventional aluminum as a wiring material has been put into practical use. In addition, in order to reduce the inter-wiring capacity, it has been attempted to apply a material having a low relative dielectric constant to the material of the insulating film (wiring interlayer insulating film) in which the wiring groove that accommodates the wiring is formed. Instead of the silicon oxide film (relative dielectric constant k: 4.0 to 4.5) used as the wiring interlayer insulating film, an insulating film (low-k film) having a relative dielectric constant k smaller than that of the silicon oxide film is applied. Is being considered. In this case, in order to effectively reduce the capacitance between the wirings, it is desirable to reduce the relative dielectric constant k of the wiring interlayer insulating film to, for example, 3.0 or less.

  Silsesquiosan-based materials, such as hydrogenated cissesquioxane and methyl cissesquioxane, have a small relative dielectric constant of a relative dielectric constant k of 3.0 or less, and are attracting attention as materials for wiring interlayer insulation films. ing. Further, some organic insulating films such as polyallyl ether have a very small relative dielectric constant of a relative dielectric constant k of 2.7 or less. However, since the organic insulating film generally has a very low mechanical strength, when applied to a wiring interlayer insulating film, the wiring layer may be damaged during a process such as CMP.

  FIG. 7 shows a conventional semiconductor device having a multilayer wiring structure described in Patent Document 1. In FIG. The semiconductor device 30 is a semiconductor device having a dual damascene structure, and is a first wiring interlayer insulating film made of a silicon oxide film, which is sequentially stacked on elements such as MOS transistors formed on a silicon substrate 31. Protective film 33 made of silicon nitride film, via interlayer insulating film 34 made of methylsilsesquioxane, etch stopper film 35 made of silicon oxide film, insulating film made of polyallyl ether having a relative dielectric constant k = 2.7 (first film) 2 wiring interlayer insulating film) 36. On the second wiring interlayer insulating film 36, the silicon oxide film 37 formed as a hard mask in the polishing process by the CMP method in the manufacturing process of the semiconductor device 30 is left as it is.

  A lower wiring 38 is formed in the first wiring interlayer insulating film, a via plug 39 is formed in the protective film 33, the via interlayer insulating film 34, and the etch stopper 35, and an upper wiring 40 is formed in the second wiring interlayer insulating film. , Each embedded. The via plug 39 and the upper layer wiring 40 are embedded in the same process, and the lower layer wiring 38, the via plug 39, and the upper layer wiring 40 are all made of Cu.

According to the above-mentioned patent document, the second wiring interlayer insulating film for embedding the upper layer wiring is formed of an organic insulating film having a low relative dielectric constant, and this is protected by a silicon oxide film having a high mechanical strength. A semiconductor device having high mechanical strength is obtained.
JP 2002-134609 A (paragraphs 0038 to 0070, FIG. 4)

  In the semiconductor device described in the patent document, as described above, the wiring interlayer insulating film is formed of an organic insulating film having a low relative dielectric constant, and this is protected with a silicon oxide film, thereby reducing the capacitance between the wirings. ing. However, in this structure, the silicon oxide film provided for obtaining the mechanical strength has a high relative dielectric constant, so that there is a problem that the inter-wiring capacitance is not sufficiently reduced.

In view of the above, the present invention is a method for manufacturing a semiconductor device having a multilayer wiring structure having a damascene structure, and can effectively reduce wiring capacity while maintaining sufficient mechanical strength to withstand a CMP process. An object is to provide a method for manufacturing a semiconductor device.

In order to achieve the above object, a semiconductor device according to the present invention includes a plurality of wiring interlayer insulating films each having a receiving groove for storing a metal wiring, and via plugs sandwiched between two adjacent wiring interlayer insulating films. In a semiconductor device having a multilayer wiring structure including a via interlayer insulating film to be accommodated,
At least one of the wiring interlayer insulating film and the via interlayer insulating film includes an organic insulating film and a siloxane having a hydrogen group or an alkyl group as a side chain as a main component formed on the organic insulating film. Or an insulating film (hereinafter referred to as a low dielectric constant inorganic insulating film) formed of a polymer mainly composed of silsesquioxane having a hydrogen group or an alkyl group as a side chain. It is said.

  In the semiconductor device according to the present invention, at least one insulating film of the wiring interlayer insulating film and the via interlayer insulating film is formed on the organic insulating film and the organic insulating film, and is defined by the present invention. By providing the dielectric constant inorganic insulating film, the low dielectric constant inorganic insulating film of the wiring interlayer insulating film or via interlayer insulating film can maintain sufficient mechanical strength to withstand the CMP process. Further, the organic insulating film and the low dielectric constant inorganic insulating film having a low relative dielectric constant can effectively reduce the interwiring capacitance and suppress the RC delay of the electric signal. Furthermore, since the organic insulating film has good adhesion to the low dielectric constant inorganic insulating film, it is possible to suppress interlayer peeling and further increase the mechanical strength of the semiconductor device.

  Further, the lower part of the wiring interlayer insulating film or via interlayer insulating film is composed of an organic insulating film, so that an inorganic insulating film and an etch stopper film adjacent to the lower side of the wiring interlayer insulating film or via interlayer insulating film High etch selectivity can be obtained. Accordingly, it is possible to improve the etch stop property at the time of forming the wiring trench or the via hole and obtain a favorable wiring or via plug shape.

  Examples of low dielectric constant inorganic insulating films include hydrogen silsesquioxane (HSQ), methyl silsesquioxane (MSQ), methyl silsesquioxane (HMSQ). Or what polymerized several types of these in a suitable ratio can be mentioned. The material having an alkyl group in the side chain in the low dielectric constant inorganic insulating film is also referred to as an organic-inorganic hybrid film in the present invention.

  The low dielectric constant inorganic insulating film can be formed by a coating method or the like. The film thickness of the low dielectric constant inorganic insulating film is desirably 100 nm or more and 200 nm or less. This is because if the thickness of the low dielectric constant inorganic insulating film is less than 100 nm, the mechanical strength that can withstand the CMP process is insufficient, and if it exceeds 200 nm, the capacitance between wirings increases. In addition, the film thickness of the low dielectric constant inorganic insulating film may be set to a value equal to or greater than the film thickness of the organic insulating film in order to maintain sufficient mechanical strength to withstand the CMP process. desirable.

  In a preferred embodiment of the present invention, the organic insulating film is formed of a polymer containing aromatic as a main component. Since the low dielectric constant organic insulating film has a very low relative dielectric constant of k = 2.0 to 2.5, it can be suitably applied as the organic insulating film of the present invention. An example of the low dielectric constant organic insulating film is polyallyl ether.

  In a preferred embodiment of the present invention, the wiring interlayer insulating film includes the organic insulating film and the low dielectric constant inorganic insulating film, and the via interlayer insulating film adjacent to the lower side of the wiring interlayer insulating film is inorganic. It is an insulating film. Thereby, it is possible to obtain a good etch stop property when forming a wiring groove in the wiring interlayer insulating film.

  In a preferred embodiment of the present invention, the wiring interlayer insulating film includes the organic insulating film and the low dielectric constant inorganic insulating film, and the via interlayer insulating film adjacent to the lower side of the wiring interlayer insulating film includes A first insulating film and a second insulating film formed on the first insulating film, wherein an etch selectivity between the second insulating film and the organic insulating film is the first insulating film and the organic insulating film; It is formed of a material having a higher etch selectivity with respect to the film. Thereby, when manufacturing the semiconductor device of the present invention, the etching can be stopped more reliably on the upper surface of the second insulating film, so that a wiring groove having a better shape can be obtained.

  According to the semiconductor device of the present invention, at least one of the wiring interlayer insulating film and the via interlayer insulating film is formed on the organic insulating film and the organic insulating film, and is defined by the present invention. By providing the low dielectric constant inorganic insulating film, the low dielectric constant inorganic insulating film of the wiring interlayer insulating film or via interlayer insulating film can maintain sufficient mechanical strength to withstand the CMP process. Further, the organic insulating film and the low dielectric constant inorganic insulating film having a low relative dielectric constant can effectively reduce the interwiring capacitance and suppress the RC delay of the electric signal. Furthermore, since the organic insulating film has good adhesion to the low dielectric constant inorganic insulating film, it is possible to suppress interlayer peeling and further increase the mechanical strength of the semiconductor device.

  Further, the lower part of the wiring interlayer insulating film or via interlayer insulating film is composed of an organic insulating film, so that an inorganic insulating film or an etch stopper film adjacent to the lower side of the wiring interlayer insulating film or via interlayer insulating film is formed. High etch selectivity can be obtained. Accordingly, it is possible to improve the etch stop property at the time of forming the wiring trench or the via hole and obtain a favorable wiring or via plug shape.

  Hereinafter, with reference to the drawings, the present invention will be described in more detail based on exemplary embodiments according to the present invention. FIG. 1 is a cross-sectional view showing a configuration of a semiconductor device having a multilayer wiring structure according to a first embodiment of the present invention. The multilayer wiring structure is a structure formed by laminating two or more wiring layers. The semiconductor device 100 is a semiconductor device having a dual damascene structure, and includes a first wiring interlayer insulating film 12, a cap layer 13, and vias sequentially stacked on an element such as a MOS transistor formed on the silicon substrate 10. An interlayer insulating film 14, an aromatic organic polymer film 15 and a methylsilsesquioxane film 16 constituting the second wiring interlayer insulating film are provided.

The aromatic organic polymer film 15 is formed to a thickness of about 100 nm to 200 nm, and the methylsilsesquioxane film 16 is formed to a thickness of about 100 nm to 200 nm. Here, the methyl silsesquioxane film 16 is preferably set to a film thickness equal to or greater than that of the aromatic organic polymer film 15 in order to maintain sufficient mechanical strength to withstand the CMP process. The cap layer 13 is made of a SiCN film or a SiC film having a thickness of about 50 nm. The via interlayer insulating film 14 is made of an inorganic insulating film having a film thickness of 150 nm to 300 nm, such as a low dielectric constant inorganic insulating film and an SiO ₂ film.

  A lower wiring groove 11 is formed in the first wiring interlayer insulating film 12, and a lower wiring 11 a made of Cu is embedded in the lower wiring groove 11. An upper wiring groove 22 is formed in the second wiring interlayer insulating films 15 and 16, and an upper wiring 24 a made of Cu is embedded in the upper wiring groove 22. A via hole 23 having an inner diameter of about 80 nm to 200 nm is formed in the cap layer 13 and the via interlayer insulating film 14, and a via plug 24b made of Cu is embedded in the via hole 23. The via plug 24b connects the upper wiring layer 24a and the lower wiring layer 11a. The via plug 24b and the upper layer wiring 24a are formed in the same process.

  2A to 2D and FIGS. 3E to 3H are cross-sectional views showing the semiconductor device manufacturing method according to the present embodiment step by step. Hereinafter, an example in which the semiconductor device 100 according to the present embodiment is manufactured using a dual hard mask will be described. First, an element such as a MOS transistor is formed on a silicon substrate 10, and then a first wiring interlayer insulating film 12 in which a lower wiring groove 11 is formed is formed thereon. The lower layer wiring trench 11 accommodates the lower layer wiring 11a.

Next, a second wiring interlayer insulating film having a two-layer structure including a cap layer 13, a via interlayer insulating film 14, an aromatic organic polymer film 15, and a methylsilsesquioxane film 16, a first hard mask forming layer 17a, At the same time, the second hard mask formation layer 18a is sequentially formed (FIG. 2A). The first hard mask forming layer 17a and the second hard mask forming layer 18a are formed of materials having a high etch selectivity, and for example, a SiO ₂ film and a SiN film can be used, respectively.

  Next, as shown in FIG. 2B, a photoresist is applied onto the second hard mask forming layer 18a, and the upper wiring pattern is exposed and developed on the obtained photoresist film, transferred, and transferred. A photoresist mask 19 is used. Subsequently, using the first photoresist mask 19 as a mask, the second hard mask formation layer 18a is selectively etched to form a second hard mask 18 having an upper wiring pattern, and then the first photo mask is formed. The resist mask 19 is removed (FIG. 2C).

  Next, as shown in FIG. 2D, an organic BARC (Bottom Anti-Reflective Coating: not shown) is applied on the second hard mask 18, and a photoresist is applied thereon. Apply. Subsequently, a via pattern is exposed, developed and transferred to the obtained photoresist film to form a second photoresist mask 20, which is used as a mask to selectively etch the first hard mask forming layer 17a. A first hard mask 17 having a pattern is formed. Thus, a dual hard mask composed of the first hard mask 17 and the second hard mask 18 is obtained.

Next, as shown in FIG. 3E, the methyl silsesquioxane film 16 and the aromatic organic polymer film 15 are selectively etched using the first hard mask 17 as a mask. At this time, for etching the aromatic organic polymer film 15 as an etching gas, a mixed gas obtained by mixing Ar, N _{2 and the} like with a fluorocarbon gas such as CHF ₃ and CF ₄ (hereinafter referred to as a first gas). For etching the methyl silsesquioxane film 16, H ₂ , N ₂ , O ₂ , or a mixed gas thereof (hereinafter referred to as a second etching gas) is used. The first etching gas has an etching rate for etching a low dielectric constant organic insulating film of about 200 to 300 nm / min, and the second etching gas has an etching rate of 200 to 300 nm for etching a low dielectric constant inorganic insulating film. / Min.

  The first etching gas has a small etching rate of 50 nm / min or less for etching an inorganic insulating film including a low dielectric constant inorganic insulating film, and the second etching gas is a low dielectric constant organic insulating film. The etch rate for etching the organic insulating film is as low as 50 nm / min or less. Therefore, a high etching selectivity can be obtained between the inorganic insulating film and the organic insulating film with respect to each etching gas. For this reason, the etching can be accurately stopped on the upper surface of the via interlayer insulating film 14 formed of an inorganic insulating film. Subsequently, the second photoresist mask 20 and the BARC film remaining on the second hard mask 18 are removed, so that the aromatic organic polymer film 15 and the methylsilsesquioxane film 16 have a predetermined diameter. The via hole forming hole 21 can be formed.

  Next, as shown in FIG. 3F, the first hard mask 17, the methyl silsesquioxane film 16, and the aromatic organic polymer film 15 are selectively used with the second hard mask 18 as a mask. In addition to etching, the via interlayer insulating film 14 and the cap layer 13 are selectively etched along the cross-sectional shape of the via hole forming hole 21.

  In the selective etching, the first etching gas is used for etching the aromatic organic polymer film 15, and the second etching gas is used for etching the methylsilsesquioxane film 16 and the via interlayer insulating film 14. As a result, similar to the process of forming the via hole formation hole 21, a high etch selectivity can be obtained between the low dielectric constant organic insulating film and the via interlayer insulating film 14 with respect to each etching gas. Therefore, the etching can be accurately stopped on the upper surface of the via interlayer insulating film 14. By this selective etching process, the upper wiring groove 22 is formed in the aromatic organic polymer film 15 and the methylsilsesquioxane film 16, and the via hole 23 is formed in the via interlayer insulating film 14 and the cap layer 13.

  Further, as shown in FIG. 3G, Cu is deposited on the entire surface, and a wiring material 24 made of Cu is embedded in the upper wiring groove 22 and the via hole 23. Subsequently, the first hard mask 17 and the second hard mask 18 are removed by a CMP (Chemical Mechanical Polishing) method. Polishing by the CMP method is performed until the upper surface of the methylsilsesquioxane film 16 is reached. As a result, as shown in FIG. 3 (h), a semiconductor device having a dual damascene structure having an upper layer wiring 24a formed in the upper layer wiring trench 22 and a via plug 24b connecting the upper layer wiring 24a and the lower layer wiring 20. 100 is obtained.

  According to the semiconductor device 100 of this embodiment example, the aromatic organic polymer film 15 has a low relative dielectric constant, and the methylsilsesquioxane film 16 has a low relative dielectric constant and high mechanical strength. Therefore, the aromatic organic polymer film 15 and the methylsilsesquioxane film 16 maintain the mechanical strength sufficient to withstand the CMP process as the entire second wiring interlayer insulating film by the methylsilsesquioxane film 16. It is possible to effectively reduce the inter-wiring capacitance and suppress the RC delay of the electric signal.

  According to the semiconductor device 100 of the present embodiment, a high etch selectivity can be obtained between the inorganic insulating film and the aromatic organic polymer film 15 constituting the via interlayer insulating film 14. Therefore, a good wiring shape can be obtained even if the conventionally provided etch stopper film is omitted between the via interlayer insulating film 14 and the second wiring interlayer insulating film. Furthermore, since the aromatic organic polymer film 15 has good adhesion between the methyl silsesquioxane film 16 and the inorganic insulating film constituting the via interlayer insulating film 14, it is possible to prevent interlayer peeling and The mechanical strength of 100 can be further increased.

FIG. 4 is a sectional view showing a semiconductor device according to the second embodiment of the present invention. The semiconductor device 101 is different from the semiconductor device of the first embodiment shown in FIG. 1 in that an etch stopper film 25 having a thickness of about 50 nm is provided between the via interlayer insulating film 14 and the aromatic organic polymer film 15. Except for this, it has the same configuration as the semiconductor device of the first embodiment. As the etch stopper film 25, for example, a SiC film, a SiN film, or a SiO ₂ film is used.

  The manufacturing method of the semiconductor device 101 of this embodiment example differs from the manufacturing method of the semiconductor device of the first embodiment example in the following points. First, in the process shown in FIG. 2A, an etch stopper film 25 is interposed between the via interlayer insulating film 14 and the aromatic organic polymer film 15. In the etching using the first hard mask 17 shown in FIG. 3E, the etching is stopped on the upper surface of the etch stopper film 25. In the etching using the second hard mask 18 shown in FIG. 3F, the etching for forming the upper wiring groove 22 on the upper surface of the etch stopper film 25 is stopped.

  In the semiconductor device 101 of this embodiment, the etch stopper film 25 and the aromatic organic polymer film 15 are provided by interposing the etch stopper film 25 between the via interlayer insulating film 14 and the aromatic organic polymer film 15. , A higher etch selectivity than that between the via interlayer insulating film 14 and the aromatic organic polymer film 15 can be obtained. Therefore, since the etching can be stopped with higher accuracy on the upper surface of the etch stopper film 25, the upper wiring groove 22 having a better shape can be formed. Further, since the aromatic organic polymer film 15 has good adhesion with the etch stopper film 25, it is possible to prevent delamination and maintain good mechanical strength.

  FIG. 5 is a cross-sectional view showing a semiconductor device according to a third embodiment of the present invention. In the semiconductor device 102 of this embodiment, the via interlayer insulating film has an aromatic organic polymer film 26 having a thickness of 100 to 200 nm and a methyl silsesquioxy film having a thickness of 100 to 200 nm formed thereon. The semiconductor device has the same configuration as that of the semiconductor device of the first embodiment except that it is composed of the sun layer 27 and the thickness of the cap layer 13 is 20 nm or less.

  The manufacturing method of the semiconductor device 102 according to the present embodiment differs from the manufacturing method of the semiconductor device according to the first embodiment in the following points. First, in the step shown in FIG. 2A, the cap layer 13 is formed to have a film thickness of 20 nm or less, and the aromatic organic polymer layer 26 and the methylsilsesquioxane layer are used instead of the via interlayer insulating film 14. 27 is formed. In the step shown in FIG. 3F, the first etching gas is used for etching the methyl silsesquioxane layer 16 in the second wiring interlayer insulating film and the methyl silsesquioxane layer 27 in the via interlayer insulating film. And performing these etchings simultaneously. The etching of the aromatic organic polymer layer 15 in the second wiring interlayer insulating film and the aromatic organic polymer layer 26 in the via interlayer insulating film is simultaneously performed using a second etching gas. .

  The semiconductor device 102 according to the present embodiment has the following effects in addition to the effects exhibited by the semiconductor device according to the first embodiment. That is, the entire wiring interlayer insulating film is maintained by the methyl silsesquioxane layer 27 while maintaining sufficient mechanical strength to withstand the CMP process, and the inter-wiring capacitance is maintained by the aromatic organic polymer film 26 and the methyl silsesquioxane layer 27. Can be effectively reduced and the RC delay of the electrical signal can be suppressed. In addition, since a high etch selectivity can be obtained between the cap layer 13 and the aromatic organic polymer layer 26, a good via shape can be obtained even if the film thickness of the cap layer 13 is smaller than that of the conventional one. Furthermore, since the aromatic organic polymer layer 26 has good adhesion with the methylsilsesquioxane layer, peeling between layers can be prevented, and the mechanical strength of the semiconductor device 102 can be further increased.

  FIG. 6 is a sectional view showing a semiconductor device according to the fourth embodiment of the present invention. In the semiconductor device 103 according to this embodiment, the via interlayer insulating film has an aromatic organic polymer film 26 with a film thickness of 100 to 200 nm and a methyl silsesquioxy film with a film thickness of 100 to 200 nm formed thereon. The semiconductor device has the same configuration as that of the semiconductor device of the second embodiment except that it is composed of the sun layer 27 and the thickness of the cap layer 13 is 20 nm or less.

  The manufacturing method of the semiconductor device 103 according to the present embodiment differs from the manufacturing method of the semiconductor device according to the second embodiment in the following points. First, in the step shown in FIG. 2A, the cap layer 13 is formed to have a film thickness of 20 nm or less, and the aromatic organic polymer layer 26 and the methylsilsesquioxane layer are used instead of the via interlayer insulating film 14. 27 is formed. In the step shown in FIG. 3F, the first etching gas is used for etching the methyl silsesquioxane layer 16 in the second wiring interlayer insulating film and the methyl silsesquioxane layer 27 in the via interlayer insulating film. And performing these etchings simultaneously. The etching of the aromatic organic polymer layer 15 in the second wiring interlayer insulating film and the aromatic organic polymer layer 26 in the via interlayer insulating film is simultaneously performed using a second etching gas. . The semiconductor device 103 according to the present embodiment exhibits the same effects as the effects exhibited by the semiconductor device according to the third embodiment, in addition to the effects exhibited by the semiconductor device according to the second embodiment.

  For example, polyallyl ether can be used as the aromatic organic polymer film described in the first to fourth embodiments. In the first embodiment to the fourth embodiment, the example using the methyl silsesquioxane films 16 and 27 as the low dielectric constant inorganic insulating film has been shown. A dielectric constant inorganic insulating film such as a hydrogenated silsesquioxane film, a hydrogenated methylsilsesquioxane film, or a film obtained by polymerizing a plurality of these in an appropriate ratio can be used.

  As described above, the present invention has been described based on the preferred embodiment. However, the semiconductor device according to the present invention is not limited to the configuration of the above-described embodiment. Semiconductor devices that have been modified and changed are also included in the scope of the present invention. For example, in the first to fourth embodiments, the second wiring interlayer insulating film is composed of a low dielectric constant organic insulating film and a low dielectric constant inorganic insulating film formed on the low dielectric constant organic insulating film. It shall consist of two layers. However, the wiring interlayer insulating film other than the second wiring interlayer insulating film may also be configured by a two-layer structure of a low dielectric constant organic insulating film and a low dielectric constant inorganic insulating film.

It is sectional drawing which shows the structure of the semiconductor device of 1st Embodiment. 2A to 2D are cross-sectional views showing the manufacturing method of the semiconductor device of the first embodiment step by step. FIGS. 3E to 3H are cross-sectional views subsequent to FIG. 2, showing the method for manufacturing the semiconductor device of the first embodiment step by step. It is sectional drawing which shows the structure of the semiconductor device of the example of 2nd Embodiment. It is sectional drawing which shows the structure of the semiconductor device of the example of 3rd Embodiment. It is sectional drawing which shows the structure of the semiconductor device of the example of 4th Embodiment. 10 is a cross-sectional view illustrating a configuration of a semiconductor device described in Patent Document 1. FIG.

Explanation of symbols

10: Silicon substrate 11: Lower layer wiring groove 11a: Lower layer wiring 12: First wiring interlayer insulating film 13: Cap layer 14: Via interlayer insulating film 15: Aromatic organic polymer film 16: Methyl silsesquioxane film 17: First hard mask 18: Second hard mask 19: First photoresist mask 20: Second photoresist mask 21: Via hole formation hole 22: Upper layer wiring groove 23: Via hole 24: Wiring material 24a: Upper layer wiring 24b : Via plug 25: Etch stopper film 26: Aromatic organic polymer film 27: Methyl silsesquioxane film 31: Semiconductor substrate 32: First wiring interlayer insulating film 33: Protection film 34: Via interlayer insulating film 35: Etch stopper Film 36: Insulating film 37: Silicon oxide film 38: Lower layer wiring 39: Via plug 40: Upper layer wiring

Claims (7)

Forming a via interlayer insulating film on the silicon substrate;
A step of forming an organic insulating film on the via interlayer insulating film, and a polymer mainly comprising siloxane having a hydrogen group or an alkyl group as a side chain on the organic insulating film, or a hydrogen group or an alkyl group. Forming a wiring interlayer insulating film by forming an insulating film formed of a polymer mainly composed of silsesquioxane as a side chain; and
Forming via holes and wiring grooves in the via interlayer insulating film and the wiring interlayer insulating film, respectively ;
Burying a wiring material in the via hole and the wiring groove ;
Polishing the wiring material by a chemical mechanical polishing method until reaching the upper surface of an insulating film formed of a polymer containing siloxane as a main component or a silsesquioxane as a main component,
An insulating film formed of a polymer containing siloxane as a main component or a polymer containing silsesquioxane as a main component is formed to have a thickness greater than that of the organic insulating film. Production method. Forming each said via hole and wiring groove in the via layer insulating film and the wiring interlayer insulating film,
Forming a first hard mask layer on the wiring interlayer insulating film;
Forming a second hard mask layer on the first hard mask layer;
Forming a wiring pattern of a photoresist film on the second hard mask layer and performing etching to form a wiring pattern on the second hard mask layer;
Forming a via pattern of a photoresist film on the etched second hard mask layer, and etching the first hard mask layer;
Etching the wiring interlayer insulating film using the etched first hard mask layer;
The method of manufacturing a semiconductor device according to claim 1, further comprising: etching the first hard mask layer, the wiring interlayer insulating film, and the via interlayer insulating film using the etched second hard mask layer. Method.   The method for manufacturing a semiconductor device according to claim 1, wherein the organic insulating film is formed of a polymer having an aromatic as a main component.   4. The semiconductor device according to claim 1, wherein the insulating film formed of the polymer mainly containing siloxane or the polymer mainly containing silsesquioxane is a methylsilsesquioxane film. 5. Manufacturing method.   The semiconductor device according to any one of claims 1 to 4, wherein a film thickness of the insulating film formed of the polymer mainly containing siloxane or the polymer mainly containing silsesquioxane is 100 nm to 200 nm. Manufacturing method. The step of forming the via interlayer insulating film includes:
Forming a cap film having a film thickness of 20 nm or less comprising a SiCN film or a SiC film;
Forming an aromatic organic polymer film on the cap film;
Forming a methylsilsesquioxane film having a thickness of 100 nm to 200 nm on the aromatic organic polymer film. 6. The method of manufacturing a semiconductor device according to claim 1, comprising:   The wiring interlayer insulating film includes an insulating film formed of the organic insulating film and the polymer mainly containing siloxane or the polymer mainly containing silsesquioxane, and is provided below the wiring interlayer insulating film. The method for manufacturing a semiconductor device according to claim 1, wherein the adjacent via interlayer insulating film is an inorganic insulating film.

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