JPH11288923A - Trench forming method and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To form a trench, having an opening and the bottom face of almost the same diameter by performing etching treatment at a specific flow rate using the etching gas of specific mixing percentage. SOLUTION: An element isolating region 102 and a diffused layer 103 are formed on a semiconductor substrate 101, and a trench, to be used for the backed wiring of the interlayer insulating film 104 formed on the upper layer of the diffused layer 103 in formed. In this case, at least C4 F8 or C3 F8 and CO, Ar and O2 are used as etching gas in the process wherein the trench is formed by etching. At this time, the flow rate of the C4 F8 or C3 F8 is set at 6 to 10 sccm, the flow ratio of CO/Ar is set at 10 to 20%, and the flow rate of O2 is set at 5 to 7 sccm. In addition, the total flow rate of etching gas is set at 350 to 400 sccm or smaller. In this way, the trench can be formed by performing high speed and vertical etching under satisfactory etching conditions, and satisfactory wiring plug can be formed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a dry etching method used in the field of manufacturing semiconductor devices.
In particular, the present invention relates to an etching method capable of performing vertical and high-speed trenches used for wiring.

[0002]

2. Description of the Related Art As the integration and speed of semiconductor devices increase,
In recent years, a so-called embedded wiring technique of forming a trench in advance and embedding a metal in the trench to form a metal wiring has attracted attention. This buried wiring technology is formed on a backing wiring which lowers the resistance of the diffusion layer by backing it on the impurity diffusion layer of the semiconductor substrate, a local wiring connecting between each diffusion layer and the word line, and an insulating film on the connection hole. It is applied to various wiring such as damascene wiring.

[0003] Among these, the trench used for the backing wiring is a method of reducing the resistance of the diffusion layer by increasing the contact area with the diffusion layer by forming the connection hole into a trench shape. That is, with the miniaturization of the design rule of the semiconductor device, the diameter of the contact hole formed in the diffusion layer decreases, and when the connection hole is formed in a cylindrical shape, the contact area with the diffusion layer decreases, and the resistance increases. It is used as a means to solve the problem of

[0004] Such a trench is formed by etching an insulating film formed on a substrate. Therefore,
At the time of etching, the selection ratio between the insulating film and the underlying silicon substrate, and when the connection hole has a self-aligned contact structure, the selection ratio between the insulating film and silicon nitride used as a stopper for the gate electrode are taken into consideration. Is done.

As a method of etching an insulating film with a high selectivity, for example, Japanese Patent Application Laid-Open No. 57-64951 discloses a method of using C ₄ F ₈ or C ₃ F ₈ by using a previously patterned aluminum layer as a mask. There is known a technique for selectively etching a stacked film (a so-called ONO film) composed of silicon oxide-silicon nitride-silicon oxide by reactive sputter etching. This is C ₄
Reactive sputter etching using F ₈ or the like, an aluminum mask material is a technique utilizing the characteristics that there is no absolutely contamination of the etched silicon substrate.

Therefore, when forming a trench in an insulating film, attempts have been made to improve the reactive sputter etching method using C ₄ F ₈ or C ₃ F ₈ as an etching gas.

For example, as a conventionally known magnetron type RIE (Reactive I
on Etching) device, C ₄ F ₈ , CO,
There is an etching method using a combination of Ar, O _{2 and the} like as an etching gas.

Hereinafter, the results of an experiment in which the present inventors formed a backing wiring on an insulating film by this method will be described with reference to the drawings. As shown in FIG. 9A, for example, an element isolation film 602 is formed on an n-type semiconductor substrate 601, and ion implantation of boron or the like (BF ₂ ⁺ ions: 35 keV, 3E15ion) is performed.
s / cm ²⁾ after a nitrogen atmosphere, to form a diffusion layer 603 by annealing of 10 minutes at 900 ° C., an interlayer insulating film 604 made of silicon oxide, is formed at a thickness of 1000nm by atmospheric pressure CVD , Photoresist film 605
Is formed into a predetermined trench pattern. In this case, the trench pattern 606 has, for example, a width of 0.3 μm, a length of 0.5 μm, and 40 μm.

Next, after etching is performed under the following conditions, the resist film 606 is peeled off to obtain a state as shown in FIG.

(Etching conditions) Apparatus: magnetron-type RIE apparatus Etching gas: C ₄ F ₈ / CO / Ar / O ₂ = 8 /
150/200/3 sccm Pressure: 5, 3 Pa RFPower: 1700 W Electrode spacing: 27 mm Electrode temperature: top / sidewall / bottom = 60/60/2
0 ° C Wafer back pressure (center / edge) = 9.3 / 5
3.3 hPa overetch rate: 20%

As a result of this etching, the inclination angles A and B of the side walls of the trench were 85.5 to 87.5 °, the shaved amount g of the underlying silicon substrate was about 30 nm, and h was about 40 nm. The difference between the shaved amounts g and h of the underlying silicon substrate is caused by the difference in the etching rate due to the microloading effect due to the difference in the opening area of the resist film.

The etching rate of the oxide film and the in-plane uniformity of the etching rate of the oxide film are as follows: 360 nm / min (± 3 μm) in a trench having a width of 0.3 μm and a length of 0.5 μm.
%)Met.

Thereafter, as shown in FIG. 10C, a metal 607 for forming an adhesion layer is formed inside the trench, and after a lamp annealing process, a metal 608 for burying is formed. A buried wiring was formed by a whole-surface etch-back method using ionic ion etching.

The following is an example of the conditions for forming the buried metal wiring. Sputtering of metal for adhesion layer formation: Collimated Ti
= 20 nm (0.52 Pa, 8 kW, Ar = 35 scc)
m, 300 ° C.) Lamp annealing: 650 ° C., 1 atm, N ₂ = 100
%, 30 sec Blanket W CVD: 600 nm (10.7 kP
a, WF ₆ / H ₂ / Ar = 40/400 / 2250sc
cm, 450 ° C) W etch back: 1st step (W Etch) 4
5.5 Pa, 275 W, SF ₆ / Ar / He = 110 /
90/5 sccm) 2ed step (TiN Etch) 6.5 Pa, 2
50W, Ar / Cl ₂ = 75/5 sccm 3rd step (W overetch) 32.5P
a, 70W, SF ₆ / Ar / He = 20/10 / 1sc
cm

Since the trench formed by the above-described conventional method has a small side wall inclination angle, the contact area with the diffusion layer becomes smaller than the originally designed area, and the resistance becomes higher than the designed value. become.

Since the trench increases the contact area with the diffusion layer, it is desired to increase the contact area as much as possible. However, in a highly integrated semiconductor device, the width and length of the trench are limited, so that the width and length of the trench cannot be changed conveniently. Therefore, in the etching for forming the trench, it is necessary to process as designed as much as possible, that is, to perform a vertical etching to reduce the conversion difference, and to reduce the shaving amount of the underlying silicon substrate as much as possible.

[0017]

As an etching method which satisfies this, 1) a method in which the mean free path of ions is lengthened by lowering the pressure at the time of etching to perform etching with strong anisotropy, and 2) a method of etching at the time of etching. There is known a method of reducing a gas component (Depo-based substance) having a property of adhering to a side wall to suppress a side wall inclination angle.

Of the above methods, in the case of 1), when the pressure is reduced, the substance to be an etchant and the film to be etched are discarded before they sufficiently react with each other, so that the etching rate is lowered.

Regarding 2), when it is desired to perform etching at a high aspect ratio such as in the case of trench formation, there are reactive ions which are incident perpendicularly to the wafer and ions which are obliquely incident. Therefore, when the amount of the Depo-based material decreases, the trench may have a bowing shape. Of course, it is said that if the pressure is reduced, it is difficult to form a bowing shape. However, in this case, the etching rate is reduced, so it is hard to say that this is an ideal method.

Further, among the gas components used as an etching gas in the present invention, C ₄ F is used as the Depo-based substance.
₈ (or C ₃ F ₈ ), which is the only gas component that contains the etchant (F source). Therefore, C
_If the content of ₄ F ₈ (C ₃ F ₈ ) is too small, the etching rate will be extremely reduced. For the above reasons, it can be said that the method 2) is not very suitable.

In the etching, it is necessary to consider the etching selectivity with respect to the underlying silicon or silicon nitride.

The present invention has been made in view of the above circumstances, and has a method of forming a trench by etching an insulating film vertically and at a high speed with a high selectivity to an underlying silicon substrate or a silicon nitride film. And a semiconductor manufacturing method using the same.

[0023]

According to the present invention, in order to achieve the above-mentioned object, a conductor is filled in the insulating film to connect the lower conductive layer and the upper conductive layer laminated with the insulating film interposed therebetween. Forming a trench for etching by etching, the step of forming the trench by etching, as an etching gas,
At least C ₄ F ₈ or C ₃ F _8, CO, Ar was used and O _2, the flow rate of C ₄ F ₈ or C ₃ F ₈ is 6-1
0 sccm, CO / Ar flow rate ratio 10-20%, O ₂
Is 5 to 7 sccm, and the total flow rate of the etching gas is 350 to 400 sccm or less, more preferably 3 to 400 sccm.
Provided is a method for forming a trench, which is a step of performing etching at 61 to 67 sccm.

In the present invention, the trench is preferably a trench for filling a conductor in the insulating film for connecting a conductive layer formed on a semiconductor substrate and an upper wiring.

In the present invention, the trench is preferably a trench for filling the insulating film with a conductor for connecting a lower wiring and an upper wiring.

In the present invention, preferably, the trench is a trench used for damascene wiring.

In the present invention, the insulating film is preferably a film made of silicon oxide, silicon nitride, or a laminate of silicon oxide, silicon nitride, and silicon oxide.

In the present invention, the step of forming the trench by etching is preferably performed by a magnetron type reactive ion etching (RIE) apparatus.

The present invention also provides a step of forming a lower conductive layer on a semiconductor substrate or on a semiconductor substrate, a step of forming an insulating film on the lower conductive layer, and forming a lower conductive layer and an upper layer on the insulating film. to fill a conductor for connecting the conductive layer, as an etching gas, using at least C ₄ F ₈ or C ₃ F _8, CO, Ar and O _2, C ₄ F
₈ or C ₃ F ₈ flow rate 6-10 sccm, CO / A
The flow rate ratio of r is 10-20%, and the flow rate of O ₂ is 5-7 scc.
m and the total flow rate of the etching gas is 350 sccm or more.
There is also provided a method of manufacturing a semiconductor device including a step of forming a trench by etching at 400 sccm or less and a step of forming a conductive material so as to fill the trench.

In the method of manufacturing a semiconductor device according to the present invention, preferably, between the step of forming the trench and the step of forming a conductive material so as to fill the trench, a bottom portion and a side surface of the trench are further provided. Forming a contact metal layer.

As the conductive substance, aluminum,
A material mainly containing aluminum, copper, a material mainly containing copper, tungsten, a material mainly containing tungsten, a material mainly containing metal silicide such as tungsten silicide, and the like can be given.

Hereinafter, the present invention will be described in detail. The present invention is characterized in that a trench used as a connection hole for connecting a lower wiring and an upper wiring to an insulating film formed on a semiconductor substrate is formed by etching under a specific etching condition. A method for forming a semiconductor device, and a method for manufacturing a semiconductor device, comprising: after forming the trench, forming a conductive material so as to fill the trench.

According to the present invention, at least C ₄ F ₈ or C ₃ F ₈ , CO, Ar and O ₂ are used as an etching gas, the flow rate of C ₄ F ₈ is 6 to 10 sccm, and CO / A
The flow rate ratio of r is 10-20%, and the flow rate of O ₂ is 5-7 scc.
m and the total flow rate of the etching gas is 350 to 400 s
It is characterized in that the insulating film is etched at ccm or less.

Of the etching gas components, C ₄ F ₈
And C ₃ F ₈ are F sources, and the Depo during etching is
It is a system substance. The flow rate of C ₄ F ₈ and C ₃ F ₈ is 6-1
0 sccm is preferred. FIG. 11 shows the relationship between the change in the flow rate of C ₄ F ₈ , the etching rate, and the inclination angle of the trench side wall. In the figure, the horizontal axis represents the flow rate of C ₄ F ₈ (sccm),
The left side of the vertical axis shows the etching rate (nm / min), and the right side of the vertical axis shows the inclination angle (°) of the trench side wall. As is clear from this figure, C ₄ F ₈ (or C ₃ F
_If the flow rate in step ₈ ) is less than 6 sccm, the etching gas becomes insufficient and the etching rate drops extremely.

The reaction product (fluorocarbon compound) of C ₄ F ₈ (C ₃ F ₈ ) is also deposited on the underlying substrate, and also plays a role in improving the etching selectivity with the underlying substrate. .

Of the etching gas components, CO is a component that affects the selectivity of the etching gas between the insulating film and the underlying silicon substrate. Generally, the etching gas is C
When O is added, the selectivity and the etching rate tend to decrease. This is because the etching rate of the oxide insulating film decreases when the C / F ratio (ratio of the amount of carbon and fluorine) in the plasma is large.

In this respect, CO gas is used as the etching gas.
It can also be said that it is preferable not to add. However, when CO is not added, and when it is desired to form a contact hole having a high aspect ratio, such as when a trench is used as a contact hole, the etching rate in the hole is extremely reduced. This is considered to be affected by O atoms of CO and Ar used as a diluent gas. As described above, the mixing ratio and the flow rate of CO and Ar greatly affect the etching rate and the selectivity in the hole.

FIG. 12 shows the relationship between the mixing ratio of CO / Ar, the etching rate, and the microloading effect. In the figure, the left side of the vertical axis indicates the etching rate, the right side of the vertical axis indicates the etching rate ratio (selectivity) of the silicon oxide film and the silicon nitride film, and the horizontal axis indicates the O ₂ gas flow rate (sccm). As is clear from this figure, CO / Ar
Is preferably 10/100 to 20/100.
When the flow ratio (%) of CO / Ar is less than 10%, the etching rate is improved, but the etching rate in the fine trench (in the hole) is reduced. On the other hand, CO
If the flow rate ratio (%) of / Ar exceeds 20%, the etching rate becomes extremely slow, which is not preferable.

The microloading effect (μ-L
DG) causes a pattern shift due to a difference in etching rate between a portion having a large opening diameter and a portion having a small opening diameter. On the other hand, if it exceeds 10 sccm, a reaction product of C ₄ F ₈ (or C ₃ F ₈ ) adheres to the side wall at the time of etching, and the side wall inclination angle becomes small.

Of the etching gas components, O ₂ is
This is added to remove the reaction product of C ₄ F ₈ (C ₃ F ₈ ), which is a Depo-based substance, from adhering to the side wall. The flow rate of O ₂ is preferably 5 to 7 sccm. FIG. 13 shows the relationship between the flow rate of O _2, the etching rate, and the selectivity between the silicon oxide film and the silicon nitride film. In the figure,
The horizontal axis indicates the O ₂ gas flow rate (sccm), the left vertical axis indicates the etching rate (nm / min), and the left vertical axis indicates the etching rate ratio (selectivity) of the silicon oxide film and the silicon nitride film. As is apparent from this figure, O
_When the flow rate of ₂ is less than 5 sccm, the removal effect is poor, and when it exceeds 7 sccm, C ₄ F ₈ (C ₃ F) which plays a role of improving the etching selectivity with the underlying substrate is used.
₈ ) The protective film made of the reaction product (fluorocarbon) is etched, which causes a decrease in the selectivity.

In the present invention, the total flow rate of the etching gas is preferably 350 sccm to 400 sccm, more preferably 361 to 167 sccm. When the total flow rate of the etching gas is less than 350 sccm, it is difficult to perform the etching at a high speed, while the etching flow is 400 s.
If it exceeds ccm, the etching proceeds excessively, and the selectivity to the underlying substrate deteriorates.

As described above, the present invention is a technique for forming a trench by performing etching at a specific flow rate using an etching gas having a specific mixing ratio. It is possible to form a trench having a diameter substantially the same as that of the bottom surface.

[0043]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in more detail with reference to embodiments. First, FIG. 14 schematically shows a magnetron-type RIE apparatus that can be used in the following embodiments.
In this method, for example, an RF bias of 13.56 MHz is applied to the upper electrode (susceptor) 8 from a high-frequency power source, and plasma is formed by the magnetic field (120 gauss) of the magnet 4 disposed right beside the chamber. Especially,
Since the magnet 4 is arranged right beside the chamber, a horizontal magnetic field is formed with respect to the wafer, and the magnetic field has a distribution to keep Vdc constant. The wafer 1 being etched is fixed on the lower electrode by a monopolar electrostatic chuck. The wafer cooling mechanism is provided with a system of the wafer backside cooling gas 13 and 14 on the lower electrode, which independently controls the center and the edge, respectively. The lower electrode is a coolant (for example, (Product name: Florinert) is circulated.

The present invention is characterized by etching conditions, and is preferably carried out by the above-described etching apparatus. However, other etching apparatuses may be used without departing from the gist of the present invention. It is of course possible to use it.

First Embodiment A first embodiment of the present invention will be described with reference to the drawings. In the first embodiment, the present invention is applied to a case where an element isolation region and a diffusion layer are formed in a semiconductor substrate, and a trench for a backing wiring is formed on the diffusion layer and in an interlayer insulating film formed thereon. Is applied.

First, as shown in FIG. 1A, a LOCOS (Local) is formed on an n-type semiconductor substrate 101, for example.
An element isolation film 102 is formed by an Oxidation on Silicone method. Then, BF ₂ ⁺ ions, for example, at 35 keV and 3E15 ions are formed on the element isolation region and in a region where a contact hole is to be formed.
/ Cm ² and ion implantation at 90 ° C.
The impurity diffusion layer 103 is formed by performing a heat treatment (thermal annealing) at 0 ° C. for 10 minutes.

Next, a low pressure CVD method (Chemical
Vapor Deposition method)
An interlayer insulating film 104 is formed to a thickness of 1000 nm over the entire surface by using an OS (Tetraethoxy silicon).

Next, a photoresist film 105 is formed on the entire surface of the diffusion layer 103, and patterning for forming a trench is performed. The trench pattern 106
For example, the width is 0.3 μm, the length is 0.5 μm, and the length is 40 μm.

Next, etching is performed under the following conditions to form a trench shown in FIG. (Etching conditions) Apparatus: magnetron type RIE apparatus Etching gas: C ₄ F ₈ / CO / Ar / O ₂ = 8/5
0/300/5 sccm Pressure: 5.3 Pa RF Power: 1700 W Electrode spacing: 27 mm Electrode temperature: top / sidewall / bottom = 60/60/20 ° C. Wafer back pressure (center / edge) = 9.3 / 53.
3hPa 20% overetch rate

By this etching, the side wall inclination angles α and β of the trench were 87.5 to 88.5 °, the shaved amount a of the base silicon substrate was about 40 nm, and b was about 40 nm. Also, the etching rate in the fine trench is
It was 430 nm / min. Conventional conditions (C ₄ F ₈ /
CO / Ar / O ₂ = 8/150/200/3 sccm,
RF Power = 1700 W, pressure = 5.3 Pa, etching rate in fine trench = 360 nm / mi
Compared to n), the etching rate is improved by about 20%.

Thereafter, as shown in FIG.
After forming the adhesion layer metal 107 and performing lamp annealing, a burying metal 108 such as tungsten is formed, and a buried wiring is formed by, for example, an entire etch-back method by reactive ion etching. it can.

The conditions for forming the buried wiring are as follows, for example. (Formation conditions of embedded wiring) Adhesion layer metal sputter: Collimated Ti = 30 nm
(0.52 Pa, 8 kW, Ar = 35 sccm, 300
° C) + TiN = 70 nm (0.78 Pa, 6 kW, Ar
= 35 sccm, 300 ° C.) Lamp annealing: 650 ° C., 1 atm, N ₂ = 100
%, 30 sec Blanket tungsten (W) CVD: 600 nm
(10.7 kPa, WF ₆ / H ₂ / Ar / He = 40 /
400 / 2250sccm, 450 ° C) W etch back: 1st step (W etching) 4
5.5 Pa, 275 W, SF ₆ / Ar / He = 110 /
90/5 sccm 2ed step (TiN etching) 6.5 Pa, 2
50W, Ar / Cl ₂ = 75/5 sccm 3rd step (W over etching) 32.5P
a, 70W, SF ₆ / Ar / He = 20/10 / 1sc
cm

As described above, according to the present embodiment, trenches can be formed by high-speed and vertical etching under favorable etching conditions as compared with the prior art, and good wiring plugs can be formed. .

Second Embodiment The second embodiment is an example in which each diffusion layer is applied to a step of forming a local wiring connecting a word line. First, as shown in FIG. 3A, an element isolation film 202 is formed on an n-type silicon semiconductor substrate 201 by, for example, a LOCOS method, and a diffusion layer 203, an insulating film 210, a word line 211, and a stopper A silicon nitride (Si ₃ N ₄ ) film 209 and the like are sequentially formed by, for example, a low pressure CVD method. Next, an interlayer insulating film 204 is formed on the entire surface by, for example, a normal pressure CVD method.

Thereafter, CMP (Chemical Me
The interlayer insulating film 204 is flattened by a chemical polishing method, a photoresist film 205 is formed on the entire surface, and patterning for forming a trench is performed. The pattern 206 of the trench is, for example, 0.4 μm in diameter, 40 μm in length, and 0.3 μm in length.

The method of forming each layer in the above steps is, for example, as follows. (Structure and forming method of each layer described above) Formation of diffusion layer: BF ₂ ⁺ ion implantation (35 keV, 3E
15 ions / cm ² ), 900 ° C. under N ₂ atmosphere,
Word line structure: CVD film made of doped polysilicon with a thickness of 100 nm + high-temperature WSi film with a thickness of 100 nm Stopper Formation of Si ₃ N ₄ film: SiH ₂ Cl ₂ / NH
₃ / N ₂ = 50/200/200 sccm, pressure = 70
Pa, formed at a substrate temperature of 760 ° C. Formation of a 50 nm-thick interlayer insulating film: TEOS = 10 sccm, O ₃ flow rate = 750
mg / min, temperature = 380 ° C., by ordinary CVD. Thickness: 1000 nm Interlayer insulating film flattening (CMP) condition: 300 nm polishing,
Polishing plate rotation speed = 20 rpm, wafer holding sample stage rotation speed = 20 rpm, polishing pressure = 500 gf / cm ² ,
Polishing liquid = silica particles (14 wt%) + KOH aqueous solution

Next, etching is performed under the following conditions to form a trench shown in FIG. (Etching conditions for interlayer insulating film) Etching device: magnetron type RIE device Etching gas: C ₄ F ₈ / CO / Ar / O ₂ = 8/5
0/300/5 sccm Pressure: 5.3 Pa RF Power: 1700 W Electrode spacing: 27 mm Electrode temperature: upper / sidewall / lower = 60/60/20 ° C. Wafer back pressure (center / edge) = 9.3 / 53 /
3 hPa overetch rate: 20%

(Etching conditions for stopper Si ₃ N ₄ film) Etching device: magnetron type RIE device Etching gas: CHF ₃ / CO / O ₂ = 40/160
/ 14 sccm Pressure: 5.3 Pa RF Power: 1000 W Electrode interval: 27 mm Electrode temperature: Top / sidewall / bottom = 60/60/20 ° C. Wafer back pressure (center / edge) = 9.3 / 53.
3Pa overetch rate: 10%

By this etching, the inclination angles γ and δ of the side walls of the trench are 87.5 to 88.5 ° and the underlying WSi
The shaved amount c of the _X film was about 20 nm, and the shaved amount d of the underlying silicon film was about 40 nm.

Thereafter, as shown in FIG. 4D, an adhesion layer metal layer 207 is formed, and after lamp annealing,
A buried metal 208 is formed, and a buried wiring can be formed by, for example, an entire surface etch-back method by reactive ion etching.

The conditions for forming the embedded metal wiring are, for example, as follows. (Formation conditions of embedded metal wiring) Adhesion layer metal sputter: Collimated Ti = 30 nm
(0.52 Pa, 8 kW, Ar = 35 sccm, 300
° C) + TiN = 70 nm (0.78 Pa, 6 kW, N ₂
/ Ar = 42/21 sccm, 300 ° C.) Lamp annealing: 650 ° C., 1 atm, N ₂ = 100
%, 30 sec Blanket tungsten (W) CVD: 600 nm
(10.7 kPa, WF ₆ / H ₂ / Ar / He = 40 /
400/2250 sccm, 450 ° C.) W etchback: 1st step (etching of W) 45.5 Pa, 275 W, SF ₆ / Ar / He = 1
10/90/5 sccm 2nd step (TiN etching) 6.5 Pa,
250 W, Ar / Cl ₂ = 75/5 sccm 3rd step (W over etching) 32.5
Pa, 70W, SF ₆ / Ar / He = 20/10 / 1s
ccm

As described above, according to the present embodiment, trenches for forming wiring plugs can be formed at high speed and vertically by etching under favorable conditions, and good wiring plugs can be formed.

Third Embodiment A third embodiment is an example in which the present invention is applied to a step of forming a local wiring connecting each diffusion layer and a word line, as in the second embodiment. First, as shown in FIG. 5A, an element isolation film 302 is formed on an n-type silicon semiconductor substrate 301 by, for example, a LOCOS method, and then a diffusion layer 303 and a stopper Si ₃ N ₄ film 309 are respectively formed. It is formed by a low pressure CVD method.

Next, an interlayer insulating film 304 is formed on the entire surface to a thickness of 1000 nm by, for example, a low pressure CVD method, and then a photoresist film 305 is formed on the entire surface, and then subjected to predetermined patterning for trench formation. Perform The trench pattern 306 has a width of 0.3 μm and a length of 10 μm
And 40 μm.

The structure and forming method of each of the above-mentioned layers are as follows, for example.
It is as follows. (Structure and forming method of each layer described above) Formation of diffusion layer: BF ₂ ⁺ ion implantation (35 keV, 3E
15 ions / cm ² ) Formation of stopper Si ₃ N ₄ film: 50 nm thick, SiH
₂ Cl ₂ / NH ₃ / N ₂ = 50/200 / 200scc
m, pressure = 70 Pa, substrate temperature = 760 ° C. Deposition of interlayer insulating film: low-pressure CVD using TEOS

Next, etching is performed under the following conditions to form a trench shown in FIG. (Etching conditions for interlayer insulating film) Etching device: magnetron type RIE device Etching gas: C ₄ F ₈ / CO / Ar / O ₂ = 8/5
0/300/5 sccm Pressure: 5.3 Pa RF Power: 1700 W Electrode spacing: 27 mm Electrode temperature: top / sidewall / bottom = 60/60/20 ° C. Wafer back pressure (center / edge) = 9.3 / 53.
3 hPa overetch rate: 20%

(Etching conditions for stopper Si ₃ 4 ₄ film) Etching device: magnetron type RIE device Etching gas: CHF ₃ / CO / O ₂ = 40/160
/ 14 sccm Pressure: 5.3 Pa RF Power: 1000 W Electrode interval: 27 mm Electrode temperature: Top / sidewall / bottom = 60/60/20 ° C. Wafer back pressure (center / edge) = 9.3 / 53.
3Pa overetch rate: 10%

By this etching, the inclination angle ε of the side wall of the trench is 87.5 °, and the shaving amount e of the underlying silicon film is set.
Was about 20 nm.

Thereafter, as shown in FIG. 6C, an adhesion layer metal 307 is formed, a lamp anneal is performed, a buried metal 308 is formed, and the entire surface is etched back by, for example, reactive ion etching. A buried wiring is formed by the method.

The conditions for forming the buried metal wiring are, for example, as follows. (Formation conditions of embedded metal wiring) Adhesion layer metal sputter: Collimated Ti = 30 nm
(0.52 Pa, 8 kW, Ar = 35 sccm, 300
° C) + TiN = 70 nm (0.78 Pa, 6 kW, N ₂
/ Ar = 42/21 sccm, 300 ° C.) Lamp annealing: 650 ° C., 1 atm, N ₂ = 100
%, 30 sec Blanket tungsten (W) CVD: 600 nm
(10.7 kPa, WF ₆ / H ₂ / Ar / He = 40 /
400/2250 sccm, 450 ° C.) W etchback: 1st step (etching of W) 45.5 Pa, 275 W, SF ₆ / Ar / He = 1
10/90/5 sccm 2nd step (TiN etching) 6.5 Pa,
250 W, Ar / Cl ₂ = 75/5 sccm 3rd step (W over etching) 32.5
Pa, 70W, SF ₆ / Ar / He = 20/10 / 1s
ccm

As described above, according to the present embodiment, trenches for forming wiring plugs can be formed at high speed and vertically by etching under favorable conditions, and good wiring plugs can be formed.

Fourth Embodiment The fourth embodiment is an example in which the present invention is applied to a damascene wiring. First, as shown in FIG. 7A, an interlayer insulating film 404 is formed on an n-type silicon semiconductor substrate (not shown) to a thickness of 800 by, for example, a low pressure CVD method using TEOS.
nm. Next, a photoresist film 40 is formed on the entire surface.
After the film 5 is formed, predetermined patterning for trench processing is performed. In this case, the trench pattern 406 can have, for example, a width of 0.2 μm and a length equal to the length of the aluminum wiring.

Next, etching is performed under the following conditions, and FIG.
A trench shown in (b) is formed. (Etching conditions for interlayer insulating film) Etching apparatus: magnetron type RIE apparatus Etching gas: C ₄ F ₈ / CO / Ar / O ₂ = 8/5
0/300/7 sccm Pressure: 5.3 Pa RF Power: 1700 W Electrode spacing: 27 mm Electrode temperature: upper / side wall / lower = 60/60/20 ° C. Wafer back pressure (center / edge) = 9.3 / 53.
3hPa

The side wall inclination angle θ of the trench formed by this etching is 88 °, and the depth of the trench is about 40 °.
It was 0 nm.

Thereafter, as shown in FIG. 7C, a film of copper 408 as a wiring material is formed to a thickness of 500 nm, subjected to a reflow treatment, and then polished by aluminum CMP.

As described above, according to the present embodiment, the trench for the damascene wiring can be etched at high speed and vertically under favorable conditions, and a good damascene wiring can be formed.

Fifth Embodiment The fifth embodiment is an example in which the present invention is applied to the formation of a damascene wiring as in the fourth embodiment. First, FIG.
As shown in (1), a laminated film (ONO film) 504 composed of silicon oxide 512-silicon nitride 513-silicon oxide 514 is formed on an n-type silicon semiconductor substrate. continue,
A photoresist film 505 is formed on the entire surface, and patterning for forming a trench is performed. The trench pattern 506
Is 0.2 μm in width and the length is the same as the wiring length of the aluminum wiring.

The structure and forming method of each of the above-mentioned layers are as follows, for example.
It is as follows. (Structure and Forming Method of Each Layer) Formation of First Silicon Oxide Film: 600 nm thick, TEO
Low pressure CVD using S. Deposition of silicon nitride film: 50 nm thick, low pressure VD method Deposition of second silicon oxide film: 500 nm, TEO
Low pressure CVD method using S

Next, etching is performed under the following conditions to form a trench shown in FIG. (Etching conditions for interlayer insulating film) Etching device: magnetron type RIE device Etching gas: C ₄ F ₈ / CO / Ar / O ₂ = 8/5
0/300/5 sccm Pressure: 5.3 Pa RF Power: 1700 W Electrode spacing: 27 mm Electrode temperature: top / sidewall / bottom = 60/60/20 ° C. Wafer back pressure (center / edge) = 9.3 / 53.
3 hPa overetch rate: 20%

The side wall inclination angle η of the trench formed by this etching is 88 °, and the depth f of the trench is 5 °.
It was 50 nm.

Then, as shown in FIG. 8C, a damascene wiring is formed by forming a wiring material of copper 508 to a thickness of 500 nm, performing a reflow treatment, and polishing the aluminum by aluminum CMP. Can be.

As described above, according to the present embodiment, the trench for the damascene wiring can be etched at a high speed and vertically under favorable conditions, and a good damascene wiring can be formed.

Although the present invention has been described with reference to the above-described five embodiments, it should be understood that the present invention should not be limited to the above-described embodiments, but may include a plasma source, a device configuration, a wiring structure, and an etching gas. The etching conditions such as the mixing ratio, etching temperature, and pressure can be appropriately selected without departing from the gist of the present invention.

[0084]

The present invention is used for a connection hole between conductive layers of a semiconductor device, for example, a connection hole for connecting a conductive layer of a semiconductor substrate and an upper wiring, and a connection hole for connecting a lower wiring and an upper wiring. A method for forming a trench in an insulating film and a method for forming a buried wiring layer such as a backing wiring and a damascene wiring formed by burying a conductive material in the trench.

According to the present invention, the trench can be formed by high-speed and vertical etching. Therefore, the connection hole can be formed according to the pattern by the manufacturing method of the present invention.

Therefore, a highly reliable semiconductor device having a finely structured wiring layer can be manufactured with good yield and high efficiency.

[Brief description of the drawings]

FIG. 1 is a sectional view of a main process in a manufacturing process according to a first embodiment. (A) is a diagram in which a resist film is formed and predetermined patterning is performed, and (b) is a diagram in which a trench is formed by the trench forming method of the present invention.

FIG. 2 is a cross-sectional view illustrating main processes of a manufacturing process according to the first embodiment. (C) is a diagram in which an embedded wiring is formed.

FIG. 3 is a cross-sectional view illustrating main processes of a manufacturing process according to a second embodiment. (A) is a diagram in which an interlayer insulating film is formed on the entire surface, and (b) is a diagram in which a resist film is formed and predetermined patterning is performed.

FIG. 4 is a cross-sectional view illustrating main processes of a manufacturing process according to a second embodiment. (C) is a diagram in which a trench is formed by the trench forming method of the present invention, and (d) is a diagram in which a buried wiring is formed.

FIG. 5 is a sectional view of a main process in a manufacturing process according to a third embodiment. (A) is a diagram in which a resist film is formed and predetermined patterning is performed, and (b) is a diagram in which a trench is formed by the trench forming method of the present invention.

FIG. 6 is a cross-sectional view showing main processes in a manufacturing process according to a third embodiment. (C) is a diagram in which an embedded wiring is formed.

FIG. 7 is a sectional view of a main process in a manufacturing process of a fourth embodiment. (A) is a diagram in which a resist film is formed and predetermined patterning is performed; (b) is a diagram in which a trench is formed by the trench forming method of the present invention;
(C) is a diagram in which an embedded wiring is formed.

FIG. 8 is a sectional view of a main process in a manufacturing process according to a fifth embodiment. (A) is a diagram in which a resist film is formed and predetermined patterning is performed; (b) is a diagram in which a trench is formed by the trench forming method of the present invention;
(C) is a diagram in which an embedded wiring is formed.

FIG. 9 is a sectional view of a main step in the formation of a buried interconnect according to a conventional method. FIG. 3A is a diagram in which a resist film is formed and predetermined patterning is performed, and FIG.
FIG. 3 is a view showing a trench formed by the trench forming method of the present invention.

FIG. 10 is a sectional view of a main step in the formation of a buried wiring according to a conventional method. (C) is a diagram in which an embedded wiring is formed.

FIG. 11 is a diagram showing a relationship between a change in the flow rate of C ₄ F ₈ and an etching rate and a taper angle.

FIG. 12 is a diagram showing a relationship between a change in a mixing ratio of CO and Ar gas, an etching rate, and a micro-rowing effect.

FIG. 13 is a diagram showing a relationship between a change in the flow rate of O ₂ gas, an etching rate, and a selectivity in etching of a silicon oxide film and a silicon nitride film.

FIG. 14 is a schematic diagram of a magnetron-type RIE apparatus that can be used for carrying out the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Wafer, 2 ... Focus ring, 3 ... Insulator ring (quartz), 4 ... Magnet, 5 ... Deposit shield, 6 ...
Baffle plate, 7: lower electrode, 8: upper electrode, 9: process gas, 10: lifter mechanism, 11: refrigerant pipe for cooling lower electrode, 12: cooling gas (edge) for wafer back surface, 13 ...
Wafer backside cooling gas (center), 14 ... pressure gauge, 10
1,201,301,601 ... silicon semiconductor substrate, 1
02, 202, 302, 602 ... element isolation film, 103,
203, 303, 603: impurity diffusion regions, 104, 2
04, 304, 404, 504, 604 ... interlayer insulating film,
105, 205, 305, 405, 505, 605 ... photoresist film, 106, 206, 306, 406, 5
06,606 ... Trench pattern, 107,207,3
07,607 ... adhesion metal layer, 108,208,30
8, 408, 508, 608: metal for embedding (for wiring), 209: etch stopper film, 210, 309: insulating film, 211: word line, 512, 514: silicon oxide film, 513: silicon nitride film, α, β, γ, δ, ε,
θ, η, A, B ... taper angles, a, b, c, d, e,
g, h: amount of substrate scraping, f: depth of trench

Claims (17)

[Claims] 1. A method for forming a trench, comprising: forming a trench for filling a conductor in an insulating film by etching to connect a lower conductive layer and an upper conductive layer laminated with an insulating film interposed therebetween. In the step of forming the trench by etching, at least C ₄ F ₈ or C ₃ F ₈ is used as an etching gas.
And CO, Ar and O ₂ , using C ₄ F ₈ or C ₃
Flow rate F ₈ is 6~10sccm, CO / flow ratio of Ar 10 to 20% at a flow rate of O ₂ is 5～7Sccm, and total flow rate of etching gas 350sccm~400scc
m, which is a step of performing etching at a depth of not more than m. 2. The method according to claim 1, wherein the trench is a trench for filling the insulating film with a conductor for connecting a conductive layer formed on a semiconductor substrate and an upper wiring. . 3. The method according to claim 1, wherein the trench is a trench for filling the insulating film with a conductor to connect a lower wiring and an upper wiring. 4. The method according to claim 1, wherein the trench is a trench used for damascene wiring. 5. The method according to claim 1, wherein the insulating film is a film made of silicon oxide. 6. The method according to claim 1, wherein the insulating film is a film made of silicon nitride. 7. The method for forming a trench according to claim 1, wherein the insulating film is a film made of a stacked body of silicon oxide, silicon nitride, and silicon oxide. 8. The method according to claim 1, wherein the step of forming the trench by etching is performed by a magnetron reactive ion etching (RIE) apparatus. 9. A step of forming a lower conductive layer on a semiconductor substrate or on a semiconductor substrate; a step of forming an insulating film on the lower conductive layer; and forming a lower conductive layer and an upper conductive layer on the insulating film. As an etching gas to fill the conductor to connect
At least C ₄ F ₈ or C ₃ F ₈ , CO, Ar and O ₂ are used, and the flow rate of C ₄ F ₈ or C ₃ F ₈ is 6-1.
0 sccm, CO / Ar flow rate ratio 10-20%, O ₂
A step of forming a trench by etching at a flow rate of 5 to 7 sccm and a total flow rate of etching gas of 350 sccm to 400 sccm or less, and a step of forming a conductive material so as to fill the trench. Manufacturing method. 10. The method according to claim 10, further comprising, between the step of forming the trench and the step of forming a conductive material so as to fill the trench, a step of forming an adhesion metal layer on the bottom and side surfaces of the trench. 10. The method for manufacturing a semiconductor device according to item 9. 11. The manufacturing of a semiconductor device according to claim 9, wherein said trench is a trench for filling said insulating film with a conductor for connecting a conductive layer formed on a semiconductor substrate and an upper layer wiring. Method. 12. The method of manufacturing a semiconductor device according to claim 9, wherein said trench is a trench for filling said insulating film with a conductor for connecting a lower wiring and an upper wiring. 13. The method of manufacturing a semiconductor device according to claim 9, wherein said trench is a trench used for damascene wiring. 14. The method according to claim 9, wherein the insulating film is a film made of silicon oxide. 15. The method according to claim 9, wherein the insulating film is a film made of silicon nitride. 16. The method for forming a trench according to claim 9, wherein said insulating film is a film made of a laminate of silicon oxide, silicon nitride, and silicon oxide. 17. The method according to claim 10, wherein the adhesion metal layer is a layer made of silicon nitride.