CN110571150B - Etching method of high-aspect-ratio opening and semiconductor device - Google Patents
Etching method of high-aspect-ratio opening and semiconductor device Download PDFInfo
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- CN110571150B CN110571150B CN201910866100.5A CN201910866100A CN110571150B CN 110571150 B CN110571150 B CN 110571150B CN 201910866100 A CN201910866100 A CN 201910866100A CN 110571150 B CN110571150 B CN 110571150B
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- 238000005530 etching Methods 0.000 title claims abstract description 137
- 238000000034 method Methods 0.000 title claims abstract description 38
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Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
- H01L2221/1005—Formation and after-treatment of dielectrics
- H01L2221/101—Forming openings in dielectrics
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- General Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Drying Of Semiconductors (AREA)
Abstract
The invention relates to an etching method of a high-aspect-ratio opening and a semiconductor device. The etching method of the high aspect ratio opening comprises the following steps: and carrying out dry etching on the dielectric layer by using a feed gas comprising an etching gas, an oxygen source gas and an inert carrier gas to form an opening, wherein the inert carrier gas accounts for 4-21% of the flow of the feed gas.
Description
Technical Field
The present invention relates to semiconductor manufacturing methods, and more particularly, to an etching method for a high aspect ratio opening and a semiconductor device.
Background
The opening etching is a key technology of a super-large-scale integrated circuit, and as a CMOS device enters a process age after 32nm, the high-aspect-ratio opening etching and the filling thereof have a considerable influence on the yield of the device. For advanced memories, aspect ratios have reached ratios above 40:1, which makes the challenge even greater.
In semiconductor devices such as NAND memory, DRAM memory or CMOS devices, the medium in which the openings are etched is typically silicon dioxide (SiO) 2 ) Silicon nitride (SixNy, e.g. Si) 3 N 4 ) And an insulating layer such as silicon oxynitride (SiOxNy). The opening may be a hole or a trench. The dimensions of the holes in both horizontal directions are similar or of the same order of magnitude. For a trench (trench), its dimension in one horizontal direction is significantly larger than the dimension in the other horizontal direction, e.g. by one or more orders of magnitude.
In the etching of the high aspect ratio opening, the opening profile is not ideal, for example, there are problems of opening bending (bending), and stripe generation (deformation) on the side wall of the opening. In addition, when the aspect ratio of the opening is further increased, the etching capability is lowered and the predetermined depth cannot be reached.
Disclosure of Invention
The invention provides an etching method of a high-aspect-ratio opening, which can improve the etching capability and solve the problems of opening bending, stripes and the like.
The invention adopts the technical scheme that the etching method for the opening with the high depth-to-width ratio comprises the following steps: and carrying out dry etching on the dielectric layer by using a feed gas comprising an etching gas, an oxygen source gas and an inert carrier gas to form an opening, wherein the inert carrier gas accounts for 4-21% of the flow of the feed gas.
In one embodiment of the invention, the inert carrier gas is selected from one or more of the following combinations: helium (He), neon (Ne), argon (Ar), krypton (Kr), and xenon (Xe).
In an embodiment of the present invention, the etching gas includes: one or more of fluorocarbons; and/or one or more of hydrofluorocarbons.
In one embodiment of the present invention, the etching gas comprises a compound of formula C 3 One or more of HxFy's gases, where x is an integer between 0 and 8, y is an integer between 0 and 8, and x + y is 8.
In an embodiment of the invention, a material of the dielectric layer includes silicon oxide, silicon oxynitride, hafnium oxide, or zirconium oxide.
In an embodiment of the invention, the material of the dielectric layer includes nitride.
In an embodiment of the invention, the thickness of the polymer layer deposited along the sidewall of the opening during the etching is between 0.5 and 4 nm.
In an embodiment of the invention, an aspect ratio of the opening is greater than 15: 1.
In an embodiment of the present invention, the dielectric layer is a single dielectric layer or a composite dielectric layer; the composite dielectric layer comprises a plurality of vertically stacked dielectric layers, wherein in two adjacent dielectric layers, one dielectric layer is made of silicon oxide, hafnium oxide or zirconium oxide, and the other dielectric layer is made of silicon nitride or silicon oxynitride.
The invention also provides a semiconductor device, which comprises a substrate and a dielectric layer positioned above the substrate, wherein an opening with a high depth-to-width ratio is formed in the dielectric layer, the opening is formed by dry etching the dielectric layer by using the feed gas of etching gas, oxygen source gas and inert carrier gas, and the inert carrier gas accounts for 4-21% of the flow of the feed gas.
In an embodiment of the present invention, the semiconductor device further includes: a fill layer located within the opening.
In one embodiment of the invention, the inert carrier gas is selected from one or more of the following combinations: helium (He), neon (Ne), argon (Ar), krypton (Kr), and xenon (Xe).
In an embodiment of the present invention, the etching gas includes: one or more of a fluorocarbon; and/or one or more of hydrofluorocarbons.
In one embodiment of the present invention, the etching gas comprises a compound of formula C 3 One or more of HxFy's gases, where x is an integer between 0 and 8, y is an integer between 0 and 8, and x + y is 8.
In an embodiment of the invention, a material of the dielectric layer includes silicon oxide, hafnium oxide, or zirconium oxide.
In an embodiment of the invention, the material of the dielectric layer comprises nitride.
In an embodiment of the invention, the thickness of the polymer layer deposited along the sidewall of the opening during the etching is between 0.5 and 4 nm.
In an embodiment of the present invention, the dielectric layer is a single dielectric layer or a composite dielectric layer; the composite dielectric layer comprises a plurality of vertically stacked dielectric layers, wherein in two adjacent dielectric layers, one dielectric layer is made of silicon oxide, hafnium oxide or zirconium oxide, and the other dielectric layer is made of silicon nitride or silicon oxynitride.
Compared with the prior art, the invention adds a proper amount of inert carrier gas, and the inert carrier gas is difficult to ionize, so that the ion concentration can be reduced, the expansion chance is reduced, the plasma temperature is reduced, and the ion energy is increased. On the other hand, the inert carrier gas is used as an electrically neutral gas, is not easily influenced by charges in the dielectric layer, and can bring etching ions to a deeper surface, thereby being more beneficial to etching with a high aspect ratio. Thanks to the increased ion energy and easier access to deeper surfaces, the etching capacity is improved, while the negative effects on the sidewalls of the openings, such as bending (bowing), tilting (tilting), twisting (distortion) and striation (deformation) are also smaller.
Further, the etching gases of one aspect of the present invention are based on carbon chains of 3 carbon atoms, so that it is easy to precisely control the ratio of carbon, hydrogen and fluorine in the gases, thereby enabling precise control of the balance between adsorbed radicals and etching ions. In particular, when the etching gas comprises a mixture of a plurality of the above gases, which is often the case, the same carbon chain gas molecules will be more or less plasmatized, and thus more evenly distributed throughout the opening, which also facilitates the control of the ratio of carbon, hydrogen and fluorine. Using an etching gas of this general formula, a more uniform and thinner polymer layer can be maintained during etching, resulting in better inside profile of the opening and better etching capability.
Drawings
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below, wherein:
FIG. 1 is a partial cross-sectional view of a semiconductor structure requiring etching in accordance with one embodiment of the present invention.
FIG. 2 is a partial cross-sectional view of a semiconductor structure requiring etching according to another embodiment of the present invention.
Fig. 3 is a flowchart of a method for etching a high aspect ratio opening according to an embodiment of the invention.
Fig. 4 is a cross-sectional view of the semiconductor structure shown in fig. 1 after etching to form an opening.
Fig. 5 is a cross-sectional view of the semiconductor structure shown in fig. 2 after etching to form an opening.
Fig. 6 is a cross-sectional view of the semiconductor structure shown in fig. 1 and 2 after etching to form an opening.
Fig. 7 is a schematic diagram of a conventional etching method resulting in under-etching of the bottom of an opening during etching.
Fig. 8 is a schematic view of a conventional etching method resulting in bending of an opening during etching.
Fig. 9 is a schematic illustration of a conventional etching method resulting in twisting of the opening during etching.
Fig. 10 is a schematic illustration of a conventional etching method resulting in roughness of the sidewalls of the opening during etching.
Detailed Description
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, but the present invention may be practiced in other ways than those specifically described herein, and thus the present invention is not limited to the specific embodiments disclosed below.
As used in this application and in the claims, the terms "a," "an," "the," and/or "the" are not intended to be inclusive in the singular, but rather are intended to include the plural, unless the context clearly dictates otherwise. In general, the terms "comprises" and "comprising" are intended to cover only the explicitly identified steps or elements as not constituting an exclusive list and that the method or apparatus may comprise further steps or elements.
In describing embodiments of the present invention in detail, the cross-sectional views illustrating the device structures are not enlarged partially in general scale for convenience of illustration, and the schematic views are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.
For convenience in description, spatial relational terms such as "below," "beneath," "below," "under," "over," "upper," and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these terms of spatial relationship are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary words "below" and "beneath" can encompass both an orientation of up and down. The device may have other orientations (rotated 90 degrees or at other orientations) and the spatial relationship descriptors used herein should be interpreted accordingly. Further, it will also be understood that when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.
In the context of this application, a structure described as having a first feature "on" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed in between the first and second features, such that the first and second features may not be in direct contact.
It will be understood that when an element is referred to as being "on," "connected to," "coupled to" or "contacting" another element, it can be directly on, connected or coupled to or contacting the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly on," "directly connected to," "directly coupled to" or "directly contacting" another element, there are no intervening elements present. Similarly, when a first component is said to be "in electrical contact with" or "electrically coupled to" a second component, there is an electrical path between the first component and the second component that allows current to flow. The electrical path may include capacitors, coupled inductors, and/or other components that allow current to flow even without direct contact between the conductive components.
As used herein, the term "high aspect ratio" refers to a depth to width (or diameter) ratio of about 15:1 or higher.
As mentioned above, in the current etching of high aspect ratio openings, the opening profile is not ideal.
Taking a silicon dioxide dielectric layer as an example, generally, a standard process for etching silicon dioxide uses a fluorocarbon-based gas plasma. Dissociation of the fluorocarbon molecules by the action of the plasma generates reactive radicals and/or ions which act on the silicon dioxide. For example, in some high density plasmas, from CF 3 And other CxFy radical-generated CF + 、CF 2+ And CF 3+ The ions are the primary etch ions for silicon dioxide and are less fluorinated radicals (e.g., CF) 2 And CF) adsorb onto the sidewall and bottom surfaces in the silicon dioxide material openings during the etching process and polymerize to form an ion etch inhibiting non-volatile fluoropolymer layer.
For silicon nitride, a fluorocarbon-based gas and a hydrofluorocarbon-based gas plasma are used for etching. The hydrogen-carbon-fluorine-based gas can be used for chemically etching the silicon nitride film, and the etching speed is improved.
During the above etching process, polymer accumulation may hinder etching and even cause etching stop. However, as the plasma temperature rises, the opening profile is not ideal, and there are problems such as opening bending (bending) and striation (deformation) of the opening sidewall. In addition, when the aspect ratio of the opening is further increased, the etching capability is lowered and the predetermined depth cannot be reached.
Embodiments of the invention relate to methods of plasma etching doped and undoped dielectric materials used in semiconductor device processing to create openings to fabricate high aspect ratio contacts or capacitors. The present invention provides a method for etching high aspect ratio openings that can improve etch performance and reduce the negative impact on the sidewalls of the openings by increasing ion energy and ion transport to deeper surfaces within the openings.
FIG. 1 is a partial cross-sectional view of a semiconductor structure requiring etching according to one embodiment of the invention. Referring to fig. 1, a semiconductor structure 100a includes an insulating or dielectric layer 102 formed on a substrate 101, and active regions or elements 103 (e.g., diffusion regions, contact regions, conductive lines, etc.).
The dielectric layer 102 may be formed of undoped silicon dioxide (SiO) 2 ) Or doped SiO 2 Formed in a single layer or multiple layers. Dielectric layer 102 may also be a nitride (e.g., Si) 3 N 4 Silicon nitride (SixNy)) or silicon oxynitride (SiOxNy). The dielectric layer 102 may be a high-K (dielectric constant) material, such as hafnium oxide (HfO) 2 ) And zirconium oxide (ZrO) 2 )。
The material of the substrate 101 is different from the dielectric layer 102. In general, substrate 101 has a high etch selectivity to dielectric layer 102. For example, the substrate 101 may be a layer of doped silicon dioxide, a layer of silicon such as monocrystalline or polycrystalline silicon, a region of doped silicon, a metal silicide such as titanium silicide, a metal interconnect, or other layer of material, as opposed to the dielectric layer 102, such as silicon dioxide. In one example, the substrate 101 is silicon and the active region or element region 103 is provided in the substrate 101. The material of the active region or element 103 may be polysilicon. As another example, the surface of the substrate 101 may have a refractory metal nitride layer such as titanium nitride, tungsten nitride, etc. different from the dielectric layer 102, such as silicon nitride, as an etch stop layer for the dielectric layer 102.
A mask layer 104, such as a photoresist layer or a hard mask layer, may be formed on the dielectric layer 102 to resist etching. The mask layer 104 may be illuminated and etched to be patterned to define a plurality of openings 110 that expose several regions of the dielectric layer 102.
In other embodiments, the dielectric layer 102 may comprise a stack of multiple layers of different materials. For example, the dielectric layer 102 may be a stack of multiple dielectric layers, wherein two adjacent dielectric layers are different in material, and one of the two dielectric layers is undoped silicon dioxide (SiO) 2 ) Or doped SiO 2 The other layer being a nitride (e.g. Si) 3 N 4 Silicon nitride (SixNy)) or oxynitrideSilicon (SiOxNy)), hafnium oxide (HfO) 2 ) Or zirconium oxide (ZrO) 2 ). Figure 2 is a partial cross-sectional view of a semiconductor structure requiring etching according to another embodiment of the present invention. Referring to fig. 2, the dielectric layer 102 in the semiconductor structure 100b includes a first material layer 102a and a second material layer 102b that are alternately stacked. The first material layer 102a may be undoped silicon dioxide (SiO) 2 ). The second material layer 102b may also be a nitride, such as Si 3 N 4 Silicon nitride (SixNy). Substrate 101 has a high etch selectivity to dielectric layer 102. For example, the substrate 101 may be a silicon layer, such as monocrystalline or polycrystalline silicon, or a doped silicon region. The material of the active region or element 103 may be the same material as the substrate 101, such as silicon or ion doped regions formed using Selective Epitaxial Growth (SEG).
Fig. 3 is a flowchart of a method for etching a high aspect ratio opening according to an embodiment of the invention. Referring to fig. 3, a method according to an embodiment of the present invention may include the following steps:
in step 301, a feed gas comprising an etching gas, an oxygen source gas, and an inert carrier gas is formed into a plasma.
At step 302, a plasma is applied to the dielectric layer to etch the opening. Referring to fig. 4 and 5, plasma 10 is passed through dielectric layer 102 to etch a vertical opening 112.
The etching gas may be one gas or a gas mixture including a plurality of gases. Typical etch gases include one or more fluorocarbons, one or more hydrofluorocarbons, or combinations thereof. For example, the etching gas may be selected from tetrafluoromethane (CF) 4 ) Difluoromethane (CH) 2 F 2 ) Fluoromethane (CH) 3 F) Hexafluorobutadiene (C) 4 F 6 ) Octafluorocyclobutane (C) 4 F 8 ). The etching gas may have different compositions and proportions depending on the material of the dielectric layer being etched. These gases may produce CF as a gaseous precursor for polymer deposition 2 Free radical and CF for etching dielectric layer 3+ Ions. The polymer layer 105 is deposited on the sidewalls 113 of the opening 112 to protect the sidewalls 113 fromAnd is further etched. In one embodiment, the etching gas can include at least one hydrofluorocarbon, such as CH 2 F 2 . Hydrofluorocarbons can be used to help etch dielectrics other than silicon dioxide, such as silicon nitride.
The inert carrier gas may be one or more selected from the group consisting of helium (He), neon (Ne), argon (Ar), krypton (Kr), and xenon (Xe). Inert carrier gases are conventionally used to dilute the etch gas so that excessive etching or deposition does not occur, to stabilize the plasma being generated and to enhance the uniformity of the etch process. Embodiments of the present invention utilize an inert carrier gas in the etching process of high aspect ratio openings, but utilize the characteristics of the inert carrier gas that it is difficult to ionize and it remains electrically neutral. Since the inert carrier gas is difficult to ionize, the ion concentration can be reduced, thereby reducing the chance of expansion and lowering the plasma temperature, while the ion energy is increased. On the other hand, the inert carrier gas is used as an electrically neutral gas, is not easily influenced by charges in the dielectric layer, and can bring etching ions to a deeper surface, thereby being more beneficial to etching with a high aspect ratio. Thanks to the increased ion energy and easier access to deeper surfaces, the etching capacity is improved, while the negative effects on the sidewalls of the openings, such as bending (bowing), tilting (tilting), twisting (distortion) and striation (deformation) are also smaller.
Further research has found that controlling the flow ratio of inert carrier gas to feed gas to 4-21% helps to increase the ion energy and carry ions to deeper surfaces within the opening.
The oxygen source can be oxygen (O) 2 ) Carbon monoxide (CO), or mixtures thereof, in amounts that do not degrade the performance of the etching gas. The oxygen source will react with the carbon and fluorine containing ions (CFx) within the plasma to adjust the amount of carbon and fluorine that adheres to the sidewalls 113 and inhibit etch stop caused by carbon deposits on the bottom 112a of the opening 112.
After providing the above-described feed gas comprising the etching gas, the oxygen source gas, and optionally the inert carrier gas, rf power may be applied to the feed gas to excite the above-described plasma 10. Specifically, a semiconductor structure 100a or 100b (e.g., a wafer) having a dielectric layer 102 to be etched is placed in a plasma reaction chamber of a suitable apparatus for performing an etching process, then a feed gas is flowed into the plasma reaction chamber, and power is applied to ignite a plasma from the feed gas. Generally, a plasma is formed on a surface of a wafer and bias power is supplied to a semiconductor structure containing the wafer or to a support or chuck supporting the semiconductor structure to accelerate ions from a reactant gas toward the surface. Species (e.g., fluorine ions) formed after the feed gas is energized impinge on and react with regions of the dielectric layer 102 exposed via the patterned mask layer 104 to etch away and drive the etch front. By-products, which may be volatile, may be exhausted from the reaction chamber via the outlet.
The plasma may be generated using any known suitable etching apparatus. Those skilled in the art will readily appreciate that depending on the particular etching apparatus used to generate the plasma, various etching parameters, such as gas mixture, temperature, RF power, pressure, and gas flow rate, can be varied to achieve desired etch rates and etch characteristics for the plasma system.
It is understood that the etching process to form the opening 112 includes one or more etching steps.
In a preferred embodiment, the etching gases in step 301 have a common general formula: c 3 HxFy, where x is an integer between 0 and 8, y is an integer between 0 and 8, and x + y is 8. This formula is C 3 The gas of HxFy may include: octafluoropropane (C) 3 F 8 ) Heptafluoropropane (C) 3 HF 7 ) Hexafluoropropane (C) 3 H 2 F 6 ) Pentafluoropropane (C) 3 H 3 F 5 ) Tetrafluoropropane (C) 3 H 4 F 4 ) Trifluoropropane (C) 3 H 5 F 3 ) Difluoropropane (C) 3 H 6 F 2 ) Fluoropropane (C) 3 H 7 F) And propane (C) 3 H 8 )。
In one embodiment, formula C is used 3 The HxFy etching gas can include at least one hydrofluorocarbon, such as C 3 HF 7 ,C 3 H 2 F 6 ,C 3 H 3 F 5 ,C 3 H 4 F 4 ,C 3 H 5 F 3 ,C 3 H 6 F 2 ,C 3 H 7 F, the etching solution contains three elements which are usually needed in etching, namely hydrogen, fluorine and carbon. Hydrofluorocarbons can be used to help etch dielectrics other than silicon dioxide, such as silicon nitride. In alternative embodiments, C may also be used or added 3 H 8 To aid in etching dielectrics other than silicon dioxide. C 3 H 8 Can be used to adjust the ratio of H to F generated after the etching gas is excited. It will be appreciated that the type and/or composition of the etching gas may be adjusted depending on the material it etches. For example, there may be a mixture of several hydrofluorocarbons, or one or more hydrofluorocarbons with C 3 H 8 Mixed, or one or more hydrofluorocarbons with C 3 F 8 And (4) mixing. In one example, the etching gas is C 3 HF 7 (ii) a In another example, the etching gas is C 3 H 2 F 6 (ii) a In another example, the etching gas is C 3 HF 7 And C 3 H 3 F 5 The equal ratio mixed gas of (1); in yet another example, the etching gas is C 3 H 8 ,C 3 HF 7 And C 3 H 3 F 5 The mixed gas of (2). In the case of using a single gas or a mixed gas containing hydrogen, fluorine, and carbon, the gas contains three elements required for etching, that is, hydrogen, fluorine, and carbon, and the ratio of the three elements is appropriate.
In some embodiments, the composition of the etching gas, e.g., the ratio of hydrogen, fluorine, carbon, may be varied at different times during the deep hole etch. For example, in the early stage of etching, the proportion of fluorine is higher, the proportion of hydrogen is lower, and gas with high fluorine content can be used; the proportion of fluorine decreases and the proportion of hydrogen increases toward the latter stage of etching, and a gas having a low fluorine content may be used. Using the general formula C 3 The etching gas of HxFy (including single gas or mixed gas) can still be written as C 3 HxFy, except that, x may be an integer or fraction of 0 to 8The number, y, may be an integer or fraction between 0 and 8.
As mentioned above, the etching gas is selected from the group consisting of those having the general formula C 3 HxFy gas. Advantageously, whatever the gas or combination chosen, these gases are based on carbon chains of 3 carbon atoms. It has been found that this type of gas makes it easy to precisely control the ratio of carbon, hydrogen and fluorine in the gas, thereby enabling precise control of the balance between adsorbed radicals (for forming the polymer layer 105) and etching ions. In particular, when the etching gas comprises a mixture of a plurality of the above gases, which is often the case, the same carbon chain gas molecules are more uniformly plasmatized and thus distributed throughout the opening, which also facilitates the control of the ratio of carbon, hydrogen and fluorine. Using an etching gas of this general formula, a more uniform and thinner polymer layer 105 can be maintained during etching, resulting in better inside profile of the opening and better etching capability. Typically, polymer layer 105 is a mixture of carbon, oxygen, and silicon. In one embodiment, the polymer layer 105 may have a thickness of 0.5 to 4 nm. In one example, the conventional etching gas (fluorocarbon gas) is C 3 HF 7 Or C 3 H 2 F 6 After the replacement, the deep hole etching capability is enhanced, the bottom CD (critical dimension) is expanded by 8%, and the middle expansion is reduced by 10%, so that the bending problem is improved; meanwhile, the damage to the side wall is reduced by 5%, and the smoothness is improved.
Through further research, the flow rate ratio of the inert carrier gas to the feed gas is controlled to be 4-21%, which is beneficial to improving the ion energy and leading ions to be carried to deeper surfaces in the opening, thereby being more beneficial to realizing high aspect ratio etching.
According to one experiment, the etching material was a silicon oxide/silicon nitride multilayer laminate, and the feed gas included fluorocarbon gas, oxygen gas, and krypton gas (Kr). When the flow rate of krypton is 0-7sccm, namely the total flow rate is 0% -3.7%, the yield is not changed and is still only 15%. When the flow rate of krypton is increased from 7.1sccm to 20sccm, namely the total flow rate ratio is increased from 3.8% to 10%, the yield is increased from 15% to 85%. As the krypton flow rate continues to increase from 20.1sccm, yield begins to decrease and the deep hole begins to have an enlarged upper opening. When the krypton gas flow is increased to 50sccm, i.e. the total flow rate is 21.7%, the yield is reduced to less than 10%, and the upper opening portion is damaged.
Therefore, according to an embodiment of the present invention, the etching material is a silicon oxide/silicon nitride multilayer laminated material, the feed gas comprises hydrocarbon fluorine gas, oxygen gas and krypton gas (Kr), wherein the flow rate of the hydrocarbon fluorine gas is 160sccm, the flow rate of the oxygen gas is 20sccm, the flow rate of the krypton gas (Kr) is 20sccm (ratio is 10%), and the yield can reach 85% when deep holes (holes) with a depth of 5 μm and a diameter of 140nm are etched. In contrast, when krypton gas (Kr) is not added, the yield is only 15%, and the polymer blocks the bottom of the deep hole, resulting in insufficient bottom-etch.
According to another embodiment of the present invention, the etching material is a silicon oxide/silicon nitride multilayer laminated material, the feed gas comprises a hydrogen fluoride gas, oxygen gas and xenon gas (Xe), wherein the flow rate of the hydrogen fluoride gas is 160sccm, the flow rate of the oxygen gas is 25sccm, the flow rate of the xenon gas (Xe) is 20sccm (ratio is 9.7%), and the yield can reach 95% when etching a deep trench (trench) with a depth of 4 μm and a width of 150 nm. In contrast, without xenon (Xe) addition, the yield is only 40% and polymer over-deposition results in a facet slope that is too small to etch to the bottom and under-etch.
In summary, the experiment proves that when the inert carrier gas flow rate ratio exceeds 21%, even increases to 30% or higher, the chemical etching effect is attenuated drastically and the inert carrier gas bombardment effect increases due to the low proportion of the main etching gas (fluorocarbon gas), resulting in the physical damage of the upper surface due to the stop of the lower etching. Too high a flow of inert gas, e.g., over 21%, is not suitable for high aspect ratio etching. Therefore, the invention controls the flow ratio of the inert carrier gas to the feed gas to be 4-21%, especially 10-15%, so as to improve the etching yield.
Fig. 6 is a cross-sectional view of the semiconductor structure shown in fig. 1 and 2 after the high aspect ratio etching process provided by the embodiment is performed to form an opening. Fig. 7 is a schematic diagram of a conventional etching method resulting in under-etching of the bottom of an opening during etching. In fig. 6 and 7, the black lattices a and the dark gray lattices B represent regions under-etched, and the light gray lattices C and the white lattices D represent regions normal-etched. As shown in fig. 7, when the inert carrier gas is not used, there are a large number of underetched regions at the bottom of the opening (in the figure, there are many black lattices a and pieces of dark gray lattices B). As shown in fig. 6, when the inert carrier gas of the proper proportion of the embodiment of the present invention is used, the case of insufficient etching (a very small amount of black lattices a and one turn of gray lattices B in the figure) is remarkably improved.
Fig. 8 is a schematic view of a conventional etching method resulting in bending of an opening during etching. Fig. 9 is a schematic illustration of a conventional etching method resulting in twisting of the opening during etching. The same reference numerals in fig. 8 and 9 as in fig. 4 denote corresponding parts. As can be seen by comparing FIG. 4 with FIGS. 8 and 9, FIG. 4 results in an opening 112 that is more straight and of substantially the same diameter throughout the depth without bending and twisting problems; when using compounds of the formula C 3 The effect is more obvious when the etching gas of HxFy is used. In contrast, in fig. 8 and 9, the bottom of the opening 112 is obstructed by etching, which is more likely to cause bending and twisting of the sidewall 113, especially in the case where the polymer of the sidewall is not uniform.
Fig. 10 is a schematic illustration of a conventional etching method resulting in roughness of the sidewalls of the opening during etching. Like reference numerals in fig. 10 to those in fig. 5 denote corresponding parts. As can be seen by comparing FIG. 5 with FIG. 10, the opening 112 formed in FIG. 5 has a smoother inner profile, particularly using C, due to the better etching capability of the bottom of the opening 3 HxFy's etching gas to provide more uniform polymer protection; in contrast, fig. 10 results in a gap 112b at the interface between the two material layers 102a, 102b on the sidewall 113. Thus, the notches 112b may be distributed at each interface of the two material layers alternately stacked, causing the surface of the sidewall 113 to be rough.
Referring to fig. 4 and 5, dielectric layer 102 is etched to form high aspect ratio openings 112, such as contact holes and vias, or other openings such as trenches, that extend to substrate 101 for forming contact holes, for example, for interconnect layers, gate electrodes, capacitor electrodes, vias, and the like, in the fabrication of various devices or circuits, such as 3D NAND, DRAM, CIS (CMOS Image Sensor), and the like. Typically, the opening 112 is etched to a high aspect ratio of about 1:15 to about 1:40 or about 1:20 to about 1:30 with a Critical Dimension (CD) (width) of less than about 100nm or about 25 to 70nm and a depth (d) of, for example, about 1 to 3 μm.
After etching of openings 112 is complete, a dry etch may then be performed, for example, by an oxygen plasma ashing step or by a Piranha (Piranha) cleaning solution (H) 2 SO 4 /H 2 O 2 ) Wet etching is performed to remove the mask layer 104 and the polymer layer 105.
The semiconductor structure 100a or 100b may undergo post-etch processing steps known in the art to fabricate desired components. For example, by coating with a coating of, inter alia, copper, aluminum, silicon, Ti 3 N 4 Is filled and the resulting opening 112 is further processed to form a fill layer, such as a contact or conductive line, for example, to the active region or element 103 in the fabrication of integrated circuit devices, such as memory devices, or with Al, for example, using metal-insulator-metal stacks 2 O 3 、HfO 2 、ZrO 2 、SrTiO 3 And the like, to form a capacitor. The completed semiconductor wafer may be cut into dies, which may then be further processed into semiconductor devices such as integrated circuit chips and incorporated into electronic devices.
This application uses specific words to describe embodiments of the application. Reference throughout this specification to "one embodiment," "an embodiment," and/or "some embodiments" means that a particular feature, structure, or characteristic described in connection with at least one embodiment of the present application is included in at least one embodiment of the present application. Therefore, it is emphasized and should be appreciated that two or more references to "an embodiment" or "one embodiment" or "an alternative embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, some features, structures, or characteristics of one or more embodiments of the present application may be combined as appropriate.
Although the present invention has been described with reference to the present specific embodiments, it will be appreciated by those skilled in the art that the above embodiments are merely illustrative of the present invention, and various equivalent changes and substitutions may be made without departing from the spirit of the invention, and therefore, it is intended that all changes and modifications to the above embodiments within the spirit and scope of the present invention be covered by the appended claims.
Claims (16)
1. A method for etching a high aspect ratio opening includes the following steps:
dry etching the dielectric layer by using a feed gas comprising an etching gas, an oxygen source gas and an inert carrier gas to form an opening, wherein the inert carrier gas accounts for 10-15% of the flow of the feed gas, and the etching gas is selected from a plurality of gases with a general formula of C 3 HxFy gas, where x is an integer between 0 and 8, y is an integer between 0 and 8, and x + y is 8.
2. The method of claim 1, wherein the inert carrier gas is selected from one or more of the following combinations: helium (He), neon (Ne), argon (Ar), krypton (Kr), and xenon (Xe).
3. The method of claim 1, wherein the etching gas comprises:
one or more of a fluorocarbon; and/or
One or more of hydrofluorocarbons.
4. The method of claim 1, wherein a material of the dielectric layer comprises silicon oxide, silicon oxynitride, hafnium oxide, or zirconium oxide.
5. The method of claim 1, wherein the material of the dielectric layer comprises a nitride.
6. The method of claim 1, wherein a polymer layer deposited along sidewalls of the opening during the etching has a thickness between 0.5 nm and 4 nm.
7. The method of claim 1, wherein the opening has an aspect ratio greater than 15: 1.
8. The method of claim 1, wherein the dielectric layer is a single dielectric layer or a composite dielectric layer;
the composite dielectric layer comprises a plurality of vertically stacked dielectric layers, wherein in two adjacent dielectric layers, one dielectric layer is made of silicon oxide, hafnium oxide or zirconium oxide, and the other dielectric layer is made of silicon nitride or silicon oxynitride.
9. A semiconductor device, comprising:
a substrate;
a dielectric layer on the substrate, wherein the dielectric layer has an opening with a high aspect ratio, the opening is formed by dry etching the dielectric layer by using a feed gas of an etching gas, an oxygen source gas and an inert carrier gas, the inert carrier gas accounts for 10% -15% of the feed gas, and the etching gas is selected from a plurality of gases with a general formula of C 3 HxFy, where x is an integer between 0 and 8, y is an integer between 0 and 8, and x + y is 8.
10. The semiconductor device according to claim 9, further comprising: a fill layer located within the opening.
11. The semiconductor device of claim 9, wherein the inert carrier gas is selected from one or more of the following combinations: helium (He), neon (Ne), argon (Ar), krypton (Kr), and xenon (Xe).
12. The semiconductor device of claim 9, wherein the etching gas comprises:
one or more of a fluorocarbon; and/or
One or more of hydrofluorocarbons.
13. The semiconductor device according to claim 9, wherein a material of the dielectric layer comprises silicon oxide, hafnium oxide, or zirconium oxide.
14. The semiconductor device of claim 9, wherein a material of the dielectric layer comprises a nitride.
15. The semiconductor device of claim 9, wherein a thickness of the polymer layer deposited along the sidewalls of the opening during the etching is between 0.5 nm and 4 nm.
16. The semiconductor device of claim 9, wherein the dielectric layer is a single dielectric layer or a composite dielectric layer;
the composite dielectric layer comprises a plurality of vertically stacked dielectric layers, wherein in two adjacent dielectric layers, one dielectric layer is made of silicon oxide, hafnium oxide or zirconium oxide, and the other dielectric layer is made of silicon nitride or silicon oxynitride.
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| US6228775B1 (en) * | 1998-02-24 | 2001-05-08 | Micron Technology, Inc. | Plasma etching method using low ionization potential gas |
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| CN103531464A (en) * | 2012-07-03 | 2014-01-22 | 中国科学院微电子研究所 | Etching method of silicon nitride high depth-width ratio hole |
| CN103578973A (en) * | 2012-07-29 | 2014-02-12 | 中国科学院微电子研究所 | Cyclic etching method for silicon nitride high depth-to-width ratio hole |
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