KR20070022608A - A method for etching high dielectric constant materials - Google Patents

Abstract

In one embodiment, a method is provided for etching a high k dielectric material in a plasma etch reactor, the method comprising plasma etching the high k dielectric material with a plasma gas reaction mixture having BCl ₃ . The high k dielectric material may comprise Al ₂ O ₃ in a stack having a silicon layer. The etching step may include providing a passivation gas, for example C ₂ H _4, and may further comprise supplying a diluent gas, such as, for example, a rare gas of He. In some embodiments, the etching step may be performed in a reactive ion etch process.

Description

A method of etching high dielectric constant materials {A METHOD FOR ETCHING HIGH DIELECTRIC CONSTANT MATERIALS}

1 shows a cross-sectional side view of a partially etched stack having a high dielectric constant layer or high k layer to be etched.

FIG. 2 shows a cross-sectional side view of the laminate after etching the high k layer of FIG. 1.

3 shows a cross-sectional side view of a laminate including a high dielectric constant layer prior to etching.

4 shows a cross-sectional side view of the laminate after etching the high k layer of FIG. 3.

※ Explanation of codes for main parts of drawing

100: laminate 110: mask layer

120, 130: optional layers 120s, 130s: sidewall structures

140: high k layer 150: polysilicon layer

Integrated circuits (ICs) play an important role in the field of modern semiconductor technology. The development of integrated circuits has become possible in modern society with advanced electrical technologies. Applications of integrated circuits are very widespread and their importance affects everyday life from cell phones, digital televisions to flash memory chips in cameras. Such integrated circuits are typically formed on active semiconductor devices with structured processes for a wide range of stacked layers of different materials to allow for memory capacities.

Recently, in modern semiconductor technology, integrated circuits have evolved into smaller devices with more memory. In the manufacture of semiconductor integrated circuits (IC), dielectric materials such as silicon dioxide (SiO ₂ ), silicon nitride (Si ₃ N ₄ ) and silicon oxynitride (SiON) are commonly used. However, as technology evolves, the appearance of IC devices becomes smaller and results in much thinner integrated circuit devices. When conventional IC devices approach a thickness of several nanometers or less, electronic breakdowns typically occur in conventional dielectric materials described above and can no longer provide the required memory storage.

In order to solve the above problems, high dielectric constant materials (high k dielectric materials) have been used in semiconductor chip fabrication with potential applications of memory devices. Examples of high k materials include aluminum oxide, (Al ₂ O ₃ ), hafnium oxide (HfO ₂ ), zirconium oxide (ZrO ₂ ) and mixtures thereof, and metal silicates such as HfSi _x O _y , ZrSiO ₄ and mixtures thereof Include them.

The high k materials described above are sold for use in IC applications, but it is known to those skilled in the art that it is very difficult to dry etch. High k materials are typically very stable and resistant to most etching reactions (due to their chemical inertness), so they have been used as etch stop layers and hard mask layers in plasma etching and other materials.

Conventional deposition processes preferably produce high k dielectric films on a substrate (eg, a silicon wafer), but unwanted reactions may be formed in these films and other parts of the reaction chamber. Accumulation of such unwanted residues can lead to particle shedding, deposition uniformity degradation, and these effects can result in wafer defects and subsequent device defects.

With respect to high dielectric constant materials, aluminum oxide (Al ₂ O ₃ ) with one of the slowest etch rates is usually known to those skilled in the art. Typically, strong plasma conditions generate high chuck bias voltages, resulting in improved ion sputtering and sputter induced etch.

Conventional methods of etching high k dielectric materials typically include chlorine (Cl ₂ ) and fluorine gas at high wafer temperatures. There were many disadvantages to these methods. Chemical agents based on Cl ₂ aggressively etch polysilicon, resulting in low selectivity to polysilicon. The etched high k dielectric layers may form residue on the wafer after etching, resulting in low capacitive structures or defective wafers. Specifically, with respect to aluminum oxide, this means that there is a great difficulty in etching Al ₂ O ₃ on top of the thin poly 1 layer for flash memory and other related applications. Typically fluorine has been shown to be ineffective in etching high k dielectric materials. Fluorine usually forms non-volatile metal fluorides and is therefore difficult to remove from the reactor.

Flash memory stacks for nodes larger than 55nm consist of poly2 / Al ₂ O ₃ (or other high k dielectric material) / poly 1. It is known to those skilled in the art that Al ₂ O ₃ differs from poly in the film stack and is difficult to etch. Important to successfully etch high k dielectric materials such as Al ₂ O _{3 on} top of a thin layer of poly 1 layer of a new flash memory film stack is to have a reasonable Al ₂ O ₃ etch rate and high selectivity for polysilicon. Find a process.

As will be appreciated by those skilled in the art, there is a need for methods capable of etching high dielectric constant materials. Preferably, such etching methods should not have undesirable properties that promote unwanted residues that can form wafer defects. Moreover, there is a need for methods of etching high dielectric constant materials, such as aluminum oxide, which are cost effective, have high selectivity, and have moderately high etch rates.

It is an object of the present invention to provide a method for etching high dielectric constant materials that do not have properties that promote unwanted residues that can form wafer defects, are cost effective, have high selectivity, and have moderately high etch rates. will be.

In one embodiment, a method is provided for etching a high k dielectric material in a plasma etch reactor, the method comprising plasma etching the high k dielectric material with a plasma gas reaction mixture having BCl ₃ . The high k dielectric material may be Al ₂ O ₃ in a stack having at least one silicon layer. Hydrocarbons, ie, passivation gases such as CH ₄ , C ₂ H ₄ , and the like, may be provided for etching with diluent gases of noble gases such as, for example, He. In some embodiments, the etching can be performed in a reactive ion etch process.

1 shows a cross-sectional side view of a partially etched stack 100 having a high dielectric constant layer or high k layer 140 to be etched. In this embodiment, mask layer 110 is patterned on top of high k layer 140. Additional optional layers 120, 130 may be located between mask layer 110 and high k layer 140. In one embodiment, the mask layer 110 is typically a hard mask, such as a plasma enhanced chemical vapor deposition oxide or PECVD oxide, BSG or boron doped spin-on glass, another oxide hard mask, silicon nitride, or other hard mask. . In one embodiment, the selection layer 120 is tungsten (W) and the selection layer 130 is titanium nitride (TiN). The high k layer is polysilicon layer 150. FIG. 2 shows the stack 200 after etching the high k layer 140 of FIG. 1. The high k layer 240 being etched is etched into the underlying polysilicon layer 150, which may be part of the substrate in some embodiments. A barrier layer (not shown), such as silicon nitride (SiN) or other barrier layer material, may be located between the high k layer 140 and the polysilicon layer 150. In this embodiment, high k layer 140 is etched into the barrier layer.

Materials with high dielectric constants are referred to as high k dielectric materials. High k dielectric materials typically have a dielectric constant greater than 4, in some embodiments more preferably greater than 5, and in some embodiments even more preferably 7 or more. In some embodiments, the high k material is preferably at least one selected from the group consisting of Al ₂ O ₃ , HfO ₂ , AlHf _x O _y , ZrO ₂ , HfSi _x O _y , ZrSi _x O _y and mixtures thereof. It is a member.

Referring to FIG. 1, in one embodiment, etching of the high k material layer 140 is performed with BCl ₃ . In the case of the high k material Al ₂ O ₃ , BCl ₃ etches Al ₂ O ₃ by the formation of volatile AlCl ₃ . Passivation gas such as C ₂ H ₄ , CH ₄ or other hydrocarbons to provide passivation of the sidewall structures 120s and 130s of the layers 120 and 130 and to improve selectivity to the underlying polysilicon layer 150. Can be introduced. The ratio of BCl ₃ to C ₂ H ₄ or the ratio of BCl ₃ to CH ₄ is chosen to provide the desired etch rate and high selectivity for the polysilicon layer 150. Hydrocarbon additives reduce the etch rate of the polysilicon layer 150 to improve selectivity. One advantage of C ₂ H ₄ is that it is a polymer precursor of polypropylene and has a content similar to photoresist.

Diluent gases such as He may be introduced with a passivation such as C ₂ H ₄ , for example. The atomic ratio of C ₂ H ₄ to He may be about 2.7% to 1 in some embodiments. Other ratios may be possible. In one specific example, C ₂ H ₄ : He, which comprises 2.7% C ₂ H ₄ and 97.3% He, for a dilution factor of 37 is commercially available.

In other embodiments, the high k material layer 140 may be etched using a gas mixture comprising another halogen containing gas along with a passivation gas comprising other hydrocarbons. Thus, in some embodiments, the passivation gas may comprise an inert gas selected from the group consisting of helium, argon, neon, xenon and krypton.

Referring to FIG. 1, in some embodiments the high k layer 140 etching process may be performed using reactive ion etching. All etching steps can be performed in a single plasma etch chamber, such as a DPS etch reactor, or reactive ion etch (RIE), all available from Applied Materials, Inc. of Santa Clara, California. In one RIE process, the processing parameters include a source power of about 0 W, about 200 W bias power, a chamber pressure of about 25 mT, and about 30 sccm BCl ₃ at about 80 ° C. This provides a polysilicon layer 150 of less than 100 kV with a low sidewall taper and good sidewall profile at an etch rate of about 150 kPa / min. The bias power can range from about 150W to about 300W. In general, sidewall passivation of the W layer 120 and the TiN layer 130 is more difficult to control at higher cathode temperatures than at low temperatures of about 100 ° C. or less. For example, 80 ° C. provides good passivation of the W layer 120 and the TiN layer 130 to provide a good etch profile in the RIE process.

In another embodiment, an inductively coupled mode having a source power of about 800 W at 10 mT with a BCl ₃ of about 60 sccm at about 250 ° C. and a bias power of 200 W provides good sidewall profiles. The inductively coupled mode provides a higher etch rate of the Al ₂ O ₃ high k layer 140, while the RIE mode described above provides about three times higher selectivity for the polysilicon layer 150. In some embodiments, the bias power range is about 150-300W.

In some embodiments, the etching can be performed in a two step etch process with a main etch and an over etch step, as known in the art. The main etch is designed to etch the high k layer 140. The over etching step ensures uniform penetration of the high dielectric constant layer 140 to the polysilicon layer 150 or the barrier layer (not shown in FIG. 1).

High k dielectric materials such as Al ₂ O ₃ may be etched at temperatures as high as about 250 ° C. or as low as about 80 ° C. After the main etch and over etch steps are completed, dechucking and cleaning of the chamber may be performed as desired. In some embodiments a low temperature operation, for example as low as about 100 ° C. or as low as 80 ° C., may facilitate more rapid cooling and dechucking to improve wafer throughput.

In some embodiments, a hydrocarbon passivation gas comprising hydrogen and carbon may be added to the gas mixture at a chamber pressure of 40 mT or less. The passivation gas is a hydrocarbon, such as — (CH ₂ ) _n gas, which is ethylene in some embodiments, but other hydrocarbons may be used, for example methane.

To etch Al ₂ O ₃ at an appropriate etch rate and high selectivity to polysilicon, BCl ₃ or boron trichloride is used. Cl ₂ gas is typically used to etch high k dielectric materials, but can aggressively etch polysilicon and other materials. Since boron helps to reduce the polysilicon etch rate by forming the silicon-boron combination, it can increase the selectivity and provide successful results when etching materials with high dielectric constants. Boron trichloride can chemically etch Al ₂ O ₃ by the formation of volatile AlCl ₃ . The ratio of BCl ₃ to C ₂ H ₄ / He or CH ₄ is chosen to provide a suitable Al ₂ O ₃ etch rate and high selectivity for polysilicon. Formation of B ₂ O ₃ and B-Si complexes will promote high selectivity for polysilicon. Hydrocarbon passivation gases such as C ₂ H ₄ / He, CH _4, etc. reduce the polysilicon etch rate to improve selectivity, reduce the etch rate when the polysilicon layer is exposed, and in other embodiments one or more polysilicon Prevents lateral penetration of sidewalls 120s, 130s of other layers 120, 130, which may include layers (not shown in FIG. 1).

As mentioned above, in addition to the reactants described in the present invention, inert diluent gases such as helium, argon, neon, krypton and xenon may be added. Inert diluent gases are needed for stability reasons and can alter plasma properties. The concentration of the inert gas can range from 1.0% to about 3.0% for helium. Other shock inert diluent gases may also be possible.

In some embodiments, conventional chamber cleaning may be performed after an etching process.

In other embodiments, HBr may be used to etch high k dielectric materials. As mentioned above, passivation gas and diluent gas may be used. For Al ₂ O ₃ high k materials, HBr etches Al ₂ O ₃ by the formation of volatile AlBr ₃ . The ratio of HBr to C ₂ H ₄ is chosen to provide a suitable etch rate. The diluent can be an inert gas such as He having a ratio of C ₂ H ₄ to He of about 2.7% to 1 as described above.

Referring to FIG. 3, in one embodiment, a high k material is located between two layers of polysilicon, poly1 is indicated by reference number 341, and poly2 is indicated by reference number 342. poly2 342 is located above the high k layer 340 and poly1 341 is located below the high k layer 340. According to one embodiment, the stack 300 is etched using a mask 310, which may be a hard mask in some embodiments. The etching of poly2 342 is stopped in a high k layer 340, such as, for example, Al ₂ O ₃ layer, so that the etching has a high selectivity for Al ₂ O ₃ . Al ₂ O ₃ etching is followed and has high selectivity for poly2 342 and poly1 341 and stops at poly1 341. An optional SiN barrier layer 322 may be used. Poly1 341 may then be etched against underlying gate oxide layer 347.

To achieve high etch selectivity in the Al ₂ O ₃ etch, the reaction mixture may have BCl ₃ and possibly a hydrocarbon passivation gas such as C ₂ H ₄ . The Al ₂ O ₃ layer 340 may be etched with C ₂ H ₄ diluted with BCl ₃ etchant and He. Dilution is particularly effective for low flow rates of C ₂ H ₄ . The process may include two steps, a main etch, and a subsequent over etch that may have the same reaction mixture as the main etch. In some embodiments, a temperature greater than 100 ° C. provides good results with a temperature of 150 ° C. which gives better results.

4 shows a cross-sectional side view of the stack 400 which is etched after etching the high k layer of FIG. To form the etch stack 400, a high k layer 440 to be etched is formed after the poly2 layer 442 to be etched. The etched barrier layer 444 is formed after etching the high k layer 440, and the etched poly1 layer 441 is formed of the poly2 etched, the high k layer 440 etched and the barrier layer 444 etched. It is formed after etching. Mask 410 is used to define poly2 etched, high k layer 440 etched, barrier layer 444 etched, and poly1 layer 441 etched.

Typically, processes associated with polysilicon use chemical plasma etching with decoupled plasma source power and bias power. However, some of the embodiments described above may be performed by reactive ion etching using only bias power. In certain embodiments, reactive ion etching of high k materials provides greater selectivity to polysilicon. In one exemplary embodiment, the process window has a bias power of about 100 W to about 400 W, a source power of about 0 W, and a BCl ₃ at a flow rate of about 20 sccm to about 200 sccm at about 30 ° C. to about 350 ° C.

In some embodiments it may be possible to use a chemical plasma etch for the main etch process and then switch to reactive ion etch near the endpoint, or to the over etch step described above.

One of several advantages of certain embodiments described above is that the main etchant gas mixture can be formed without fluorine, which can react with Al ₂ O ₃ to form aluminum fluoride contaminants.

The foregoing detailed description is merely illustrative of the invention and is not intended to limit the invention to the disclosed configurations disclosed. Embodiments disclosed herein are not limited to the specific stacking configurations illustrated. Other stacking configurations and embodiments may be possible. Modifications and variations apparent to those skilled in the art are within the spirit and character of the invention as defined in the appended claims.

The present invention provides a method of etching high dielectric constant materials that do not have properties that promote unwanted residues that can form wafer defects, are cost effective, have high selectivity, and have moderately high etch rates. It can be effective.

Claims (35)

A method for etching high k dielectric materials in a plasma etch reactor, the method comprising: Plasma etching the high k dielectric material using a plasma gas reaction mixture comprising BCl ₃ . The method of claim 1, And wherein said etching step comprises providing a passivation gas. The method of claim 2, Said high k dielectric material is selected from the group consisting of aluminum oxide, hafnium oxide, zirconium oxide, and mixtures thereof. The method of claim 3, wherein And the dielectric material is aluminum oxide. The method of claim 4, wherein And said passivation gas comprises C ₂ H ₄ . The method of claim 2, And said passivation gas comprises a hydrocarbon. The method of claim 6, And said passivation gas comprises C ₂ H ₄ . The method of claim 7, wherein And said etching step further comprises supplying a diluent gas comprising a rare gas. The method of claim 8, Supplying the diluent gas comprises supplying He. The method of claim 9, And etching using an oxide hard mask. The method of claim 9, And the high k dielectric material comprises Al ₂ O ₃ . The method of claim 11, And the etching step comprises using a reactive ion etching process. The method of claim 12, And said etching step comprises etching within a range of about 250 [deg.] C. The method of claim 12, Wherein the etching step comprises etching at about 100 ° C. or less. The method of claim 14, Wherein the etching step comprises etching at about 80 ° C. The method of claim 6, And said passivation gas comprises CH ₄ . The method of claim 16, And the high k dielectric material comprises Al ₂ O ₃ . The method of claim 17, And the etching step comprises using a reactive ion etching process. The method of claim 18, And said etching step comprises etching within a range of about 250 [deg.] C. The method of claim 18, Wherein the etching comprises etching at about 100 ° C. or less. The method of claim 20, Wherein the etching step comprises etching at about 80 ° C. The method of claim 2, Etching the high k dielectric material comprises etching a stack comprising silicon. The method of claim 22, Etching the high k dielectric material comprises etching the high k dielectric material under a silicon containing layer. The method of claim 23, Etching the high k dielectric material comprises etching the high k dielectric material against a silicon containing material below the high k dielectric material. The method of claim 23, Etching the high k dielectric material comprises etching the high k dielectric material against a barrier layer below the high k dielectric material. A method for etching high k dielectric materials in a plasma etch reactor, the method comprising: Plasma etching the Al ₂ O ₃ layer in the silicon-containing laminate using a plasma formed from BCl ₃ , a hydrocarbon passivation gas, and a noble gas. The method of claim 26, And said rare gas comprises He. The method of claim 27, And said hydrocarbon passivation gas comprises C ₂ H ₄ . The method of claim 27, Wherein said hydrocarbon passivation gas comprises CH ₄ . The method of claim 26, And the etching step comprises using a reactive ion etching process. A method for etching high k dielectric materials in a plasma etch reactor, the method comprising: Plasma etching the high k dielectric material with a first plasma gas reaction mixture comprising HBr, a passivation gas comprising a hydrocarbon, and a rare gas diluent. The method of claim 31, wherein And said passivation gas comprises C ₂ H ₄ . The method of claim 31, wherein And said rare gas diluent comprises He. The method of claim 31, wherein Etching the high k dielectric material comprises etching a stack comprising silicon. The method of claim 31, wherein And the etching step comprises using a reactive ion etching process.

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